KR100450845B1 - Fabrication method of semiconductor device - Google Patents
Fabrication method of semiconductor device Download PDFInfo
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- KR100450845B1 KR100450845B1 KR10-2002-0019936A KR20020019936A KR100450845B1 KR 100450845 B1 KR100450845 B1 KR 100450845B1 KR 20020019936 A KR20020019936 A KR 20020019936A KR 100450845 B1 KR100450845 B1 KR 100450845B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title claims description 7
- 239000002184 metal Substances 0.000 claims abstract description 95
- 229910052751 metal Inorganic materials 0.000 claims abstract description 95
- 239000010410 layer Substances 0.000 claims abstract description 56
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims 2
- 238000001465 metallisation Methods 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
반도체 소자 제조 방법에 관한 것으로, 그 목적은 비아 형성을 위한 상부절연막 식각시 하부금속배선 주변의 노출된 층간절연막이 함께 식각되는 파임현상을 방지하는 데 있다. 이를 위해 본 발명에서는, 하부 금속배선 및 층간절연막을 포함한 반도체 구조물 상부 전면에 금속층을 형성하는 단계; 하부 금속배선 상의 금속층이 남도록 금속층을 선택적으로 식각함으로써, 금속층으로 매립된 비아를 형성하는 단계; 금속층을 포함한 상부 전면에 금속배선막을 형성하고 비아 상부를 포함하는 영역을 제외한 나머지 금속배선막을 식각하여 비아를 통해 하부 금속배선과 연결되는 상부 금속배선을 형성하는 단계를 포함하여 반도체 소자를 제조한다.The present invention relates to a method of manufacturing a semiconductor device, and an object thereof is to prevent a phenomenon in which the exposed interlayer insulating layer around the lower metal wiring is etched together when the upper insulating layer is etched to form vias. To this end, in the present invention, forming a metal layer on the upper surface of the semiconductor structure including a lower metal wiring and an interlayer insulating film; Selectively etching the metal layer to leave a metal layer on the lower metallization to form vias embedded in the metal layer; Forming a metal interconnection film on the upper front surface including a metal layer and etching the remaining metal interconnection film except for the region including the upper via to form an upper metal wiring connected to the lower metal wiring through the via to manufacture a semiconductor device.
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 금속물질로 매립된 비아를 형성하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming vias filled with a metal material.
반도체 소자가 점차 고집적화, 다층화됨에 따라 중요한 기술의 하나로 다층 배선 기술이 등장하게 되었는데, 이와 같은 다층 배선 기술은 금속 배선층과 절연막층을 회로 소자가 형성된 반도체 기판 상부에 교대로 형성하며, 절연막에 의해 분리된 금속 배선층 사이를 비아를 통해 전기적으로 접속함으로써 회로 동작이 이루어지도록 하는 것이다.As semiconductor devices have been increasingly integrated and multilayered, multilayer wiring technology has emerged as one of the important technologies. The multilayer wiring technology alternately forms a metal wiring layer and an insulating film layer on the semiconductor substrate on which the circuit elements are formed, and is separated by an insulating film. The circuit operation is performed by electrically connecting the interconnected metal wiring layers through vias.
포토리소그래피 공정에 의해 금속배선의 상부에 비아를 형성하는데 있어서 최근 반도체 소자의 고집적화 추세에 따라 금속배선의 선폭이 좁아질수록 금속배선상부의 정확한 위치에 비아를 형성하는 것이 기술적으로 매우 어려워지고 있다. 또한, 비아의 종횡비가 금속배선의 종횡비보다 크기 때문에 비아 형성을 위한 포토리소그래피 작업이 금속배선 형성작업보다 훨씬 어렵다.In forming vias on top of metal wirings by a photolithography process, according to the recent trend of higher integration of semiconductor devices, it is technically very difficult to form vias at precise positions on metal wirings as the line widths of metal wirings become narrower. In addition, since the aspect ratio of the via is larger than the aspect ratio of the metal wiring, the photolithography operation for forming the via is much more difficult than the metal wiring forming operation.
이러한 이유로 선폭이 매우 좁은 금속배선 상부에서는 금속배선보다 더 넓은 폭으로 비아를 형성한다.For this reason, the vias are formed in a wider width than the metal wires on the metal wires having a very narrow line width.
도 1은 종래 반도체 소자 제조 방법에 따라 금속배선보다 더 큰 폭으로 형성된 비아가 도시된 단면도이다.1 is a cross-sectional view of a via formed in a larger width than a metal wiring according to a conventional semiconductor device manufacturing method.
도 1에 도시된 바와 같이, 반도체 기판(1)의 구조물 상부에는 하부절연막(2)이 형성되어 있고, 하부절연막(2)의 소정부분 상에는 하부금속배선(3)이 형성되어 있으며, 하부금속배선(3)을 제외한 하부절연막(2) 상에는 층간절연막(4)이 형성되어 있다. 층간절연막(4) 상에는 상부절연막(5)이 형성되어 있되, 하부금속배선(3)의 상부에는 이보다 더 넓은 폭으로 상부절연막(5)이 제거되어 비아(6)가 형성되어 있다. 즉, 하부금속배선(3)의 폭은 A로, 비아(6)의 폭은 B로 도시되어 있다.As shown in FIG. 1, a lower insulating film 2 is formed on the structure of the semiconductor substrate 1, and a lower metal wiring 3 is formed on a predetermined portion of the lower insulating film 2, and the lower metal wiring is formed. The interlayer insulating film 4 is formed on the lower insulating film 2 except for (3). The upper insulating film 5 is formed on the interlayer insulating film 4, but the upper insulating film 5 is removed on the upper portion of the lower metal wiring 3 to have a wider width so that the via 6 is formed. That is, the width of the lower metal wiring 3 is shown as A, and the width of the via 6 is shown as B. FIG.
그러나 이와 같은 종래방법에서는 비아(6) 형성을 위한 상부절연막(5) 식각시 하부금속배선(3) 주변의 노출된 층간절연막이 함께 식각되는 파임현상이 발생하는데, 이로 인해 금속배선간 누설전류가 증가하는 문제점이 있다.However, in such a conventional method, when the upper insulating layer 5 is etched to form the vias 6, a dig phenomenon occurs in which the exposed interlayer insulating layer around the lower metal line 3 is etched together, which causes leakage current between the metal lines. There is an increasing problem.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 층간절연막의 파임현상을 방지하는 데 있다.The present invention has been made to solve the above problems, and an object thereof is to prevent the pitting phenomenon of the interlayer insulating film.
도 1은 종래 반도체 소자 제조 방법에 따라 금속배선보다 더 큰 폭으로 형성된 비아가 도시된 단면도이다.1 is a cross-sectional view of a via formed in a larger width than a metal wiring according to a conventional semiconductor device manufacturing method.
도 2a 내지 2d는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는, 하부 금속배선 및 층간절연막을 포함한 반도체 구조물 상부 전면에 금속층을 형성하는 단계; 하부 금속배선 상의 금속층이 남도록 금속층을 선택적으로 식각함으로써, 금속층으로 매립된 비아를 형성하는 단계; 금속층을 포함한 상부 전면에 금속배선막을 형성하고 비아 상부를 포함하는 영역을 제외한 나머지 금속배선막을 식각하여 비아를 통해 하부 금속배선과 연결되는 상부 금속배선을 형성하는 단계를 포함하여 반도체 소자를 제조한다.In order to achieve the above object, in the present invention, forming a metal layer on the upper surface of the semiconductor structure including a lower metal wiring and an interlayer insulating film; Selectively etching the metal layer to leave a metal layer on the lower metallization to form vias embedded in the metal layer; Forming a metal interconnection film on the upper front surface including a metal layer and etching the remaining metal interconnection film except for the region including the upper via to form an upper metal wiring connected to the lower metal wiring through the via to manufacture a semiconductor device.
이 때, 금속층을 선택적으로 식각할 때에는 금속층을 하부 금속배선보다 넓은 폭으로 남기고 나머지 영역을 건식 식각으로 제거하고, 건식 식각 과정에서 제거된 금속층 하부에 있던 층간절연막이 소정두께 더 식각되는 것이 바람직하다.In this case, when the metal layer is selectively etched, it is preferable to leave the metal layer in a wider width than the lower metal wiring, and to remove the remaining regions by dry etching, and to further etch the interlayer insulating film under the metal layer removed during the dry etching process. .
이하, 본 발명에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail.
도 2a 내지 2d는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판(11)의 구조물, 즉 개별 소자가 형성된 반도체 기판 또는 금속 배선층 상부에 산화막 등으로 이루어진 하부절연막(12)을 형성하고, 하부절연막(12) 상에 금속배선막을 형성하고 패터닝하여 하부 금속배선(13)을 형성한다.First, as shown in FIG. 2A, a lower insulating film 12 made of an oxide film or the like is formed on a structure of the semiconductor substrate 11, that is, on a semiconductor substrate or a metal wiring layer on which individual elements are formed, and then, The metal wiring layer is formed and patterned to form the lower metal wiring 13.
이 때 하부 금속배선(13)으로는 Al, Al합금, 또는 Cu 등을 사용할 수 있다.In this case, Al, Al alloy, Cu, or the like may be used as the lower metal wiring 13.
이어서, 하부 금속배선(13)을 포함한 상부 전면에 층간절연막(14)을 증착하고 하부 금속배선(13)의 상면이 노출될 때까지 화학기계적 연마하여층간절연막(14)의 상면이 하부 금속배선(13)과 동일한 높이가 되도록 평탄화한다.Subsequently, an interlayer insulating film 14 is deposited on the entire upper surface including the lower metal wiring 13 and chemically mechanically polished until the top surface of the lower metal wiring 13 is exposed, so that the top surface of the interlayer insulating film 14 is lower metal wiring ( Flatten it to the same height as 13).
다음, 도 2b에 도시된 바와 같이, 하부 금속배선(13) 및 층간절연막(14)의 상부 전면에 금속층(15)을 증착한 후, 금속층(15) 상에 감광막을 도포하고 노광 및 현상하여 비아로 예정된 영역의 상부에 해당하는 일부분을 제외한 나머지 부분이 제거된 감광막 패턴(16)을 형성한다.Next, as shown in FIG. 2B, after depositing the metal layer 15 on the upper front surface of the lower metal wiring 13 and the interlayer insulating film 14, a photosensitive film is coated on the metal layer 15, exposed and developed, and then vias. The photoresist pattern 16 may be formed to remove portions other than the portion corresponding to the upper portion of the predetermined region.
금속층(15) 증착 전에 하부 금속배선(13) 상면에 자연적으로 형성된 산화막까지 모두 제거한 후, 금속층을 증착하는 것이 바람직하다.Before the deposition of the metal layer 15, it is preferable to remove all the oxide films naturally formed on the upper surface of the lower metal wiring 13, and then deposit the metal layer.
금속층(15) 증착 후에는 300~450℃의 온도로 10~60분의 시간 동안 열처리하여 금속층(15)과 하부 금속배선(13)과의 접착력을 향상시킬 수도 있다.After the deposition of the metal layer 15, heat treatment may be performed at a temperature of 300 to 450 ° C. for 10 to 60 minutes to improve adhesion between the metal layer 15 and the lower metal wiring 13.
감광막 패턴(16)은 오프닝된 부분인 비아 예정 부분의 폭이 하부 금속배선(13)의 폭보다 더 넓도록 형성한다. 금속층(15)으로는 W, Al, Al합금, 또는 Cu 등을 사용한다.The photoresist pattern 16 is formed such that the width of the via predetermined portion, which is the opened portion, is wider than the width of the lower metal wiring 13. W, Al, Al alloy, Cu, or the like is used as the metal layer 15.
다음, 도 2c에 도시된 바와 같이, 감광막 패턴(16)을 마스크로 하여 노출된 금속층(15)을 건식 식각하여 비아로 예정된 영역에만 금속층(15)을 남겨둠으로써, 내부가 금속물질로 충진된 비아(100)를 형성한다. 이 때 건식 식각과정에서 노출된 금속층(15)이 모두 식각된 다음에는 그 하부의 층간절연막(14)이 소정두께 더 식각된다.Next, as shown in FIG. 2C, the metal layer 15 is dry-etched using the photoresist pattern 16 as a mask to leave the metal layer 15 only in a region intended as a via, thereby filling the inside with a metal material. Form via 100. At this time, after all of the exposed metal layer 15 in the dry etching process is etched, the lower interlayer insulating layer 14 is further etched to a predetermined thickness.
이어서, 비아(100) 및 층간절연막(14)의 상부 전면에 상부절연막(17)을 비아 내에 충진된 금속층보다 두껍게 증착하고, 도 2d에 도시된 바와 같이 비아의 상면이 노출될 때까지 상부절연막(17)을 화학기계적 연마하여 상면을 평탄화시킨 후,세정을 수행한다.Subsequently, the upper insulating layer 17 is deposited on the upper surface of the via 100 and the interlayer insulating layer 14 thicker than the metal layer filled in the via, and as shown in FIG. 2D, until the upper surface of the via is exposed. 17) is chemical mechanically polished to planarize the upper surface, and then washed.
이어서, 평탄화된 비아 및 상부절연막(17)의 상면에 금속배선막을 증착하고 부분적으로 식각하여 비아(100)를 통해 하부 금속배선(13)과 연결되는 상부 금속배선(18)을 형성한다.Subsequently, a metal wiring film is deposited on the top surface of the planarized via and the upper insulating layer 17 and partially etched to form an upper metal wiring 18 connected to the lower metal wiring 13 through the via 100.
이 때 상부 금속배선(18)으로는 Al, Al합금, 또는 Cu 등을 사용할 수 있다.In this case, Al, Al alloy, Cu, or the like may be used as the upper metal wiring 18.
또한, 상부 금속배선(18) 형성을 위한 금속배선막 증착 전에 비아(100) 상면에 자연적으로 형성된 산화막까지 모두 제거한 후, 금속배선막을 증착하는 것이 바람직하다.In addition, it is preferable to remove the oxide film formed on the upper surface of the via 100 before the deposition of the metal wiring film for forming the upper metal wiring 18, and then deposit the metal wiring film.
금속배선막 증착 후에는 250~400℃의 온도로 10~60분의 시간 동안 열처리하여 금속배선막과 비아 내에 충진된 금속층과의 접착력을 향상시킬 수도 있다.After deposition of the metal wiring film, heat treatment may be performed at a temperature of 250 to 400 ° C. for 10 to 60 minutes to improve adhesion between the metal wiring film and the metal layer filled in the via.
상술한 바와 같이, 본 발명에서는 금속층을 먼저 형성한 후 비아로 예정된 부분을 제외한 나머지 금속층을 제거함으로써 내부가 금속층으로 충진된 비아를 형성하기 때문에, 종래기술에서 문제가 되었던 비아 형성을 위한 상부절연막 식각시 하부금속배선 주변의 노출된 층간절연막이 함께 식각되는 파임현상이 방지되는 효과가 있으며, 따라서 금속배선간 누설전류 증가 문제를 해결하는 효과가 있다.As described above, in the present invention, since the via is filled with the metal layer by forming the metal layer first and then removing the remaining metal layer except for the portion intended as the via, the upper insulating layer etch for forming the via, which has been a problem in the prior art. When the exposed interlayer dielectric film around the lower metal wiring is etched together, there is an effect of preventing the phenomena, and thus the problem of increasing the leakage current between the metal wiring.
Claims (3)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR890007384A (en) * | 1987-10-22 | 1989-06-19 | 강진구 | Manufacturing method of semiconductor multilayer wiring apparatus |
| KR19990001665A (en) * | 1997-06-17 | 1999-01-15 | 윤종용 | Method for manufacturing metal wiring in semiconductor device |
| US5895263A (en) * | 1996-12-19 | 1999-04-20 | International Business Machines Corporation | Process for manufacture of integrated circuit device |
| KR100246100B1 (en) * | 1997-12-31 | 2000-03-15 | 김영환 | Multi-wiring of semiconductor device |
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2002
- 2002-04-12 KR KR10-2002-0019936A patent/KR100450845B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR890007384A (en) * | 1987-10-22 | 1989-06-19 | 강진구 | Manufacturing method of semiconductor multilayer wiring apparatus |
| US5895263A (en) * | 1996-12-19 | 1999-04-20 | International Business Machines Corporation | Process for manufacture of integrated circuit device |
| KR19990001665A (en) * | 1997-06-17 | 1999-01-15 | 윤종용 | Method for manufacturing metal wiring in semiconductor device |
| KR100246100B1 (en) * | 1997-12-31 | 2000-03-15 | 김영환 | Multi-wiring of semiconductor device |
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