KR19990001665A - Method for manufacturing metal wiring in semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing metal wiring in a semiconductor device, and in particular, in the multilayer wiring process, a first metal pattern is formed on the first insulating film for insulating the lower structures and the upper wiring layers to a height less than a desired wiring thickness, and then Forming a second insulating film on the resultant, etching the second insulating film until the surface of the first metal pattern is exposed, and then etching the exposed portion of the first metal pattern, and then After the second metal layer is formed, a second metal pattern is formed on the first metal pattern using a photolithography and an etching process. Therefore, the present invention can improve the aspect ratio between the interlayer insulating film and the metal, thereby increasing the reliability of the semiconductor device.

Description

Method for manufacturing metal wiring in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring manufacturing method of a semiconductor device, and more particularly, to a metal wiring manufacturing method of a semiconductor device that achieves a desired metal thickness by performing a plurality of metal wiring manufacturing processes in a metal wiring manufacturing process.

In recent years, as semiconductor design rules have become increasingly finer, semiconductor devices have a multilayered and complicated structure. In addition, in order to achieve a high current density, the width of the metal wiring is reduced while increasing the thickness of the metal. However, when the interlayer metal layer is formed by chemical vapor deposition in a state in which the metal thickness is increased, protrusions are often generated at the metal edges, causing problems such as voids and gapfill to fill them.

SUMMARY OF THE INVENTION An object of the present invention is to provide a metal wiring manufacturing method of a semiconductor device which can increase the aspect ratio between an insulating film and a metal by forming a plurality of metal patterns in a metal wiring manufacturing process in order to solve the problems of the prior art as described above.

In order to achieve the above object, the present invention includes the steps of depositing and planarizing the first insulating film for insulating the lower structures and the upper wiring layer in the multi-layer wiring process; Forming a first metal pattern on the first insulating layer at a height equal to or less than a desired wiring thickness, and then forming a first metal pattern using a photolithography and an etching process; Forming a second insulating film on the resultant product; Etching the second insulating layer until the surface of the first metal pattern is exposed; Etching the exposed portion of the first metal pattern; Forming a second metal layer on the resultant, and forming a second metal pattern on the first metal pattern by using a photolithography and an etching process; And forming a third insulating film on the resultant, and performing a planarization process.

1 to 7 are vertical cross-sectional views for sequentially explaining a method for manufacturing metal wiring of a semiconductor device according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: first insulating film 12: first metal layer

14 second insulating film 16 second metal layer

18: third insulating film

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 to 7 are vertical cross-sectional views for sequentially explaining a method for manufacturing metal wiring of a semiconductor device according to the present invention.

First, a semiconductor element (not shown) is manufactured by performing a series of semiconductor element manufacturing processes on a semiconductor substrate. Next, after the first insulating film 10 is formed on the semiconductor device, a planarization process is performed.

Referring to FIG. 1, when the thickness of the metal wire to be formed in the semiconductor device is 14000 μs, the first metal layer 12 may be about 10% higher than 7000 μs using USG (undoped silicon glass) or P-TEOS on the first insulating layer 10. Form to a large thickness. Thereafter, the first metal pattern is formed by using a photo and etching process.

Next, as shown in FIG. 2, a second insulating film 14 is formed on the resultant, and the second insulating film 14 is etched until the surface of the first metal pattern is exposed by chemical mechanical polishing. In this case, the end point is about 10% of the thickness of the first metal layer 12.

Subsequently, the exposed portion T of the first metal pattern is removed using an etching process as shown in FIG. 3. By the etching process, the thickness of the first metal pattern is maintained at about 7000 kPa.

Next, as shown in FIG. 4, a second metal layer 16 is formed on the resultant at about 7000 kPa. Subsequently, the second metal layer 16 is etched using the reticle used to form the first metal pattern as shown in FIG. 5. Accordingly, a second metal pattern having the same thickness and pattern as the first metal pattern is formed on the first metal pattern. At this time, even if the second metal pattern is formed in a misalignment with the first metal pattern, it is possible to take electrical properties by the properties of the metal.

Thereafter, as shown in FIG. 6, the third insulating film 18 is formed of USG, P-TEOS, or USG + P-TEOS on the resultant, and a planarization process is performed to complete metal wiring of the semiconductor device as shown in FIG. 7.

Since the present invention forms a metal wiring formed twice (or more) in accordance with the above manufacturing process, the aspect ratio of the metal thickness in contact with the interlayer insulating film surface can be doubled (or more). have.

Since the aspect ratio between an interlayer insulating film and a metal can be improved, this invention has the effect which can raise the reliability of a semiconductor device.

Claims (1)

Depositing and planarizing a first insulating film for insulating the lower structures and the upper wiring layers in the multilayer wiring process; Forming a first metal pattern on the first insulating layer at a height equal to or less than a desired wiring thickness, and then forming a first metal pattern using a photolithography and an etching process; Forming a second insulating film on the resultant product; Etching the second insulating layer until the surface of the first metal pattern is exposed; Etching the exposed portion of the first metal pattern; Forming a second metal layer on the resultant, and forming a second metal pattern on the first metal pattern by using a photolithography and an etching process; And And forming a third insulating film on the resultant and performing a planarization process.