JPH01119028A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01119028A
JPH01119028A JP27638487A JP27638487A JPH01119028A JP H01119028 A JPH01119028 A JP H01119028A JP 27638487 A JP27638487 A JP 27638487A JP 27638487 A JP27638487 A JP 27638487A JP H01119028 A JPH01119028 A JP H01119028A
Authority
JP
Japan
Prior art keywords
mask
aluminum
film
oxide film
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27638487A
Other languages
Japanese (ja)
Inventor
Nobuaki Yamamori
山盛 信彰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27638487A priority Critical patent/JPH01119028A/en
Publication of JPH01119028A publication Critical patent/JPH01119028A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To allow patterns of submicron thick to be formed using an exposing technique with an ordinary light by patterning a material remaining in a sidewall of an intermediate layer as a mask. CONSTITUTION:Aluminum 2 is bonded to an oxide film 1 to cause an intermediate layer consisting of an oxide film 3 to grow. Such layer is etched with a photoresist 4 as a mask, the photoresist 4 being removed to cause a plasma nitride film 5 to grow on the entire surface of a wafer. When removing the oxide film 3 and the plasma nitride film by means of a reactive ion etching, the plasma nitride film 5 bonded to the side of the oxide film 3 remains due to anisotropy of the etching. The aluminum is etched with the remained nitride film 5 as a mask, an aluminum wiring of about 0.3mum wide save the mask being formed. A polysilicon wiring is also formed with an aluminum sidewall as a mask.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に微細パター
ンを形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a fine pattern.

〔従来の技術〕[Conventional technology]

従来、被加工膜をパターニングする方法としては、フォ
トレジストを使用して所望のパターンを形成し、これを
マスクとして被加工膜を除去する方法が一般的である。
Conventionally, a common method for patterning a film to be processed is to form a desired pattern using a photoresist and remove the film to be processed using this as a mask.

第3図は従来の製造方法によりアルミニウムをパターニ
ングした例を示している。まず、第3図(a)の様に酸
化膜21上にアルミニウム22を例えばスパッタ法によ
り被着させ、フォトレジスト24により所望のパターン
を形成する。
FIG. 3 shows an example of patterning aluminum using a conventional manufacturing method. First, as shown in FIG. 3(a), aluminum 22 is deposited on an oxide film 21 by, for example, sputtering, and a desired pattern is formed using a photoresist 24. As shown in FIG.

次に第3図(b)の様に7オトレジスト24をマスクに
不要部分のアルミニウムを反応性イオンエ。
Next, as shown in FIG. 3(b), using the 7-photoresist 24 as a mask, unnecessary parts of the aluminum are etched with reactive ion etchant.

チングによりと9除く。そして最後に第3図(C)の様
に酸素プラズマによシ、マスクとして使用したフォトレ
ジストをとり除いてアルミニウムのパターニングが完成
する。
Excluding 9 due to chingu. Finally, as shown in FIG. 3(C), the photoresist used as a mask is removed by oxygen plasma to complete the aluminum patterning.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のパターン形成方法では、被加工物はマス
クであるフォトレジストのパターンどうりに加工される
ため、パターンの最小幅はフォトレジストの幅で決定さ
れる。現在の光によるフォトレジスト露光法では、最小
幅は約1μmが限界であり、サブミクロンのフォトレジ
ストパターンを形成することは困難である。従って、被
加工物をサブミクロンの幅でパターニングすることは困
難であるという欠点があった。
In the conventional pattern forming method described above, the workpiece is processed according to the pattern of the photoresist as a mask, so the minimum width of the pattern is determined by the width of the photoresist. In the current photoresist exposure method using light, the minimum width is limited to about 1 μm, and it is difficult to form a submicron photoresist pattern. Therefore, there is a drawback that it is difficult to pattern a workpiece with a submicron width.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の微細パターン形成方法は、被加工
膜上の中間層の側壁にのみ絶縁膜又は導電膜を形成する
工程と、側壁の絶縁膜又は導電膜を残して中間層をと9
除く工程と、残った絶縁膜又は導電膜をマスクにして被
加工膜を反応性イオンエツチングにより除去する工程と
を有している。
The method for forming a fine pattern of a semiconductor device according to the present invention includes a step of forming an insulating film or a conductive film only on the side wall of an intermediate layer on a film to be processed, and a step of forming an insulating film or a conductive film on the side wall of the intermediate layer.
and a step of removing the film to be processed by reactive ion etching using the remaining insulating film or conductive film as a mask.

〔実施例〕〔Example〕

次て本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の第1の実施例の製造工程を示す断面図
である。
FIG. 1 is a sectional view showing the manufacturing process of the first embodiment of the present invention.

まず、第1図(a)の様に、下地酸化膜1上に被加工物
であるアルミニウム2を被着し、さらに中間層でちる酸
化膜3を例えばCVD法により約500OA成長させる
。引き続き、フォトレジスト4によりバター/を形成す
る。次に第1図(b)の様に、フォトレジスト4をマス
クにして中間層である酸化膜3を例えばCF4 + L
ガスを使用した反応性イオンエツチングによりとシ除く
。次に第1図(C)の様に、フォトレジスト4を酸素プ
ラズマによりと9除き、ウェハ全面にプラズマ窒化膜5
t−例えば約300 of成長させる。・ この後第1図(d)の様に、例えばCF、ガスを使用し
た反応性イオンエツチングによ#)rR化膜3およびア
ルミニウム2上に成長したプラズマ窒化膜をと9除くの
であるが、この際エツチングの異方性により、酸化膜3
の側面に付着したプラズマ窒化膜5は除去されずに残る
。さらに第1図(e)の様に中間層である酸化膜3を例
えばバッフアート弗酸によりとシ除く。しかる後第1図
(f)の様に残ったプラズマ窒化膜5をマスクにして不
要部分のアルミニウムを例えばBCfls + CCQ
、ガスによる反応性イオンエッチングによりとり除く。
First, as shown in FIG. 1(a), aluminum 2, which is a workpiece, is deposited on a base oxide film 1, and an intermediate oxide film 3 of about 500 OA is grown by, for example, the CVD method. Subsequently, a butter layer is formed using photoresist 4. Next, as shown in FIG. 1(b), using the photoresist 4 as a mask, the oxide film 3 as the intermediate layer is coated with, for example, CF4 + L.
Remove by reactive ion etching using gas. Next, as shown in FIG. 1(C), the photoresist 4 is removed by oxygen plasma and a plasma nitride film 5 is formed over the entire surface of the wafer.
t - for example, about 300 of.・After this, as shown in FIG. 1(d), the plasma nitride film grown on the rR film 3 and the aluminum 2 is removed by reactive ion etching using, for example, CF gas. At this time, due to the anisotropy of etching, the oxide film 3
The plasma nitride film 5 adhering to the side surface remains without being removed. Further, as shown in FIG. 1(e), the oxide film 3, which is the intermediate layer, is removed by, for example, buffered hydrofluoric acid. After that, as shown in FIG. 1(f), using the remaining plasma nitride film 5 as a mask, unnecessary parts of aluminum are coated with, for example, BCfls + CCQ.
, removed by reactive ion etching with gas.

最後に、第1図(g)の様にマスクに使用したプラズマ
窒化膜5を例えばCF4+ O,ガスプラズマによりと
り除いて配線幅が約0.3μmのアルミニウム配線が形
成される。
Finally, as shown in FIG. 1(g), the plasma nitride film 5 used as a mask is removed using, for example, CF4+O gas plasma to form an aluminum wiring having a wiring width of about 0.3 μm.

第2図は本発明の第2の実施例の製造工程を示す断面図
である。まず、第2図(a)の様に下地酸化膜11上に
被加工物であるポリシリコン16を被着し、更に中間層
である酸化膜13を例えばCVD法により約500OA
成長させる。引き続きフォトレジスト14によりパター
ンを形成する。次に第2図(b)の様に7オトレジスト
14をマスクにして中間層である酸化膜を例えばCF、
+H,ガスによる反応性イオンエツチングによりとシ除
く。次に第2図(C)の様に7オトレジスト14を酸素
プラズマによりとり除き、ウェハ全面にアルミニウム1
2を例えばCVD法により約200OA 成長させる。
FIG. 2 is a sectional view showing the manufacturing process of a second embodiment of the present invention. First, as shown in FIG. 2(a), a polysilicon 16, which is a workpiece, is deposited on a base oxide film 11, and an oxide film 13, which is an intermediate layer, is deposited to a thickness of about 500 OA by, for example, CVD.
Make it grow. Subsequently, a pattern is formed using photoresist 14. Next, as shown in FIG. 2(b), using the 7-otoresist 14 as a mask, the oxide film that is the intermediate layer is made of, for example, CF.
+H, removed by reactive ion etching with gas. Next, as shown in FIG. 2(C), the 7 photoresist 14 is removed using oxygen plasma, and the aluminum 1
2 is grown to about 200 OA by, for example, the CVD method.

この後第2図(d)の様に例えばB Cft s + 
CCu4ガスを使用した反応性イオンエツチングにより
酸化膜13およびポリシリコン16上に成長したアルミ
ニウムをとり除く。この時酸化膜13の側壁のアルミニ
ウム12は残る。更に第2図(e)の様に中間層である
愼化膜を例えばバッフアート弗1設によりとり除く。し
かる後、第2図(f)の様に残ったアルミニウム12を
マスクにして不要部分のポリシリコンを例えばCCf1
2F、ガスによる反応性イオンエッチングによりとり除
く。最後に第2図(g)の様にマスクに使用したアルミ
ニウムをPHC液によりとり除き、配線幅が約0.2μ
mのポリシリコン配線が形成される。
After this, as shown in FIG. 2(d), for example, B Cft s +
Aluminum grown on oxide film 13 and polysilicon 16 is removed by reactive ion etching using CCu4 gas. At this time, the aluminum 12 on the side wall of the oxide film 13 remains. Furthermore, as shown in FIG. 2(e), the intermediate layer, ie, the phlegmatic film, is removed by, for example, buffing. After that, as shown in FIG. 2(f), using the remaining aluminum 12 as a mask, the unnecessary portions of polysilicon are coated with, for example, CCf1.
2F, removed by reactive ion etching with gas. Finally, as shown in Figure 2 (g), the aluminum used for the mask is removed using PHC liquid, and the wiring width is approximately 0.2μ.
m polysilicon interconnections are formed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、中間層の側壁に残った材
料をマスクにしてパターニングをおこなうことにより、
通常の光による露光技術を用いてもサブミクロンのパタ
ーンが形成できる効果がある。また被加工物のできあが
り幅は、中間層上に成長させる材料の膜厚によって決ま
るため寸法の再現性も良い。
As explained above, the present invention performs patterning by using the material remaining on the sidewall of the intermediate layer as a mask.
Even if exposure technology using ordinary light is used, submicron patterns can be formed effectively. Furthermore, the finished width of the workpiece is determined by the thickness of the material grown on the intermediate layer, so dimensional reproducibility is also good.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(g)は本発明の@1の実施例の製造工
程を示す断面図、第2図(a)〜(g)は本発明の第2
の実施例の製造工程を示す断面図、第3図(a)〜(C
)は従来の製造方法を示した断面図である。 1.11,21・・・・・・酸化膜、2,12.22・
・・・・・アルミニウム、3.13・・・・・・酸化M
、4,14゜24・・・・・・フォトレジスト、5・・
・・・・プラズマ窒化膜、16・・・・・・ポリシリコ
ン。 代理人 弁理士  内 原   晋 (C)(つ) (ダ〕 第 1 図 [Q)                  <e)(
b)                 (f)IC)
                 (9)(の 第2図 (び) (b) 第3図
FIGS. 1(a) to (g) are cross-sectional views showing the manufacturing process of the @1 embodiment of the present invention, and FIGS. 2(a) to (g) are sectional views of the second embodiment of the present invention.
3(a) to (C) are cross-sectional views showing the manufacturing process of the example of
) is a sectional view showing a conventional manufacturing method. 1.11,21... Oxide film, 2,12.22.
... Aluminum, 3.13 ... Oxidation M
, 4, 14° 24... Photoresist, 5...
...Plasma nitride film, 16...Polysilicon. Agent Patent Attorney Susumu Uchihara (C) (T) (D) Figure 1 [Q] <e) (
b) (f) IC)
(9) (Figure 2 (bi) (b) Figure 3

Claims (1)

【特許請求の範囲】[Claims]  被加工膜上の中間層の側壁にのみ絶縁膜又は導電膜を
形成する工程と、側壁の絶縁膜又は導電膜を残して中間
層をとり除く工程と、残った絶縁膜又は導電膜をマスク
にして被加工膜を反応性イオンエッチングにより除去す
る工程とを有することを特徴とする半導体装置の製造方
法。
A process of forming an insulating film or a conductive film only on the sidewalls of the intermediate layer on the film to be processed, a process of removing the intermediate layer while leaving the insulating film or conductive film on the sidewalls, and a process of using the remaining insulating film or conductive film as a mask. 1. A method for manufacturing a semiconductor device, comprising the step of removing a film to be processed by reactive ion etching.
JP27638487A 1987-10-30 1987-10-30 Manufacture of semiconductor device Pending JPH01119028A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27638487A JPH01119028A (en) 1987-10-30 1987-10-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27638487A JPH01119028A (en) 1987-10-30 1987-10-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01119028A true JPH01119028A (en) 1989-05-11

Family

ID=17568665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27638487A Pending JPH01119028A (en) 1987-10-30 1987-10-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01119028A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009507375A (en) * 2005-09-01 2009-02-19 マイクロン テクノロジー, インク. Mask pattern having spacers for increasing pitch and method for forming the same
JP2009212163A (en) * 2008-02-29 2009-09-17 Toshiba Corp Method of fabricating semiconductor device
US10515801B2 (en) 2007-06-04 2019-12-24 Micron Technology, Inc. Pitch multiplication using self-assembling materials

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5742151A (en) * 1980-08-28 1982-03-09 Fujitsu Ltd Formation of pattern
JPS59107518A (en) * 1982-11-13 1984-06-21 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Method of forming structure having size of submicron range

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5742151A (en) * 1980-08-28 1982-03-09 Fujitsu Ltd Formation of pattern
JPS59107518A (en) * 1982-11-13 1984-06-21 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Method of forming structure having size of submicron range

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009507375A (en) * 2005-09-01 2009-02-19 マイクロン テクノロジー, インク. Mask pattern having spacers for increasing pitch and method for forming the same
US9099314B2 (en) 2005-09-01 2015-08-04 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US10515801B2 (en) 2007-06-04 2019-12-24 Micron Technology, Inc. Pitch multiplication using self-assembling materials
JP2009212163A (en) * 2008-02-29 2009-09-17 Toshiba Corp Method of fabricating semiconductor device
JP4630906B2 (en) * 2008-02-29 2011-02-09 株式会社東芝 Manufacturing method of semiconductor device

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