JPS5919355A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the etching performance in a reactive ion etching of a wiring material layer on a substrate by covering the entire substrate with a thin SiO2 film before etching. CONSTITUTION:After resist patterns 91, 92 which have SiO2 patterns i1, 82 are forced on an aluminum layer 4 which has stepwise difference, and a thin SiO2 film 12 is covered by a low temperature CVD method on the overall surface. Then, a semiconductor substrate 1 is charged in a reactive ion etching unit to perform reactive ion etching. Since this etching proceeds only in perpendicular direction to the substrate 1, the resist layer patterns 91, 91 and the thin SiO2 film 12' of the side of SiO2 film patterns 81, 82 are not etched but remain. This part 12' can block the volatilization of impurities such as C, N2 from the patterns 91, 92.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular -
TECHNICAL BACKGROUND OF THE INVENTION Conventionally, as a method for forming fine wiring on a semiconductor substrate having steps, a mask has been used as a method for forming fine wiring on a semiconductor substrate having steps. A method called transfer is known in which a flat pattern is created using a mask. Such a method will be described below with reference to FIGS.

First, first layer interconnections 2 are formed on a semiconductor substrate 1 on which elements have been formed in advance via an insulating film (not shown), and then an interlayer insulating film S such as a CVD-8102 film is deposited on the entire surface. After these steps, the first layer wiring 2 is placed on the surface of the substrate 1.
・Irregularities (steps) are formed. Subsequently, after depositing a wiring material layer, such as an At layer 4, on the entire surface, an organic resin layer, such as a resist layer 5, is coated on the entire surface so that the surface is flat, and a low-temperature CVD method is applied on the resist layer 5. The StO□ film 6 is coated, and a resist pattern 71.7□ is formed using a photolithography method on the area where wiring is to be formed on the 8102 film 6.
is formed (as shown in FIG. 1 (-)).

Next, the S10□ film 6 is selectively etched away using the resist layer pattern 71.7gk mask to form another 02 replacement pattern 81. After forming 8M, sho2g pattern 81.8. The resist layer 5 is selectively etched and removed using resist/I! as a mask. Forming a pattern 91.9 (as shown in FIG. 1 (5))0 Note that in this step, the resist pattern 71 on the 5IO2 film's arm turns 81+81 is formed.

7 is removed.

Next, the 810 □ is etched in a reactive ion etching device.
The 4th turn 8t, 8s (or resist pattern t=pattern 9s+93) is masked and the At layer 4 is reactive ion etched to form the 21st At wiring 101.
．． 10 Forms snow (as shown in Figure 1 (1)).

According to the conventional method described above, the step on the substrate 1 is flattened with a thick resist layer 5, and the 8102 film 6 is deposited thereon, and then a resist pattern of 71.7 m is formed by photo-kenpo.
Therefore, it is possible to form a resonette pattern with significantly higher precision than when a resist layer pattern is directly formed on a wiring material layer having steps, and as a result, a highly accurate layout a can be formed.

[Problems with background technology]

However, in the above conventional method, when the At layer 4 is selectively etched using the reactive ion etching apparatus using the 810□ film patterns 8K, 81, etc. as a mask, as shown in FIG. 1(C), Resist layer/
The adhesion layer 11 of the compound due to the reaction with the C, N2 and At layers 4 from the 9th turn 91+91 forms the resist layer pattern 9.
1.

Not only are these impurities formed on the side surfaces of the film patterns 81 and 81 of 93 and 8102, but also impurities such as C and N2 other than the reactive gas are mixed into the reactive ion etching apparatus. the result,
When the former adhesion layer 1 is formed, kA wiring J01,7
An At fence etc. is generated at the end of the resist layer pattern 91.

This has a significant adverse effect on the formation of the 9-basin film after removing the 9 m, and causes a decrease in the reliability of the semiconductor device. Furthermore, the latter contamination of impurities into the reactive ion etching apparatus degrades etching performance and inhibits uniform etching.

[Purpose of the invention]

SUMMARY OF THE INVENTION The present invention aims to provide a method for manufacturing highly reliable semiconductor devices while preventing performance degradation of a reactive ion etching apparatus used for etching a wiring material layer.

[Summary of the invention]

In the present invention, after forming a two-layer structure pattern of an organic resin layer pattern and a coating pattern on a wiring material layer having steps on a semiconductor substrate, a thin film is formed on the entire surface, and the thin film and wiring material layer are etched using a reactive ion etching device. When etching, the reactive ion etching process proceeds only in the direction perpendicular to the substrate, making use of the fact that a thin film can remain on the sides of the two-layer structure pattern (particularly on the sides of the organic resin layer and F-turn). , the remaining thin film causes the organic material layer to be removed.
The main idea is to selectively perform reactive ion etching on the wiring material layer while preventing the volatilization of 5- impurities such as C and N2 from inside the turn. Similar to the conventional method described above, the At layer 4 has a step difference.
810□ film pattern on the upper surface of the planned wiring formation area: /81
, 8B (9%, 9g) was formed (as shown in FIG. 2(a)).

Subsequently, SIO□ film/mother turn &1,8I and resist layer quantity turns 91,9. Low-temperature C is applied to the entire surface of the At layer 4 including
A 5I02 thin film 12 having a thickness of 500×, for example, was coated by the VD method (as shown in FIG. 2(b)).

Next, the semiconductor substrate 1 covered with the 5I02 thin film 12 was loaded into a reactive ion etching apparatus and subjected to reactive ion etching. At this time, since reactive ion etching progresses only in the direction perpendicular to the substrate 1, the surface of the AA layer 4 and the 5IO2 film are etched. Turn 8. 8. The upper part of the 8I02 thin film 12 is removed by Snow Crab 61, but the resist layer/f-turn 91+9
1 and 810□Membrane quantity turn &1,8. 5I on the side
The O2 thin film 12' portion remains almost unetched. As a result, the resist layer 9 turns 91.9 layers and the sio□ film 8 turns.

The exposed At layer 4 portion with the 810□ thin film 12' remaining on the side surface of 8 m is selectively etched away, and the second
Eyelet At wirings 101, 101 were formed (Fig. 2 (
,) as shown). After this, although not shown, the remaining 8102 thin film 1
2', 5 IO2 film/Lean 81, 8 Remove the snow and remove the resist layer'? After removing the turn 91*9m, a PEG film was deposited on the entire surface of the substrate to manufacture a semiconductor device.

According to the method of the present invention, the second layer 4 is etched by the reactive ion etching method while the side surfaces of the resist layer pattern 91+9g and the 810□ film turn 81+8m, which act as masks, are covered with the remaining 810□12'. For selective etching, resist layer pattern 91+
Cough residual S 1 to volatilize impurities such as C and N2 from 91
This can be prevented by the 02 thin film 12' and the 5I02 film pattern 81.8s. Therefore, it is possible to prevent the formation of an adhesion layer caused by compounds generated by the reaction of C, N2, etc. with At, and as a result, the At7
It is possible to avoid adverse effects on the formation surface of the impurity carbon film due to the formation of rays. In addition, since impurities such as C and N2 do not enter the reactive ion etching equipment, it is possible to eliminate deterioration in etching performance and non-uniformity of etching, making it possible to efficiently form high-precision wiring 101.10 g. .

In addition, although At was used as the wiring material in the above example,
Others: At-81, At-Cu, At-8l-C
An OA4 alloy such as u may also be used.

In the above embodiments, a resist was used as the organic resin, but other resins without photosensitivity such as polyimide resins and polyamide resins may also be used.

In the above embodiment, a 5I02 film was used as the coating, but other impurity-doped glass films such as an 813N4 film, an alumina film, or a tron-doped glass film may also be used.

Although the 8102 thin film was used as the thin film in the above embodiment, other thin films such as S l , N4 thin film, etc. may also be used.

〔Effect of the invention〕

As detailed above, according to the present invention, it is possible to efficiently form high-precision wiring by preventing performance deterioration of the reactive ion etching apparatus used for etching the wiring material layer.
It is possible to provide a method for manufacturing a highly reliable semiconductor device by making it possible to form a 4'y basin film that satisfactorily protects wiring and the like.

[Brief explanation of the drawing]

FIG. 1 (-) to (,) are cross-sectional views showing the wiring formation process of a semiconductor device according to the conventional method, and FIG. FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First layer wiring, 3... Interlayer insulating film, 4... AtMi%'ts 7
1...Resist pattern, 81+JI...510
2 film pattern %91. 9s...Resist layer pattern, 10. ．． 10. ...
9- Second layer At wiring, 12'...Remaining 5102 thin film. =l〇-

Claims (1)

[Claims] A process of forming a wiring material layer on the uneven layer on the semiconductor substrate, and coating the wiring material layer with an organic resin layer so that the surface is flat, and then applying a layer to the wiring planned area on the organic resin layer. a step of forming a film pattern; a step of selectively etching and removing the organic resin layer using the main turn of the film as a mask to form an organic resin layer pattern; After forming a thin film on the entire surface, anisotropic etching is performed to selectively remove the wiring material layer with the thin film remaining on the side surfaces of the coating pattern and the nine turns of the organic resin layer to form wiring. A method for manufacturing a semiconductor device, comprising the steps of: