JPH0355973B2 - - Google Patents
Info
- Publication number
- JPH0355973B2 JPH0355973B2 JP57227602A JP22760282A JPH0355973B2 JP H0355973 B2 JPH0355973 B2 JP H0355973B2 JP 57227602 A JP57227602 A JP 57227602A JP 22760282 A JP22760282 A JP 22760282A JP H0355973 B2 JPH0355973 B2 JP H0355973B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- etching
- photoresist
- semiconductor substrate
- mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- 239000002253 acid Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 238000010894 electron beam technology Methods 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electron Beam Exposure (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は、半導体装置の製造方法に関するもの
であり、より詳しく述べるならば、電子ビーム露
光用位置合せマークの形成方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for forming alignment marks for electron beam exposure.
(2) 技術の背景
半導体装置、特に、LSIなどにおいては高集積
度化のためにパターン寸法の微細化が図られ、そ
のために電子ビーム露光技術（電子ビームリソグ
ラフイ技術）が採用されるようになつてきた。電
子ビームで描画する際には位置合せが非常い重要
であり、位置合せマークの検出を正確に行なう必
要がある。一般的に位置合せマークにはウエハマ
ークとチツプマークとがあり、比較的大きいウエ
ハマークは半導体ウエハの外周近くに形成され、
ウエハの取付け誤差およびウエハの伸縮を測定す
るのに役立ち、一方、チツプマークは各チツプご
とに３個程度形成され、ビームとマークとの相対
位置誤差および回転誤差を検出するに役立つてい
る。(2) Background of the technology In semiconductor devices, especially LSIs, pattern dimensions have become smaller in order to achieve higher levels of integration, and electron beam exposure technology (electron beam lithography technology) has been adopted for this purpose. I'm getting old. When writing with an electron beam, alignment is very important, and it is necessary to accurately detect alignment marks. Generally, alignment marks include wafer marks and chip marks, and relatively large wafer marks are formed near the outer periphery of the semiconductor wafer.
It is useful for measuring mounting errors of the wafer and expansion and contraction of the wafer.On the other hand, about three chip marks are formed for each chip, and are useful for detecting relative positional errors and rotational errors between the beam and the marks.
(3) 従来技術と問題点
例えば、ゲートアレイなどでの配線のマスター
スライス化に伴ない配線工程で電子ビーム露光を
利用するようになつてきた。この場合に、従来
は、位置合せマークを次のようにして電極窓形成
時に形成されている。すなわち、第１図に示すよ
うに半導体基体（シリコンウエハ）１上の絶縁膜
（SiO2膜）２の上にホトレジストを塗布し、電極
窓および位置合せマーク用のマスクパターンを用
いて露光し、現像してホトレジスト膜３を形成す
る。このホトレジスト膜３をマスクとして絶縁膜
２を選択的にエツチングして電極窓４およびマー
クパターン窓５を形成する。次に、別のホトレジ
ストを塗布し、マークパターン窓５の上方でマー
クパターンより大きい部分のみを露光現像によつ
て除去したホトレジスト層６を形成する（第２
図）。したがつて、マーク形成部分以外をホトレ
ジスト層６で覆う。そして、異方性ドライエツチ
ング（例えば、リアクテイブイオンエツチング）
によつてマスクパターン窓５内に露出している半
導体基体１のシリコンを選択的にエツチング除去
して溝７（第３図）を形成する。この溝７が位置
合せマークであり、電子ビームによつてこのマー
クを走査すると段差部にて反射信号が変化してマ
ークの検出が行なわれる。Ｓ／Ｎのよい反射信号
を得るためには半導体基体１に形成するマークの
溝７の深さが約3μｍ程度で、溝７の側面が垂直
に近いほうが好ましい。(3) Conventional technology and problems For example, with the master slicing of wiring in gate arrays, etc., electron beam exposure has come to be used in the wiring process. In this case, conventionally, alignment marks are formed at the time of electrode window formation in the following manner. That is, as shown in FIG. 1, photoresist is coated on an insulating film (SiO 2 film) 2 on a semiconductor substrate (silicon wafer) 1, and exposed using a mask pattern for electrode windows and alignment marks. A photoresist film 3 is formed by development. Using this photoresist film 3 as a mask, the insulating film 2 is selectively etched to form an electrode window 4 and a mark pattern window 5. Next, another photoresist is applied, and a photoresist layer 6 is formed by removing only a portion larger than the mark pattern above the mark pattern window 5 by exposure and development (second photoresist layer 6).
figure). Therefore, the photoresist layer 6 covers the area other than the mark forming area. and anisotropic dry etching (e.g. reactive ion etching)
The silicon of the semiconductor substrate 1 exposed within the mask pattern window 5 is selectively etched away to form a groove 7 (FIG. 3). This groove 7 is an alignment mark, and when this mark is scanned by an electron beam, the reflected signal changes at the stepped portion, and the mark is detected. In order to obtain a reflected signal with a good S/N ratio, it is preferable that the depth of the groove 7 of the mark formed on the semiconductor substrate 1 is about 3 μm, and that the side surfaces of the groove 7 are close to vertical.
しかしながら、リアクテイブイオンエツチング
では半導体基体１のシリコンと同時にシリコンの
エツチレートより小さいエツチレートであるがホ
トレジスト膜３，６および絶縁膜２のSiO2がエ
ツチングされるので、オーバエツチング的にエツ
チング処理を行なうと、第４図に示すようなるこ
ととがある。特に、絶縁膜（SiO2膜）２の厚さ
が約0.3μｍと比較的薄いならば、この絶縁膜２が
エツチング除去されてしまい、側面に段差のある
溝８が形成される。このためにＳ／Ｎの良い反射
信号が得られない。さらに、ホトレジスト膜を２
層とするために、はじめのホトレジスト膜３には
ポジ形レジストを使用できないという制約があ
る。これはポジ形ホトレジスト膜の上にポジ形レ
ジストを塗布したときに塗布レジストの溶剤によ
つて溶解してしまうためであり、また、ネガ形レ
ジストを塗布したときにはネガ形レジストの現像
時に現像剤に溶解してしまうからである。 However, in reactive ion etching, the photoresist films 3 and 6 and the SiO 2 of the insulating film 2 are etched at the same time as the silicon of the semiconductor substrate 1, although the etching rate is lower than that of silicon. , something like the one shown in FIG. 4 may occur. In particular, if the thickness of the insulating film (SiO 2 film) 2 is relatively thin, about 0.3 μm, the insulating film 2 will be etched away, and a groove 8 with a step on the side surface will be formed. For this reason, a reflected signal with a good S/N ratio cannot be obtained. Furthermore, the photoresist film is
In order to form a layer, there is a restriction that a positive resist cannot be used for the initial photoresist film 3. This is because when a positive photoresist is applied on a positive photoresist film, it is dissolved by the solvent of the coated resist.Also, when a negative photoresist is applied, it is dissolved by the developer when developing the negative photoresist. This is because it will dissolve.
(4) 発明の目的
本発明の目的は、Ｓ／Ｎの良い反射信号を得る
ことのできる電子ビーム露光用位置合せマークを
形成することである。(4) Object of the invention The object of the invention is to form an alignment mark for electron beam exposure that can obtain a reflected signal with a good S/N ratio.
(5) 発明の構成
本発明の目的が、所定形状の耐酸化膜を半導体
基体上に形成し、該半導体基体の該耐酸化膜で覆
われない領域を選択的に酸化して酸化物膜を形成
した後該耐酸化膜を除去し、次いで該半導体基体
の酸化されない領域およびその周囲の該酸化物膜
部分を除いて全面に耐エツチング膜を形成した後
エツチングを行ない、該半導体基体の酸化されな
い領域に溝形状の位置合せマークを形成すること
を含んでなる位置合せマークの形成方法によつて
達成される。(5) Structure of the Invention An object of the present invention is to form an oxidation-resistant film in a predetermined shape on a semiconductor substrate, and selectively oxidize areas of the semiconductor substrate that are not covered with the oxidation-resistant film to form an oxide film. After forming the oxidation-resistant film, the oxidation-resistant film is removed, and an etching-resistant film is formed on the entire surface of the semiconductor substrate except for the non-oxidized region and the oxide film portion around it, and etching is performed to prevent the semiconductor substrate from being oxidized. This is accomplished by a method of forming an alignment mark that includes forming a groove-shaped alignment mark in a region.
本発明の位置合せマークの形成方法において
は、エツチングすべきマーク形状の半導体基板部
分およびその周囲の比較的厚い酸化物膜（いわゆ
るフイールド酸化膜）は露出しており、ドライエ
ツチング時にこの酸化物膜も多少エツチングされ
てしまうがその厚さが十分にあるのでマスクとし
て働く。 In the alignment mark forming method of the present invention, the mark-shaped portion of the semiconductor substrate to be etched and the relatively thick oxide film (so-called field oxide film) surrounding it are exposed, and during dry etching, this oxide film is removed. Although it is etched to some extent, it is thick enough to work as a mask.
(6) 発明の実施態様
以下、添付図面を参照して本発明の実施態様例
によつて本発明をより詳細に説明する。(6) Embodiments of the invention Hereinafter, the present invention will be explained in more detail by way of embodiments of the invention with reference to the accompanying drawings.
第５図に示すように半導体シリコン基板（シリ
コンウエハ）１１上に選択酸化のための耐酸化膜
１２を電子ビーム露光用位置合せマーク形状に形
成する。このためには、まず、シリコン基板１１
を熱酸化して薄い酸化（SiO2）膜１３を形成し、
その上に窒化（Si3N4）膜１４をCVD法によつて
形成する。次に、ホトレジストを塗布し、集積回
路（IC）の素子を規定するパターンおよび位置
合せマークのパターンを有するホトマスクを使用
して露光し、現像してホトレジスト膜（図示せ
ず）を形成する。このホトレジスト膜をマスクと
して窒化膜１４および酸化膜１３を選択エツチン
グする。なお、第５図ないし第１２図においては
位置合せマークを形成する部分のみを示す。 As shown in FIG. 5, an oxidation-resistant film 12 for selective oxidation is formed on a semiconductor silicon substrate (silicon wafer) 11 in the shape of an alignment mark for electron beam exposure. For this purpose, first, the silicon substrate 11
is thermally oxidized to form a thin oxide (SiO 2 ) film 13,
A nitride (Si 3 N 4 ) film 14 is formed thereon by CVD. A photoresist is then applied, exposed using a photomask having a pattern defining the integrated circuit (IC) elements and a pattern of alignment marks, and developed to form a photoresist film (not shown). Using this photoresist film as a mask, nitride film 14 and oxide film 13 are selectively etched. In addition, in FIGS. 5 to 12, only the portion where the alignment mark is formed is shown.
耐酸化膜１２をマスクとしてシリコン基板１１
をエツチングしてから、熱酸化処理によつて比較
的厚い酸化物（SiO2）膜１５（第６図）を形成
する。この酸化物膜１５はフイールド酸化膜と呼
ばれるもので、Isoplanar方式又はoxide
Surrounded Transiston方式などの
ComposedMosk方式で集積回路を製造する場合
の厚い酸化膜であることは好ましい。シリコン基
板１１のエツチング深さは、厚い酸化物膜１５の
表面が酸化されずにあるシリコン基板１１の表面
とほぼ高さとなるよう設定する。 Silicon substrate 11 using oxidation-resistant film 12 as a mask
After etching, a relatively thick oxide (SiO 2 ) film 15 (FIG. 6) is formed by thermal oxidation treatment. This oxide film 15 is called a field oxide film, and is an isoplanar type or oxide film.
Surrounded Transiston method etc.
A thick oxide film is preferred when manufacturing integrated circuits using the ComposedMosk method. The etching depth of the silicon substrate 11 is set so that the surface of the thick oxide film 15 is approximately at the same height as the unoxidized surface of the silicon substrate 11.
次に、シリコン基板１１の図示していない所定
領域に回路素子であるバイポーラトランジスタ、
MOSFET、拡散抵抗などの不純物導入領域を通
常の製造工程にしたがつて形成し、電極窓形成と
同時に第７図に示すようにシリコン基板１１のマ
ーク形状部分を露出させる。 Next, a bipolar transistor, which is a circuit element, is placed in a predetermined area (not shown) of the silicon substrate 11.
Impurity introduction regions such as MOSFETs and diffused resistors are formed according to the normal manufacturing process, and at the same time as electrode windows are formed, mark-shaped portions of the silicon substrate 11 are exposed as shown in FIG.
ホトレジストを全面に塗布し、位置合せマーク
部分に対して位置合せ余裕をとつたパターンのホ
トマスクで露光し、現像して第８図に示すように
シリコン基板１１の露出部分およびその近傍周囲
の厚い酸化物膜部分を除いてホトレジスト膜１６
で覆う。 Photoresist is applied to the entire surface, exposed using a photomask with a pattern that allows alignment margin for the alignment mark portion, and developed, resulting in thick oxidation of the exposed portion of the silicon substrate 11 and its surroundings, as shown in FIG. Photoresist film 16 except for the material film part
cover with
次に、異方性ドライエツチングである塩素系ガ
ス（CCl4、BCl3、SiCl4又はCl2）のリアクテイブ
イオンエツチングによつて露出しているマーク形
状のシリコン基板部分をエツチングして溝１７を
形成する。この溝１７が位置合せマークである。
このドライエツチングによつて厚い酸化物膜１５
もエツチングされてしまうが、エツチレードがシ
リコンよりも小さいのでエツチング深さはその厚
さに比べて小さい。すなわち、この厚い酸化物膜
１５が溝１７の形成のためのマスクとして働いて
いる。また、ホトレジスト１６を同時にエツチン
グされるが、十分に厚く形成しておくことでホト
レジスト膜１６に覆われている部分はエツチング
から保護されている。そしてこのホトレジスト膜
１６を適切な溶剤で除去することで電子ビーム露
光用マークが完成する。 Next, the exposed mark-shaped portion of the silicon substrate is etched by reactive ion etching using chlorine-based gas (CCl 4 , BCl 3 , SiCl 4 or Cl 2 ), which is anisotropic dry etching, to form grooves 17. form. This groove 17 is an alignment mark.
This dry etching creates a thick oxide film 15.
The etching layer is also etched, but since the etched layer is smaller than the silicon layer, the etching depth is smaller than its thickness. That is, this thick oxide film 15 functions as a mask for forming the groove 17. Further, although the photoresist film 16 is etched at the same time, the portion covered by the photoresist film 16 is protected from etching by forming it sufficiently thick. Then, by removing this photoresist film 16 with an appropriate solvent, an electron beam exposure mark is completed.
上述した実施態様例では位置合せマークである
溝をドライエツチングによつて形成する際に厚い
酸化物膜上にホトレジスト膜を形成していたが、
このホトレジスト膜の代わりにエミツタ領域形成
をウオツシユアウト方式で行なう場合のノンドー
プの多結晶シリコン膜とその上のリン・シリケー
ト・ガラス（PSG）膜との２層膜を使用するこ
とができる。 In the embodiment described above, a photoresist film was formed on a thick oxide film when forming grooves serving as alignment marks by dry etching.
Instead of this photoresist film, a two-layer film of a non-doped polycrystalline silicon film and a phosphorous silicate glass (PSG) film thereon can be used when the emitter region is formed by the washout method.
この場合には、上述した実施態様例の工程と同
様にして第５図および第６図の状態を経て第７図
に示すように厚い酸化物膜１５を形成し、シリコ
ン基板１１のマーク形状部分を露出させる。次
に、ノンドープの多結晶シリコン膜２１（厚さ約
0.1μｍをCVD法でもつて全面に形成する（第１
０図）。この多結晶シリコン膜２１の上にPSG膜
２２（厚さ0.5〜1.0μｍ）をCVD法でもつて全面
に形成する。ホトレジストをPSG膜２２の上に
塗布し、第８図でのホトレジスト膜１６を形成す
るのに使用したホトマスクでもつて露光し、現像
して、ホトレジスト膜２３を形成する（第１０
図）。 In this case, a thick oxide film 15 is formed as shown in FIG. 7 through the steps shown in FIGS. 5 and 6 in the same manner as in the process of the embodiment described above, and expose. Next, a non-doped polycrystalline silicon film 21 (with a thickness of approximately
0.1μm is formed on the entire surface by CVD method (first
Figure 0). A PSG film 22 (thickness: 0.5 to 1.0 μm) is formed on the entire surface of the polycrystalline silicon film 21 using the CVD method. A photoresist is applied onto the PSG film 22, exposed using the photomask used to form the photoresist film 16 in FIG. 8, and developed to form a photoresist film 23 (10th
figure).
このホトレジスト膜２３をマスクとしてPSG
膜２２および多結晶シリコン膜２１をウエツトエ
ツチング法（緩衝HF溶液−PSG）およびドライ
エツチング法（CF4等−poly si）で選択エツチン
グして第１１図に示すようにシリコン基板１１の
マーク部分およびその近傍周囲の厚い酸化物膜１
５を露出させる。この露出部分以外は多結晶シリ
コン膜２１およびPSG膜２２で覆われている。 Using this photoresist film 23 as a mask, PSG
The film 22 and the polycrystalline silicon film 21 are selectively etched by a wet etching method (buffered HF solution - PSG) and a dry etching method (CF 4 etc. - poly si) to form a marked portion of the silicon substrate 11 as shown in FIG. and thick oxide film 1 around it
Expose 5. The portion other than this exposed portion is covered with a polycrystalline silicon film 21 and a PSG film 22.
次に、上述の実施態様例と同じ異方性ドライエ
ツチング（リアクテイブイオンエツチング）によ
つて露出しているマーク形状のシリコン基板部分
を選択的に除去して溝２４（第１２図）を形成す
る。この溝２４が電子ビーム露光用位置合せマー
クであり、第９図の場合と同様に厚い酸化物膜１
５はエツチングされにもかかわらず残在するので
溝１７の形成のためのマスクとして働く。また、
PSG膜２２も同時にエツチングされるがエツチ
レートがシリコンのエツチレートよりも小さいの
で第１２図のように残る。この後で、通常の工程
にしたがつてPSG膜２３を所定の拡散領域上の
みに残すようにホトエツチング法で選択エツチン
グする。そして、加熱処理によつてPSG膜２３
中のリンをシリコン基板１１内へ拡散させてエミ
ツタ（Ｎ型）領域（図示せず）を形成する。この
PSG膜をウオツシユアウトし、所定の電極窓を
開けてから配線（図示せず）を電子ビーム露光を
利用して形成する。 Next, the exposed mark-shaped portion of the silicon substrate is selectively removed by the same anisotropic dry etching (reactive ion etching) as in the embodiment described above to form a groove 24 (FIG. 12). do. This groove 24 is an alignment mark for electron beam exposure, and as in the case of FIG. 9, the thick oxide film 1
5 remains even though it has been etched, and serves as a mask for the formation of groove 17. Also,
The PSG film 22 is also etched at the same time, but since the etching rate is smaller than the etching rate of silicon, it remains as shown in FIG. Thereafter, according to the usual process, the PSG film 23 is selectively etched using a photoetching method so that it remains only on a predetermined diffusion region. Then, by heat treatment, the PSG film 23
The phosphorus contained therein is diffused into the silicon substrate 11 to form an emitter (N type) region (not shown). this
After washing out the PSG film and opening a predetermined electrode window, wiring (not shown) is formed using electron beam exposure.
(7) 発明の効果
本発明の位置合せマーク形成方法によつて、
Ｓ／Ｎのよい反射信号を得ることのできる深い溝
形状マークが形成できる。比較的厚い酸化物膜を
溝マークのエツチングの際にマスクとしているの
で、従来の場合よりもドライエツチング条件の範
囲が広くなる。(7) Effects of the invention By the alignment mark forming method of the present invention,
It is possible to form a deep groove-shaped mark from which a reflected signal with a good S/N ratio can be obtained. Since the relatively thick oxide film is used as a mask when etching groove marks, the range of dry etching conditions is wider than in the conventional case.
第１図ないし第３図は、従来の電子ビーム露光
用位置合せマークの形成方法を説明する半導体装
置の部分断面図であり、第４図は従来の位置合せ
マーク形成方法での欠点を説明するための半導体
装置の部分断面図であり、第５図ないし第９図は
本発明の位置合せマーク形成方法の実施態様例を
説明する半導体装置の部分断面図であり、第１０
図ないし第１２図は別の実施例態様例を説明する
半導体装置の部分断面図である。
１……半導体基板、２……絶縁膜、３……ホト
レジスト膜、５……マークパターン窓、６……ホ
トレジスト膜、７，８……溝（位置合せマーク）、
１１……半導体基板、１２……耐酸化膜、１５…
…厚い酸化物膜、１６……ホトレジスト膜、１７
……溝、２２……PSG膜、２４……溝。
1 to 3 are partial cross-sectional views of a semiconductor device for explaining the conventional method of forming alignment marks for electron beam exposure, and FIG. 4 illustrates the drawbacks of the conventional alignment mark forming method. FIGS. 5 to 9 are partial sectional views of a semiconductor device illustrating embodiments of the alignment mark forming method of the present invention, and FIGS.
12 are partial sectional views of a semiconductor device illustrating another example of an embodiment. 1... Semiconductor substrate, 2... Insulating film, 3... Photoresist film, 5... Mark pattern window, 6... Photoresist film, 7, 8... Groove (alignment mark),
11... Semiconductor substrate, 12... Oxidation resistant film, 15...
...Thick oxide film, 16... Photoresist film, 17
...Groove, 22...PSG film, 24...Groove.
Claims (1)
し、該半導体基体の該耐酸化膜で覆われない領域
を選択的に酸化して酸化物膜を形成した後該耐酸
化膜を除去し、次いで該半導体基体の酸化されな
い領域およびその周囲の該酸化物膜部分を除いて
全面に耐エツチング膜を形成した後エツチングを
行ない、該半導体基体の酸化されない領域に溝形
状の位置合せマークを形成することを含んでなる
位置合せマークの形成方法。 ２ 前記耐エツチング膜がレジスト膜であことを
特徴とする特許請求の範囲第１項記載の形成方
法。 ３ 前記耐エツチング膜がノンドープの多結晶シ
リコン膜とリン・シリケート・ガラス膜とからな
ることを特徴とする特許請求の範囲第１項記載の
形成方法。[Scope of Claims] 1. An oxidation-resistant film of a predetermined shape is formed on a semiconductor substrate, a region of the semiconductor substrate that is not covered with the oxidation-resistant film is selectively oxidized to form an oxide film, and then the acid-resistant film is formed. After removing the oxidized film, an etching-resistant film is formed on the entire surface of the semiconductor substrate except for the non-oxidized region and the surrounding oxide film portion, and etching is performed to form a trench-shaped region in the non-oxidized region of the semiconductor substrate. A method of forming an alignment mark, the method comprising forming an alignment mark. 2. The forming method according to claim 1, wherein the etching-resistant film is a resist film. 3. The method of claim 1, wherein the etching-resistant film is comprised of a non-doped polycrystalline silicon film and a phosphorus silicate glass film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57227602A JPS59121836A (en) | 1982-12-28 | 1982-12-28 | Formation of positioning mark |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57227602A JPS59121836A (en) | 1982-12-28 | 1982-12-28 | Formation of positioning mark |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59121836A JPS59121836A (en) | 1984-07-14 |
| JPH0355973B2 true JPH0355973B2 (en) | 1991-08-27 |
Family
ID=16863503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57227602A Granted JPS59121836A (en) | 1982-12-28 | 1982-12-28 | Formation of positioning mark |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59121836A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2767594B2 (en) * | 1988-11-16 | 1998-06-18 | 富士通株式会社 | Method for manufacturing semiconductor device |
| JPH02230718A (en) * | 1989-03-03 | 1990-09-13 | Nec Corp | Aligning mark and manufacture thereof |
-
1982
- 1982-12-28 JP JP57227602A patent/JPS59121836A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59121836A (en) | 1984-07-14 |
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