JPS62137831A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62137831A
JPS62137831A JP27970385A JP27970385A JPS62137831A JP S62137831 A JPS62137831 A JP S62137831A JP 27970385 A JP27970385 A JP 27970385A JP 27970385 A JP27970385 A JP 27970385A JP S62137831 A JPS62137831 A JP S62137831A
Authority
JP
Japan
Prior art keywords
film
photoresist
hole
multilayer
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27970385A
Other languages
Japanese (ja)
Inventor
Akinori Shimizu
清水 明徳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27970385A priority Critical patent/JPS62137831A/en
Publication of JPS62137831A publication Critical patent/JPS62137831A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To form a hole, which has sufficiently tapered wall so that a metal wiring is not broken, in an insulating film only by anisotropic etching, by using a multilayer positive photoresist film, in which upper layers have higher optical sensitivity than that of the lower layers, as a mask for etching when the hole is formed in the insulating film. CONSTITUTION:A PSG film 2 is formed on one main surface of a semiconductor substrate 1. A three-layer photoresist film, in which the sensitivity of the upper layer film is higher than that of the lower layer film, is formed on the surface of the PSG film 2. Then, exposure and development are performed with a specified mask pattern, and a hole is formed at a specified region in the photoresist film. Because of the difference in the optical sensitivity in the photoresist films, the opening parts of the photoresist films 3, 4 and 5 become large in this order. When these parts are adequately baked, the side surface of the holes in the multilayer photoresist films becomes considerably smooth. With the tapered multilayer photoresist films 3, 4 and 5 as masks, reactive ions 7 are projected from the upper part of the substrate using an RIE method, and the PSG film 2 is etched away. The tapered part is slowly retreated, and the tapered part is formed in the hole in the PSG film.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に絶縁膜に開
孔を形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming openings in an insulating film.

〔従来の技術〕[Conventional technology]

従来、半導体基板上に形成した絶縁膜に開孔を形成する
には、例えば第2図に示すように、半導体基板lの一主
面に形成されたリン珪酸ガラス(以下PSGという)膜
2の表面上にポジ型フォトレジスト6を塗布し、所定の
マスクパターンで露光、現像し7オトレジスト膜に開孔
を形成した後、491にベークして開孔側面の7オトレ
ジスト6をたらす(第2図(a))。次に、反応性イオ
ンエツチング(以下RIEという)法を用いて基板上方
から反応性イオン7を照射し異方性エツチングを行ない
フォトレジスト6で被覆されていないPSG膜2に開孔
を形成する(第2図(b))。ところで、ベークにより
たらしてもフォトレジスト6の開孔側面につくテーパー
はわずかであり、エツチング前のフォトレジスト形状8
と比較してエツチング中のフォトレジストの後退量もわ
ずかである。
Conventionally, in order to form an opening in an insulating film formed on a semiconductor substrate, for example, as shown in FIG. A positive type photoresist 6 is applied on the surface, exposed and developed in a predetermined mask pattern to form an opening in the photoresist film 7, and then baked to a temperature of 491 to form a photoresist 6 on the side surface of the opening (see Fig. 2). (a)). Next, using a reactive ion etching (hereinafter referred to as RIE) method, reactive ions 7 are irradiated from above the substrate to perform anisotropic etching to form openings in the PSG film 2 that is not covered with the photoresist 6 ( Figure 2(b)). By the way, the taper formed on the side surface of the opening in the photoresist 6 is slight even when baked, and the shape of the photoresist 8 before etching is small.
The amount of retreat of the photoresist during etching is also small compared to the previous one.

そのため、第2図(bl K示すようにPSG膜の開孔
側面にはほとんどテーパーがつかないので、その後の工
程でPSG膜の開孔を覆う金属配線を形成すると開孔上
端で段切れが生じやすい。そこで、第3図に示すように
、第2図(a)に示した工程に続いて、まず弗酸緩衝液
を用いてPSG膜の開孔上部全適量だけ等方性エツチン
グを行ない、次いで残部をR,IE法を用いて異方性エ
ツチングして開孔を形成し開孔上端の角を落とす方法が
行なわれている。
Therefore, as shown in Figure 2 (bl Therefore, as shown in Fig. 3, following the step shown in Fig. 2(a), first an appropriate amount of the entire upper part of the pores of the PSG film is isotropically etched using a hydrofluoric acid buffer. Next, the remaining portion is anisotropically etched using the R, IE method to form an opening, and the upper corner of the opening is rounded.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の等方性エツチングと異方性エツチングを
併用する方法は、特に絶縁膜としてPSG膜を用いる場
合、弗酸緩衝液によるPSG膜のエツチング速度がきわ
めて大きいため、開孔の広がりがきわめて大きくなり、
素子の微細化に不利である。また、弗酸緩衝液中のごみ
がウェハ表面に付着し、開孔部は不良を引き起す大きな
欠点がある。本発明は、上記の欠点を解消し異方性エツ
チングのみで絶縁膜の開孔に金属配線が断線しない十分
なテーパーのついた開孔を形成する方法を提供すること
全目的とする。
In the above-mentioned conventional method of combining isotropic etching and anisotropic etching, especially when a PSG film is used as an insulating film, the etching rate of the PSG film with a hydrofluoric acid buffer is extremely high, so the openings are extremely wide. grow bigger,
This is disadvantageous for miniaturization of elements. Further, there is a major drawback in that dirt in the hydrofluoric acid buffer adheres to the wafer surface, causing defects in the openings. It is an object of the present invention to provide a method for eliminating the above-mentioned drawbacks and forming an opening in an insulating film with a sufficient taper to prevent metal wiring from breaking by using only anisotropic etching.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明の半導体装置の製造方法は絶縁膜を有する半2A
t体基板の一生面につ′力感度の異なる2種以上のポジ
型フォトレジスト1漠金上層映が下層膜よりも高感度と
なるように積層して多層フォトレジスト膜を形成する工
程と、前記多層フォトレジスト膜を所定のマスクパター
ンで露光、現像して側面が膜の外側に向って開いた開孔
を形成する工程と、前記開孔を有する多層フォトレジス
ト膜?マスクとして異方性エツチング法により前記絶縁
膜に開孔を形成し開孔上部の絶縁膜側面に傾斜を持たせ
ることを特徴とする。
The method for manufacturing a semiconductor device of the present invention includes a semi-conductor having an insulating film.
forming a multilayer photoresist film by laminating two or more types of positive photoresists having different stress sensitivities on the entire surface of the T-body substrate so that the upper layer has higher sensitivity than the lower layer; A step of exposing and developing the multilayer photoresist film with a predetermined mask pattern to form an opening whose side surface is open toward the outside of the film, and a multilayer photoresist film having the opening? The method is characterized in that an opening is formed in the insulating film using an anisotropic etching method as a mask, and the side surface of the insulating film above the opening is sloped.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜Fd)は本発明の一実施例の工程j唄縦
断面図である。
FIGS. 1(a) to 1(Fd) are vertical cross-sectional views of step J of an embodiment of the present invention.

まず、第1図(a)に示すように、半導体基板1の一生
面に形成されたP2O[2の表面に、第1のポジ型フォ
トレジスト膜3を塗布する。さらに、フォトレジスト膜
3の上にこれより光感度の高い第2のポジ型フォトレジ
スト4を塗布する。更に、フォトレジスト膜4の上に、
これより更に光感度が高い第3のポジ型フォトレジスト
膜5を塗布し、上層膜が下層膜よりもより高感度である
3層のホトレジスト膜を形成する。
First, as shown in FIG. 1(a), a first positive photoresist film 3 is applied to the surface of P2O[2 formed on the entire surface of the semiconductor substrate 1. Furthermore, a second positive type photoresist 4 having higher photosensitivity is coated on the photoresist film 3. Furthermore, on the photoresist film 4,
A third positive type photoresist film 5 having even higher photosensitivity is applied to form a three-layer photoresist film in which the upper layer has higher sensitivity than the lower layer.

次いで、第1図(b)に示すように所定のマスクパター
ンで露光、現像しフォトレジスト膜の所定領域に開孔を
形成する。このとき、フォトレジスト膜の光感度の差に
より、7オトレジスト膜3,4゜5の順に各々のフォト
レジスト膜の開孔部分が大きくなる。
Next, as shown in FIG. 1B, exposure and development are performed using a predetermined mask pattern to form openings in predetermined areas of the photoresist film. At this time, due to the difference in photosensitivity of the photoresist films, the openings in each of the photoresist films become larger in the order of 7 photoresist films 3 and 4.5.

次いで、第1図(C)に示すように、これを適切にベー
クすると多層フォトレジスト膜の開孔側面がかなりなめ
らかになシ、かつ一層の7オトレジスト膜に比べて十分
に大きなテーパーを有し外方に開いた形状をもつ開孔が
形成される。
Next, as shown in FIG. 1(C), when this is properly baked, the side surfaces of the openings in the multilayer photoresist film are quite smooth and have a sufficiently large taper compared to the single layer 7 photoresist film. An aperture having an outwardly open shape is formed.

次に、第1図(d)に示すように、このようなテーパー
の付いた多/i17オトレジス)[3,4,5’iマス
クとしてRIE法を用いて基板上方から反応性イオン7
を照射してPSG膜2をエツチング除表スる。エツチン
グ前の多層フォトレジスト形状8′は、−1−フォトレ
ジスト形状8に比較してフォトレジストの開孔側面が外
方に開いたよりゆるやかな傾斜を有しているため、エツ
チング中に多層7オトレジス)M3 、4 、5の開孔
のテーパ一部分が一層フオドレジストの場合よりも多く
エツチングされて徐々に後退し、その分PEG膜の開孔
にテーパーが形成される。
Next, as shown in FIG. 1(d), reactive ions 7 are injected from above the substrate using the RIE method as a tapered poly/i17 otres) [3,4,5'i mask.
The PSG film 2 is removed by etching. The multilayer photoresist shape 8' before etching has a more gradual slope with the opening side surfaces of the photoresist opening outward compared to the -1-photoresist shape 8. ) A portion of the taper of the openings M3, 4, and 5 is etched more than in the case of the photoresist and gradually recedes, forming a corresponding taper in the opening of the PEG film.

通常、PSGgの反応性イオンエツチングはCF47H
2系あるいはCHF3102系のガスで行われる。その
時のpsogの7オトレジストaに対するエツチング選
択比は、2.5〜5.0程度であるが、ガス流量比を変
えることにより、エツチング選択比を変えることができ
、必要なフォトレジストの後退量を制御できる。
Usually, reactive ion etching of PSGg is performed using CF47H.
It is carried out using 2-based or CHF3102-based gas. At that time, the etching selectivity ratio of psog to 7 photoresist a is about 2.5 to 5.0, but by changing the gas flow rate ratio, the etching selectivity ratio can be changed, and the required amount of photoresist regression can be adjusted. Can be controlled.

また、本実施例では、3層の7オトレジスト膜について
説明したが、さらに多層のフォトレジスト膜を用いるこ
とにより、フォトレジスト開孔によりなめらかなデーパ
−をつけることができる。
Further, in this embodiment, a three-layer 7 photoresist film has been described, but by using a multilayer photoresist film, a smooth taper can be formed by the photoresist openings.

また、フォトレジストの層の数や、光感度、露光条件を
選ぶことにより、エツチング条件の選択と合せて、RI
E法のみで、種々の広がり、傾斜角をもつ絶縁膜の開孔
形成が可能となる。
In addition, by selecting the number of photoresist layers, photosensitivity, and exposure conditions, RI
Using only the E method, it is possible to form holes in an insulating film having various extents and angles of inclination.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、絶縁膜に開孔を形成する
際のエツチングのマスクとして、上層はどより光感度の
高い膜を配して積層した多層ポジ型フォトレジスト膜を
用いることにより、異方性エツチング法のみを用いて絶
縁膜の開孔側面にテーパーをつけることができるので素
子の微細化に大変有利である。また、湿式エツチング法
のようなごみ付着も少なく、半導体装置の製造歩留シ向
上に大きな効果がある。
As explained above, the present invention uses a multilayer positive photoresist film in which a film with higher photosensitivity is placed in the upper layer as an etching mask when forming holes in an insulating film. Since the side surface of the opening in the insulating film can be tapered using only the anisotropic etching method, it is very advantageous for miniaturizing the device. Furthermore, unlike the wet etching method, there is less dust adhesion, which is highly effective in improving the manufacturing yield of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明の一実施例の工程順縦断
面図、第2図(a)〜(b)は従来技術を示す工程順縦
断面図、第3図は他の従来技術を示す縦断面図である。 1・・・・・・半導体基板、2・・・・・・リン珪酸ガ
ラス(PSC))IO13,4,5,6・・・・・・ポ
ジ型フォトレジスト膜、7・・・・・・反応性イオン、
8.8’・・・・・・エツチング前のフォトレジスト形
状。 代理人 弁理士  内 原   日、   1茅 1 
図 $ 2 図 $ 3 図
FIGS. 1(a) to (d) are vertical cross-sectional views in the order of steps of an embodiment of the present invention, FIGS. 2(a) to (b) are longitudinal cross-sectional views in the order of steps showing the prior art, and FIG. FIG. 1... Semiconductor substrate, 2... Phosphorsilicate glass (PSC)) IO13, 4, 5, 6... Positive photoresist film, 7... reactive ions,
8.8'...Photoresist shape before etching. Agent Patent attorney Hi Uchihara, 1 Kaya 1
Figure $ 2 Figure $ 3 Figure

Claims (1)

【特許請求の範囲】[Claims]  絶縁膜を有する半導体基板の一主面に光感度の異なる
2種以上のポジ型フォトレジスト膜を上層膜が下層膜よ
りも高感度となるように積層して多層フォトレジスト膜
を形成する工程と、前記多層フォトレジスト膜を所定の
マスクパターンで露光、現像して側面が膜の外側に向っ
て開いた開孔を形成する工程と、前記開孔を有する多層
フォトレジスト膜をマスクとして異方性エッチング法に
より前記絶縁膜に開孔を形成し開孔上部の絶縁膜側面に
傾斜を持たせることを特徴とする半導体装置の製造方法
forming a multilayer photoresist film by laminating two or more types of positive photoresist films with different photosensitivity on one main surface of a semiconductor substrate having an insulating film so that the upper layer film has higher sensitivity than the lower layer film; , exposing and developing the multilayer photoresist film with a predetermined mask pattern to form apertures with side surfaces opening toward the outside of the film; and using the multilayer photoresist film having the apertures as a mask, anisotropic A method of manufacturing a semiconductor device, comprising forming an opening in the insulating film by an etching method, and making a side surface of the insulating film above the opening slope.
JP27970385A 1985-12-11 1985-12-11 Manufacture of semiconductor device Pending JPS62137831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27970385A JPS62137831A (en) 1985-12-11 1985-12-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27970385A JPS62137831A (en) 1985-12-11 1985-12-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62137831A true JPS62137831A (en) 1987-06-20

Family

ID=17614698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27970385A Pending JPS62137831A (en) 1985-12-11 1985-12-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62137831A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02208933A (en) * 1989-02-08 1990-08-20 Mitsubishi Electric Corp Formation of contact hole
US6448183B1 (en) * 1999-11-11 2002-09-10 Anam Semiconductor Inc. Method of forming contact portion of semiconductor element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02208933A (en) * 1989-02-08 1990-08-20 Mitsubishi Electric Corp Formation of contact hole
US6448183B1 (en) * 1999-11-11 2002-09-10 Anam Semiconductor Inc. Method of forming contact portion of semiconductor element

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