JPS62177922A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form the fine patterns of resists for upper and lower layers by exposing a foundation mark, baking the fine pattern to the resist having low sensitivity for the upper layer and developing the resist having high sensitivity for the lower layer. CONSTITUTION:A lower-layer positive resist 4 is applied onto a foundation 2, and baked, and an upper-layer positive resist 3 is applied and baked. Only a positioning section is exposed and developed by a mask using only a positioning pattern section as a bored section, and an opening section 8 for a resist pattern is shaped. An element region is positioned, exposed and developed, and a fine pattern is formed to the resist 3. Since the resist 4 has sensitivity of several times as high as the resist 3 at that time, the resist 4 is developed easily, thus forming a fine pattern 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a photolithography technique for semiconductor devices, and relates to a method of eyelet exposure that provides the formation of fine patterns and precise eyelet precision. be.

[Conventional technology]

Conventionally, as a photographic etching method, an exposure method using ultraviolet light has been used, and in recent years, a stepper exposure method has been particularly adopted. Although the stepper exposure method provides extremely high alignment accuracy, it is sensitive to irregularities on the surface of the wafer substrate, making it extremely difficult to form fine patterns, especially patterns of 1 μm or less. However, surface irregularities are usually unavoidable. Therefore, in general, a multilayer resist process in which two or more layers of resist are laminated to form a pattern is used to planarize the surface and form a fine pattern.

[Problem that the invention seeks to solve]

However, the multilayer resist process described above has the following problems. In other words, since a large number of resists are stacked, light interference and scattering occur in the resist layers, resulting in inaccurate detection of alignment marks formed on the wafer surface, resulting in extremely poor alignment accuracy. turn into. Although a fine pattern can be formed using a multilayer resist process, the two-position alignment becomes poor and the original function cannot be achieved.

[Means for solving problems]

In order to solve the above-mentioned problems, in the present invention, using 2ai resists with different sensitivities for the same developer, the exposure and development of only the alignment mark part is completed in advance, and the underlying mark is exposed. After that, a fine pattern is printed on the upper layer of low-sensitivity resist, and then the lower layer of high-sensitivity resist is developed to form the fine pattern of the upper and lower resist layers. Thereafter, using the upper resist as a mask, anisotropic etching is performed by RIE (reactive ion etching) to transfer and form a fine pattern onto the base wafer substrate.

〔Example〕

Next, examples of the present invention will be shown.

FIG. 1 is a sectional view of one embodiment of the present invention.

1 is a wafer substrate, 2 is an insulating film such as an oxide film formed on the substrate, 3 is an upper layer positive resist, and 4 is a lower layer positive resist. Compared to resist 4, resist 3 has the same development conditions. The resist should have a low sensitivity to the extent that it can be exposed to several times the amount of light.

5 is a fine pattern formed on the upper resist 3 and the lower resist 4; 6 is a fine pattern formed on the base 2;
7 is an alignment pattern on the base 2, and 8 is an alignment pattern opening in the resist portion.

FIGS. 2(a) to 2(e) show the manufacturing method according to the present invention.

First, the lower layer positive resist 4 is applied on the base 2 and baked, and then the upper layer positive resist 3 is applied and baked (regular pattern)). Here, the purpose of the resist 4 is to flatten the unevenness of the underlying layer, and the purpose of the resist 3 is to form a fine pattern. Therefore, it is better for the resist 3 to be as thin as possible (0.4 to 0.5 μm at most) and for the resist 4 to be relatively thick, but when the resist 3 is exposed and developed, it is necessary to be able to develop it at the same time. The film thickness of the resist 3 is preferably about 2 to 3 times that of the resist 3 at most.

Next, only the alignment part is exposed and developed using a mask with only the alignment pattern part as a bright part, thereby forming the opening 8 of the resist pattern (FIG. 2(b)).

Since the purpose of the alignment method here is simply to expose the underlying alignment pattern 7, precise alignment is not required, and a contact exposure method or a thermal stepper may be used. Next, alignment exposure and
Development is performed to form a fine pattern on the upper resist layer. At this time, since the lower resist layer 4 has several times the sensitivity as compared to the upper layer, it is easily developed and the fine pattern 5 is formed as shown in FIG. can be formed. After that, if an etching method with strong anisotropy such as RIE is used, the pattern 5 formed in the upper layer resist) K is transferred as it is to the base 2, and a fine pattern 6 is formed (FIG. 1(d)). ). After that, the resists 3 and 4 on the surface are removed, and the same figure (e) is obtained.
The shape is obtained.

〔Effect of the invention〕

As explained above, according to the present invention, first, by exposing and developing only the alignment mark portion, the underlying alignment pattern can be exposed, and then the alignment exposure of the element region can be performed. There is no effect of light scattering or interference due to the use of , making it possible to achieve precise alignment. Furthermore, since the flatness of the multilayer resist can be utilized as is, it has the effect that fine patterns can be easily formed even on uneven wafer substrates.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a structure obtained according to an embodiment of the present invention, and FIG. 2) to FIG. 2(e) are process cross-sectional views showing an embodiment of the present invention. 1... Wafer substrate, 2... Insulating film,
3... Upper layer positive resist, 4... Lower layer positive resist, 5... Pattern formed on resist, 6... Fine pattern formed on base. , 7... Alignment pattern on wafer substrate, 8
・・・・・・Resist alignment opening. 2nd mother (C) 2nd zo (cL> 2nd figure <e)

Claims (1)

[Claims] A step of applying a first resist on one principal surface of the semiconductor substrate, a step of applying a second resist having lower sensitivity than the resist, and a step of applying a first resist only on the alignment pattern region on the semiconductor substrate. A step of exposing and developing a second resist, a step of exposing, developing and baking an element pattern on the first and second resists on the element region on the semiconductor substrate, and anisotropic etching, A method for manufacturing a semiconductor device, comprising the steps of: transferring and forming the element pattern;