JPH02177318A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02177318A
JPH02177318A JP63330897A JP33089788A JPH02177318A JP H02177318 A JPH02177318 A JP H02177318A JP 63330897 A JP63330897 A JP 63330897A JP 33089788 A JP33089788 A JP 33089788A JP H02177318 A JPH02177318 A JP H02177318A
Authority
JP
Japan
Prior art keywords
film
photoresist film
photosensitive layer
photoresist
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63330897A
Other languages
Japanese (ja)
Inventor
Masato Tanaka
正人 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63330897A priority Critical patent/JPH02177318A/en
Publication of JPH02177318A publication Critical patent/JPH02177318A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

PURPOSE:To form a fine pattern without using an expensive method by exposing the side face of a positive photoresist film so as to form a photosensitive layer, and forming a photoresist film which has fine patterns making use of the thickness of its photosensitive layer. CONSTITUTION:An Si oxide film 2 is formed on an Si substrate 1, and a positive photoresist film 3 is formed on the film 2, and is patterned. Next, the upper face and side face of the film 3 is exposed so as to form a photosensitive layer 4. Next, a positive photoresist film 5 is formed at the surface inclusive of the film 3 and film 4. Next, by development the film 5 on the layer 4 and the top of the layer 4 are removed, and at the same time the side of the layer 4 is removed so as to form an opening 6. Next, with the film 3 and 5 as masks, the film 2 and the substrate 1 are etched anisotropically in order and grooves 7 are formed. Hereby, fine patterns can be formed without using an expensive method unsuitable for mass-production.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に微細パター
ンの形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a fine pattern.

〔従来の技術〕[Conventional technology]

従来の半導体装置の製造方法は、縮小投影露光法や電子
ビームを用いた露光方法、また最近ではレーザーや加速
粒子を用いた露光方法を用いて微細パターン用フォトレ
ジスト層をノ(ターニングし、幅1μm程度の微細パタ
ーンを形成している。
Conventional semiconductor device manufacturing methods use reduction projection exposure methods, exposure methods using electron beams, and more recently exposure methods using lasers and accelerated particles to turn the photoresist layer for fine patterns to increase the width. A fine pattern of about 1 μm is formed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置の製造方法は、光を用いてパ
ターンを露光する場合、光の波長等による解像力に限界
があるため、0.5μm以下のノ(ターン形成は不可能
である。また電子ビーム等の加速粒子を用いた場合、光
よりは解像力の点で優れているが、装置の価格、処理量
等を考慮した場合、量産工程にこれらの方法を使用する
のは効率が悪いという問題点がある。
In the conventional semiconductor device manufacturing method described above, when exposing a pattern using light, there is a limit to the resolution depending on the wavelength of the light, etc., so it is impossible to form a turn of 0.5 μm or less. When using accelerated particles such as a beam, it has better resolution than light, but when considering the cost of the equipment, throughput, etc., it is inefficient to use these methods in mass production processes. There is a point.

本発明の目的は、高額で且つ量産に不向きな方法を使用
せずに@細なパターン形成が可能な半導体装置の製造方
法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can form a fine pattern without using an expensive method that is unsuitable for mass production.

〔課題な解決するための手段〕[Means to solve problems]

本発明の半導体装置の製造方法は、半導体基板上に被エ
ツチング膜とポジ型の第1のフォトレジスト膜とを順次
形成する工程と、前記第1のフォトレジスト膜をバター
ニングしたのち該第1のフォトレジスト膜を所定時間露
光しその上面および側面に感光層を形成する工程と、前
記感光層を含む全面にポジ型の第2のフォトレジスト膜
を形成したのち前記第1のフォトレジスト膜の表面が露
光するまで該第2のフォトレジスト膜を現像により除去
すると同時に前記側面の感光層を除去し開口部を形成す
る工程と、開口部により分離された前記第1および第2
のフォトレジスト膜をマスクとしij記被エツチング膜
をエツチングする工程とを含んで構成される。
The method for manufacturing a semiconductor device of the present invention includes the steps of sequentially forming a film to be etched and a positive first photoresist film on a semiconductor substrate, and after buttering the first photoresist film, the first photoresist film is patterned. A step of exposing the photoresist film for a predetermined time to form a photosensitive layer on the top and side surfaces of the photoresist film, forming a positive second photoresist film on the entire surface including the photosensitive layer, and then forming a positive photoresist film on the entire surface including the photoresist film. removing the second photoresist film by development until the surface is exposed, and simultaneously removing the photosensitive layer on the side surface to form an opening;
The method includes a step of etching the film to be etched using the photoresist film as a mask.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(f)は本発明の第1の実施例を説明す
るための工程順に示した半導体チップの断面図であり、
本発明を溝分離に適用した場合を示している。
FIGS. 1(a) to 1(f) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention,
This shows a case where the present invention is applied to groove separation.

まず、第1図(a)に示すように、シリコン基板1の上
に酸化シリコン膜2を形成し、酸化シリコン膜2の上に
厚さ2 ノLmのポジ型の第1のフォトレジスト膜3を
形成し、バターニングする。
First, as shown in FIG. 1(a), a silicon oxide film 2 is formed on a silicon substrate 1, and a positive type first photoresist film 3 with a thickness of 2 Lm is formed on the silicon oxide film 2. Form and butter.

次に第1図(b)に示すように、第1のフォトレジスト
膜3の上面及び側面を深さ0.3μmまで露光して感光
層4を形成する。
Next, as shown in FIG. 1(b), the top and side surfaces of the first photoresist film 3 are exposed to a depth of 0.3 μm to form a photosensitive layer 4.

次に第1[](c)に示すように、第1のフォトレジス
ト膜3及び感光N4を含む表面にポジ型の第2のフォト
レジスト膜5を塗布法により形成する。
Next, as shown in 1[](c), a positive type second photoresist film 5 is formed on the surface including the first photoresist film 3 and the photosensitive material N4 by a coating method.

次に第1図(d)に示すように、現像により感光層4上
の第2のフォトレジストM5と上面の感光層4を除去す
ると同時に、側面の感光層4を除去して開口部6を形成
する。この時、第1のフォトレジストpIA3として、
例えば0FPR800C(東京応化工業社製)を用いた
場合、その未露光部の現像液、例えばNMD−3(同社
製)に対する溶解速度は室温で約0.1μrn /分で
あり、感光層ノ1の同じく溶解速度は約2μm/分であ
るがら、感光M4上の第2のフォトレジスト膜5の厚さ
が1μInの場合、11分の現像時間を必要とする。こ
こで、現像前に第2のフォトレジスト膜5を表面から1
μr口の深さまで露光して感光させておけば、現像時間
は1.5分まで短縮することができる。
Next, as shown in FIG. 1(d), the second photoresist M5 on the photosensitive layer 4 and the photosensitive layer 4 on the top surface are removed by development, and at the same time, the photosensitive layer 4 on the side surfaces is removed to form the opening 6. Form. At this time, as the first photoresist pIA3,
For example, when using 0FPR800C (manufactured by Tokyo Ohka Kogyo Co., Ltd.), the dissolution rate of the unexposed area in a developer such as NMD-3 (manufactured by the same company) is about 0.1 μrn/min at room temperature, and the Similarly, although the dissolution rate is approximately 2 μm/min, if the thickness of the second photoresist film 5 on the photosensitive M4 is 1 μIn, a development time of 11 minutes is required. Here, before development, the second photoresist film 5 is coated one layer from the surface.
By exposing to the depth of the μr port, the development time can be shortened to 1.5 minutes.

次に第1図(e)に示すように、第1及び第2のフォト
レジスト膜3及び5をマスクとして酸化シリコン膜2及
びシリコン基板1を順次RIE法により胃方性エツチン
グして深さ0.3μmの溝7を形成する。
Next, as shown in FIG. 1(e), using the first and second photoresist films 3 and 5 as masks, the silicon oxide film 2 and silicon substrate 1 are sequentially etched by RIE to a depth of 0. .3 μm groove 7 is formed.

次に第1図(f)に示すように、第1及び第2のフォト
レジスト膜3及び5を除去した後、熱酸化法により溝7
に酸化シリコン膜8を形成することにより、幅0.3μ
mの溝分離が完了する。この時、熱酸化法の他にシリカ
フィルム等のSOG法(スピンオングラス)又はLPC
VD法を併用して絶縁物又はポリシリコンを満7に埋め
ても良い 第2図(a)〜(e)は本発明の第2の実施例を説明す
るための工程順に示した半導体チップの断面図であり、
本発明を平坦な配線形成に適用した場合を示している。
Next, as shown in FIG. 1(f), after removing the first and second photoresist films 3 and 5, the trenches 7 are removed by thermal oxidation.
By forming the silicon oxide film 8 on the
m groove separation is completed. At this time, in addition to the thermal oxidation method, SOG method (spin-on glass) or LPC using silica film etc.
The VD method may also be used to fill the insulator or polysilicon to the full extent. Figures 2(a) to 2(e) show semiconductor chips in order of process for explaining the second embodiment of the present invention. A cross-sectional view,
This shows a case where the present invention is applied to flat wiring formation.

まず第2図(a)に示すように、シリコン基板1に素子
形成後、その上に酸化シリコン膜2を形成しコンタクト
孔9を形成する0次で全面に厚さ1μmのアルミニウム
WilOをスパッタリング法により堆積する0次にアル
ミニウム膜1oの上に厚さ2μmのポジ型の第1のフォ
トレジストII!3を形成してバターニングする。
First, as shown in FIG. 2(a), after a device is formed on a silicon substrate 1, a silicon oxide film 2 is formed thereon, and a contact hole 9 is formed by sputtering aluminum WilO with a thickness of 1 μm over the entire surface. A positive type first photoresist II with a thickness of 2 μm is deposited on the zero-order aluminum film 1o deposited by ! Form 3 and butter.

次に第2図(b)に示すように、第1のフォトレジスト
膜3の上面及び側面を深さOjμバ1まで露光して感光
層4を形成したのち、全面にポジ型の第2のフォトレジ
ストM5を塗布法により形成する。
Next, as shown in FIG. 2(b), after exposing the top and side surfaces of the first photoresist film 3 to a depth of Ojμ 1 to form a photosensitive layer 4, a second positive type film is coated on the entire surface. A photoresist M5 is formed by a coating method.

次に第2図(c)に示すように、現像により感光層4上
の第2のフォトレジストllll5を除去すると同時に
、感光層4を除去して開口部6を形成する。
Next, as shown in FIG. 2(c), the second photoresist llll5 on the photosensitive layer 4 is removed by development, and at the same time, the photosensitive layer 4 is removed to form an opening 6.

次に第2図(d)に示すように、第1及び第2のフォト
レジスト膜3及び5をマスクとしてアルミニウム110
をRIE法により異方性エツチングして0.3μmの溝
7を形成した後、第1及び第2のフォトレジストWA3
.5を除去する。
Next, as shown in FIG. 2(d), using the first and second photoresist films 3 and 5 as masks, aluminum 110
After forming grooves 7 of 0.3 μm by anisotropic etching using the RIE method, the first and second photoresists WA3 are etched.
.. Remove 5.

次に第2図(e)に示すように、陽極酸化法によりアル
ミニウム膜lOの上面及び側面を酸化アルミニウムpA
11に変せしめる。この時、アルミニウムが多孔性の酸
化アルミニウムに変化すると、体積は約1.3倍に膨張
するので溝7は酸化アルミニウム膜11によって埋めら
れる。ここで陽極酸化法を用いたが、その他シリカフィ
ルム等のSOG法やプラズマ窒化膜、又はプラズマ酸化
膜法を用いて絶縁物を溝7に埋めても良い。
Next, as shown in FIG. 2(e), the top and side surfaces of the aluminum film IO are coated with aluminum oxide pA by anodizing.
Change it to 11. At this time, when the aluminum changes to porous aluminum oxide, the volume expands approximately 1.3 times, so the groove 7 is filled with the aluminum oxide film 11. Although the anodic oxidation method is used here, the groove 7 may be filled with an insulator using an SOG method using a silica film, a plasma nitride film, or a plasma oxide film method.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ポジ型のフォトレジスト
膜側面を露光して感光層を形成し、その感光層の厚さを
利用して微細パターンを有するフォトレジスト膜を形成
することにより、1μm以下の微細パターンの溝を被エ
ツチング体に容易に形成できるため、半導体装置の集積
度を向上させることができるという効果がある。
As explained above, the present invention exposes the side surface of a positive photoresist film to form a photosensitive layer, and utilizes the thickness of the photosensitive layer to form a photoresist film having a fine pattern of 1 μm. Since grooves having the following fine patterns can be easily formed on the object to be etched, there is an effect that the degree of integration of semiconductor devices can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(f)及び第2図(a)〜くe)は本発
明の第1及び第2の実施例を説明するための工程順に示
した半導体チップの断面図である。 1・・・シリコン基板、2・・・酸化シリコン膜、3・
・・第1のフォトレジスト膜、4・・・感光層、5・・
・第2のフォトレジスト膜、6・・・開口部、7・・・
溝、8・・・酸化シリコン孜、9・・・コンタクト孔、
10・・・アミニウム膜、11・・・酸化アルミニウム
膜。
FIGS. 1(a)-(f) and FIGS. 2(a)-(e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first and second embodiments of the present invention. 1... Silicon substrate, 2... Silicon oxide film, 3.
...first photoresist film, 4...photosensitive layer, 5...
- Second photoresist film, 6... opening, 7...
Groove, 8... silicon oxide layer, 9... contact hole,
10... Aminium film, 11... Aluminum oxide film.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に被エッチング膜とポジ型の第1のフォト
レジスト膜とを順次形成する工程と、前記第1のフォト
レジスト膜をパターニングしたのち該第1のフォトレジ
スト膜を所定時間露光しその上面および側面に感光層を
形成する工程と、前記感光層を含む全面にポジ型の第2
のフォトレジスト膜を形成したのち前記第1のフォトレ
ジスト膜の表面が露光するまで該第2のフォトレジスト
膜を現像により除去すると同時に前記側面の感光層を除
去し開口部を形成する工程と、開口部により分離された
前記第1および第2のフォトレジスト膜をマスクとし前
記被エッチング膜をエッチングする工程とを含むことを
特徴とする半導体装置の製造方法。
A step of sequentially forming a film to be etched and a positive first photoresist film on a semiconductor substrate, and after patterning the first photoresist film, exposing the first photoresist film for a predetermined time to expose the upper surface thereof. and a step of forming a photosensitive layer on the side surface, and a step of forming a positive type second layer on the entire surface including the photosensitive layer.
After forming a photoresist film, removing the second photoresist film by development until the surface of the first photoresist film is exposed, and simultaneously removing the photosensitive layer on the side surface to form an opening; A method of manufacturing a semiconductor device, comprising the step of etching the film to be etched using the first and second photoresist films separated by an opening as a mask.
JP63330897A 1988-12-27 1988-12-27 Manufacture of semiconductor device Pending JPH02177318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63330897A JPH02177318A (en) 1988-12-27 1988-12-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63330897A JPH02177318A (en) 1988-12-27 1988-12-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02177318A true JPH02177318A (en) 1990-07-10

Family

ID=18237721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63330897A Pending JPH02177318A (en) 1988-12-27 1988-12-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02177318A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58217499A (en) * 1982-06-10 1983-12-17 Toshiba Corp Fine working method of thin film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58217499A (en) * 1982-06-10 1983-12-17 Toshiba Corp Fine working method of thin film

Similar Documents

Publication Publication Date Title
JPH02177318A (en) Manufacture of semiconductor device
JP2000173979A (en) Etching mask and method of forming fine pattern
JP2621624B2 (en) Method for manufacturing semiconductor device
JP2007312373A (en) Method of manufacturing semiconductor device and semiconductor device using the same
JPH0467333B2 (en)
JPS62137831A (en) Manufacture of semiconductor device
JPS6113627A (en) Manufacture of semiconductor device
JPS63258020A (en) Formation of element isolation pattern
JPH0670954B2 (en) Method for manufacturing semiconductor device
JPH0479321A (en) Production of semiconductor device
JPS61184831A (en) Manufacture of semiconductor device
JP2985884B1 (en) Method for manufacturing semiconductor device
JPS58100434A (en) Method for forming spacer for lift off
JPH0294439A (en) Manufacture of semiconductor device
KR100382548B1 (en) Method for Fabricating of Semiconductor Device
KR100247642B1 (en) Method for forming a contact hole in semiconductor device
JPH05267253A (en) Manufacture of semiconductor device
JPH04364726A (en) Pattern formation
JPH0353522A (en) Etching of vertical wall surface
JPH0348424A (en) Manufacture of semiconductor device
JPH0478168A (en) Mos semiconductor device thereof and manufacture
JPH0269934A (en) Manufacture of semiconductor device
JPS6321831A (en) Pattern forming method
JPS61296722A (en) Manufacture of semiconductor device
JPH05136130A (en) Manufacture of semiconductor device