JPS6113627A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6113627A JPS6113627A JP13491484A JP13491484A JPS6113627A JP S6113627 A JPS6113627 A JP S6113627A JP 13491484 A JP13491484 A JP 13491484A JP 13491484 A JP13491484 A JP 13491484A JP S6113627 A JPS6113627 A JP S6113627A
- Authority
- JP
- Japan
- Prior art keywords
- film
- etching
- si3n4
- poly
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000005530 etching Methods 0.000 claims abstract description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 238000001020 plasma etching Methods 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 3
- 229910018503 SF6 Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- 229960000909 sulfur hexafluoride Drugs 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法、特に半導体装置の集積
度の増大及びアクセススピードの短縮化のために、素子
の微細加工技術に利用されるもので、なかでもアスペク
ト比の大きい、微細コンタクトボールを形成する製造方
法に関するものであコンタクトホールを形成する目的は
、半導体装置の多層配線をする場合の各層間の電気接続
するための接続用ホールや、半導体基板に形成される電
極窓用のホール、その他素子間の分離等に利用されるも
ので、通常コンタクトホールを形成する際には基板に厚
いレジスト膜を被着してパターニングを行い、それを反
応性イオンエツチング（ＲＩｒｕ）装置によって、エツ
チングされてコンタクトナールが形成されるが、従来は
レジスト膜が厚（、そのためにパターニングの精度に限
度があって、形成されたコンタクトホールの形状は開口
部の一辺の長さが１．２μｍ程度が限度であり、従って
開口部の面積に比較して深さが長い、即ちアスペクト比
の大きい、例えば１μｍ２の開口面積で深さが１μｍ程
度のコンタクトホールを形成することは困難であり、そ
のために微細な半導体装置を製造するためにアスペクト
比の大きいコンタクトホールの容易且つ正確な形成方法
が要望されている。[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to a method for manufacturing a semiconductor device, and in particular to a microfabrication technology for elements in order to increase the degree of integration and shorten the access speed of a semiconductor device. The purpose of forming contact holes is to form connection holes for electrical connections between layers in multilayer wiring of semiconductor devices. , holes for electrode windows formed in semiconductor substrates, and other devices used for isolation between elements. Normally, when forming contact holes, a thick resist film is deposited on the substrate and patterned. This is then etched using a reactive ion etching (RIru) device to form a contact knurl, but in the past, the resist film was thick (therefore, there was a limit to the accuracy of patterning, and the shape of the formed contact hole was The maximum length of one side of the opening is about 1.2 μm, so the depth is long compared to the area of the opening, that is, the aspect ratio is large, for example, a contact with an opening area of 1 μm2 and a depth of about 1 μm. It is difficult to form holes, and therefore there is a need for an easy and accurate method for forming contact holes with a large aspect ratio in order to manufacture fine semiconductor devices.
従来から、アスペクト比の大きいコンタクトホールを形
成するには、異方性のエツチング特性を有する反応性イ
オンエツチング法が採用されている。Conventionally, a reactive ion etching method having anisotropic etching characteristics has been employed to form a contact hole with a large aspect ratio.
通常の反応性イオンエツチング装置は、ガスが充填され
る真空容器内に、基板が配置され、この基板に高周波電
力が印加されて、真空容器内に充填されたガスをイオン
化して、その活性種を基板に反応させてエツチングを行
なうものである。In a typical reactive ion etching device, a substrate is placed in a vacuum container filled with gas, and high-frequency power is applied to this substrate to ionize the gas filled in the vacuum container and remove its active species. Etching is performed by reacting with the substrate.
この反応性イオンエツチング法の大きな特徴としζ、異
方性エツチングが可能であることで、通常、反応性イオ
ンエツチングを行う場合には、エツチングすべき基板表
面に１．５μｍ程度のかなり厚みのあるレジスト膜を被
着して、そのレジスト膜をパターニングしてコンタクト
ホールを形成する部分を開口し、しかる後にその基板に
対して選択比のとれるガスを用いて反応性イオンエツチ
ング法でエツチングし、コンタクトホールを形成してい
る。A major feature of this reactive ion etching method is that anisotropic etching is possible.Usually, when performing reactive ion etching, the surface of the substrate to be etched has a considerable thickness of about 1.5 μm. A resist film is deposited, the resist film is patterned to open the area where the contact hole will be formed, and then the contact is etched by reactive ion etching using a gas with a selectivity to the substrate. It forms a hole.
このような場合、従来方法ではレジスト膜を厚くする必
要があるために、紫外線露光の場合にはレジスト面での
回折現象があり、又電子ビーム露光の場合には、レジス
ト中での散乱等により、アスペクト比の大きいコンタク
トホールを生成することが不可能であり、限度として精
々１．２μｍ程度の大きさであった。In such cases, conventional methods require a thicker resist film, which causes diffraction phenomena on the resist surface when exposed to ultraviolet light, and scattering within the resist when exposed to electron beams. However, it is impossible to create a contact hole with a large aspect ratio, and the size of the contact hole is at most about 1.2 μm.
上記のように、従来の反応性イオンエツチング法では、
基板エツチングに必要なレジスト膜の膜厚が厚いために
パターニングが高精度に出来ないという問題があり、従
ってこれに代わる方法として、反応性イオンエツチング
法によるエツチング速度が材料の種類により大きく差が
ある、所謂選択性エツチング効果があることに着目し、
材料の組合せで、いずれか一方の材料をマスクにしてエ
ツチングをする新しいエツチング方法を考慮したもので
ある。As mentioned above, in the conventional reactive ion etching method,
There is a problem that patterning cannot be performed with high precision due to the thick resist film required for substrate etching.Therefore, as an alternative method, reactive ion etching is used.The etching speed varies greatly depending on the type of material. , focusing on the so-called selective etching effect,
This is a new etching method that uses a combination of materials to perform etching using one of the materials as a mask.
本発明は上記問題点を解消した選択性工・ンチングが行
える材料の組合せを提供するもので、その手段は基板上
の窒化シリコン膜の表面に酸化シリコン膜又はポリシリ
コン膜を形成して、該酸化シリコン膜又はポリシリコン
膜にレジスト膜をパターニングしてコンタクトホールを
形成する部分を開口し、該開口部分から反応性イオンエ
ツチング法によって該酸化シリコン膜又はポリシリコン
膜のエツチングと、引続き該窒化シリコン膜のエツチン
グを行なって上記コンタクトホールを生成することを特
徴とする半導体装置の製造方法によって達成できる。The present invention provides a combination of materials that can be selectively processed to solve the above-mentioned problems. A resist film is patterned on a silicon oxide film or a polysilicon film to open a portion where a contact hole is to be formed, and the silicon oxide film or polysilicon film is etched from the opening using a reactive ion etching method, and then the silicon nitride film is etched. This can be achieved by a method of manufacturing a semiconductor device characterized in that the contact hole is created by etching a film.
（作用〕
即ち、本発明は酸化シリコン膜と窒化シリコン膜とが特
定のイオンガスに対してエツチング効果に大きな差を有
する高い選択性エツチング特性を有することを利用し、
同様にポリシリコン膜と窒化シリコン膜も、特定のイオ
ンガスに対して同様に高い選択性をエツチング特性を有
している等、その選択性エツチングの差を利用して二層
の膜を形成し、その膜の表面側のマスクとして作用する
膜には、従来のレジスト膜の厚みに比較して、極めて薄
いレジスト膜で高精度のパターニングを行ってコンタク
トホールを生成するものである。(Operation) That is, the present invention takes advantage of the fact that silicon oxide films and silicon nitride films have highly selective etching characteristics that have a large difference in etching effect with respect to specific ion gases.
Similarly, polysilicon films and silicon nitride films have similar etching properties with high selectivity for specific ion gases, and the difference in etching selectivity can be utilized to form a two-layer film. The contact hole is created by highly accurate patterning using a resist film that is extremely thin compared to the thickness of a conventional resist film on the film that acts as a mask on the surface side of the film.
酸化シリコン膜と窒化シリコン膜とを四弗化炭素（ＣＦ
４ ）と酸素及び窒素の混合ガス中で反応性イオンエ
ツチングを行うか、又は六弗化硫黄（ＳＦ６）或いはフ
ロン３２（ＣＨ２Ｆ ２）ガス中で反応性イオンエツチ
ングを行うことにより、酸化シリコン膜と窒化シリコン
膜との間に、高い選択性エツチング特性があり、又ポリ
シリコン膜と窒化シリコン膜とをフロン１４ （ＣＦ４
）と水素と窒素との混合ガス中でＲＩＢを行う際にも
、同様にエソチン特性に高い選択性があり、そのエツチ
ング速度を比較すると１０〜２０倍程度の差になる。The silicon oxide film and the silicon nitride film are coated with carbon tetrafluoride (CF).
4) by performing reactive ion etching in a mixed gas of oxygen and nitrogen, or by performing reactive ion etching in sulfur hexafluoride (SF6) or fluorocarbon 32 (CH2F2) gas. It has a highly selective etching property between the silicon nitride film and the polysilicon film and the silicon nitride film.
), when performing RIB in a mixed gas of hydrogen and nitrogen, there is similarly high selectivity in etching properties, and when comparing the etching rates, the difference is about 10 to 20 times.
本発明は、この選択性エツチングの差を利用して一方の
材料のエツチングをする際には他方をマスクとして利用
するものであって、マスクとなる材料にのみ、その表面
に極めて薄いレジスト膜を被着するのみで、微細なコン
タクトホールの生成方法を提供するものである。The present invention utilizes this difference in selective etching to use one material as a mask when etching the other, and applies an extremely thin resist film on the surface of only the material that will serve as the mask. This provides a method for creating fine contact holes by simply depositing them.
第１図に本発明の実施例を示しているが、基板１０表面
に配線層２が配置されていて、その上に０．５乃至１．
５μｍの厚い窒化シリコン膜３が形成されてあり、その
表面に２０００人程度０酸化シリコン膜４又はポリシリ
コン膜が形成されている。An embodiment of the present invention is shown in FIG. 1, in which a wiring layer 2 is disposed on the surface of a substrate 10, and a wiring layer 2 of 0.5 to 1.
A silicon nitride film 3 with a thickness of 5 μm is formed, and a silicon nitride film 4 or a polysilicon film with a thickness of about 2000 is formed on its surface.
第２図は酸化シリコン膜４のパターニングを行うために
、厚さが３０００〜４０００人程度の極めて薄いレジス
日突５を形成し、このレジスト膜５を配線部分に対応し
てコンタクトホールを形成する部分を露光、エツチング
によってレジスト膜の開口部６を形成する。FIG. 2 shows that in order to pattern the silicon oxide film 4, an extremely thin resist film 5 with a thickness of about 3,000 to 4,000 layers is formed, and contact holes are formed in this resist film 5 corresponding to the wiring portions. An opening 6 in the resist film is formed by exposing and etching the portion.
第３図は、レジスト膜の開口された部分から、ＣＦ４と
ＣＩＩＦａとの混合ガスで反応性イオンエツチング法で
エツチングを行うことにより、酸化シリコン膜４をエツ
チングして開口部７を形成したものである。In FIG. 3, an opening 7 is formed by etching the silicon oxide film 4 from the opened portion of the resist film using a reactive ion etching method using a mixed gas of CF4 and CIIFa. be.
第４図は反応性イオンエツチングでエツチング速度を小
である酸化シリコン膜４をマスクとして引続き窒化シリ
コン膜を反応性イオンエツチング法でエツチングを行う
ことにより、選択エツチングの効果で酸化シリコン膜４
が僅かにエツチングされるが、窒化シリコン膜３は急速
度でエツチングがなされて、コンタクトホール８が形成
されることになる。FIG. 4 shows that the silicon nitride film is subsequently etched using the reactive ion etching method using the silicon oxide film 4, which has a low etching rate, as a mask.
Although the silicon nitride film 3 is etched slightly, the silicon nitride film 3 is etched rapidly and a contact hole 8 is formed.
このように反応性イオンエツチング法の、ガスを適当に
選択すれば、材料によってエツチング速度が大きく異な
る性質を利用して一方の材料をマスクとして形成したコ
ンタクトホールはアスペクト比が大であり、従来の厚い
レジスト膜を使用したコンタクトホールに比較して優れ
た形状が実現できる。In this way, if the gas in reactive ion etching is selected appropriately, contact holes formed using one material as a mask will have a large aspect ratio, taking advantage of the fact that the etching rate varies greatly depending on the material, which is different from conventional etching. A superior shape can be achieved compared to a contact hole using a thick resist film.
以上詳細に説明したように本発明による微細なコンタク
トホールの形成により、半導体装置の集積度の増大及び
微細化に供し得るという効果大なるものがある。As described in detail above, the formation of fine contact holes according to the present invention has the great effect of increasing the degree of integration and miniaturization of semiconductor devices.
第１図、第２図、第３図及び第４図はそれぞれ本発明の
コンタクトホールの形成工程を説明するための断面図で
ある。
図において、１は基板、２は配線層、３は窒化シリコン
膜、４は酸化シリコン膜、５はレジスト膜、６はレジス
ト膜の開口部、７は酸化シリコン膜の開口部、８はコン
タクトホールである。
第 １ 図
第 ３ 図
第４閃FIG. 1, FIG. 2, FIG. 3, and FIG. 4 are sectional views for explaining the contact hole forming process of the present invention, respectively. In the figure, 1 is a substrate, 2 is a wiring layer, 3 is a silicon nitride film, 4 is a silicon oxide film, 5 is a resist film, 6 is an opening in the resist film, 7 is an opening in the silicon oxide film, and 8 is a contact hole. It is. Figure 1 Figure 3 Figure 4 flash
Claims (1)
ポリシリコン膜を形成して、該酸化シリコン膜又はポリ
シリコン膜にレジスト膜をパターニングしてコンタクト
ホールを形成する部分を開口し、該開口部分から反応性
イオンエッチング法によって該シリコン酸化物又はポリ
シリコン膜のエッチングと、引続き該窒化シリコン膜の
エッチングを行なって上記コンタクトホールを生成する
ことを特徴とする半導体装置の製造方法。A silicon oxide film or a polysilicon film is formed on the surface of a silicon nitride film on a substrate, and a resist film is patterned on the silicon oxide film or polysilicon film to open a portion where a contact hole is to be formed, and from the opening portion. A method of manufacturing a semiconductor device, characterized in that the contact hole is created by etching the silicon oxide or polysilicon film and subsequently etching the silicon nitride film by a reactive ion etching method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13491484A JPS6113627A (en) | 1984-06-28 | 1984-06-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13491484A JPS6113627A (en) | 1984-06-28 | 1984-06-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6113627A true JPS6113627A (en) | 1986-01-21 |
Family
ID=15139482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13491484A Pending JPS6113627A (en) | 1984-06-28 | 1984-06-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6113627A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6324622A (en) * | 1986-07-16 | 1988-02-02 | Nec Corp | Semiconductor device |
| JPH01280317A (en) * | 1988-05-06 | 1989-11-10 | Matsushita Electric Ind Co Ltd | Dry etching |
| JPH09129732A (en) * | 1995-10-31 | 1997-05-16 | Nec Corp | Semiconductor device manufacturing method |
| JP2006253222A (en) * | 2005-03-08 | 2006-09-21 | Tokyo Electron Ltd | Method and apparatus for etching |
-
1984
- 1984-06-28 JP JP13491484A patent/JPS6113627A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6324622A (en) * | 1986-07-16 | 1988-02-02 | Nec Corp | Semiconductor device |
| JPH01280317A (en) * | 1988-05-06 | 1989-11-10 | Matsushita Electric Ind Co Ltd | Dry etching |
| JPH09129732A (en) * | 1995-10-31 | 1997-05-16 | Nec Corp | Semiconductor device manufacturing method |
| JP2006253222A (en) * | 2005-03-08 | 2006-09-21 | Tokyo Electron Ltd | Method and apparatus for etching |
| JP4541193B2 (en) * | 2005-03-08 | 2010-09-08 | 東京エレクトロン株式会社 | Etching method |
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