KR100248142B1 - Method of fabricating semiconductor device - Google Patents
Method of fabricating semiconductor device Download PDFInfo
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- KR100248142B1 KR100248142B1 KR1019960068901A KR19960068901A KR100248142B1 KR 100248142 B1 KR100248142 B1 KR 100248142B1 KR 1019960068901 A KR1019960068901 A KR 1019960068901A KR 19960068901 A KR19960068901 A KR 19960068901A KR 100248142 B1 KR100248142 B1 KR 100248142B1
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- oxide film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
본 발명은 반도체소자 제조방법에 관한것으로, 특히 자기 정렬(Self Aligned) 콘택을 형성할 때 콘택 지역에 형성되는 산화막 계통의 절연막에 대한 식각선택비가 높은 막으로 티타늄 산화막(TiO2)을 이용하는 것이다. 상기 티타늄 산화막은 산화막을 식각할때 이용되는 여러가지 식각 소오스에 대하여 식각선택비가 높고, 폴리머가 생성되지 않으므로 식각장비가 오염되는 문제가 발생되지 않는다. 그결과 식각 공징에 대한 재현성이 향상되고, 식각 공정의 마진이 높아 용이하게 공정을 진행할 수가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device. In particular, a titanium oxide film (TiO2) is used as a film having a high etching selectivity for an insulating film of an oxide film formed in a contact region when forming a self aligned contact. The titanium oxide film has a high etching selectivity with respect to various etching sources used to etch the oxide film, and since the polymer is not produced, the etching equipment is not contaminated. As a result, the reproducibility of the etching cavities is improved, and the etching process has a high margin, so that the process can be easily performed.
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 자기 정렬(Self Aligned) 콘택의 식각베리어막으로 콘택 지역에 형성되는 다른층과 높은 식각선택비를 갖는 막으로 형성하는 반도체소자의 콘택홀 형성방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device, which is formed by a film having a high etching selectivity with another layer formed in a contact region as an etching barrier film of a self aligned contact. It's about.
반도체소자가 고집적화됨에 따라 미세한 콘택홀이 필요로 하게 된다. 이러한 미세한 콘택흘은 깊이가 더 크져서 콘택홀의 종횡비를 의미하는 에스펙트 비(Aspect Ratio)가 증대된다. 그로 인해 미세한 콘택홀의 제조가 까다롭다.As semiconductor devices are highly integrated, fine contact holes are required. Such fine contact flows have a larger depth, thereby increasing an aspect ratio, which means an aspect ratio of a contact hole. This makes it difficult to manufacture fine contact holes.
이러한 문제점을 해소하기 위해 자기 정렬 콘택홀 형성 방법이 대두되었는데 콘택 영역에 식각베리어막으로 질화막을 증착하고, 그 상부에 절연막으로 산화막을 형성한다. 그로 인해 상기 질화막 상부에 두껍게 증착된 산화막을 식각할때 상기 질화막이 식각베리어로 작용하게 되는데 식각선택비가 20-30:1 정도이다. 이것은 산화막을 식각할때 노출되는 질화막의 표면에 폴리머가 남게되어 식각선택비가 증대하는 것으로 알려지고 있다. 한편, 상기 폴리머는 식각선택비를 증대시키는 작용을 하는 동시에 식각 장비의 챔버를 오염시키는 오염원으로 작용하여 후속 공정으로 다른 웨이퍼에서 식각공정을 진행할 때 장애 요소로 작용되며, 그로 인해 공정의 재현성이 저하되는 문제가 있다.In order to solve this problem, a method of forming a self-aligned contact hole has emerged. A nitride film is deposited on the contact region using an etch barrier film, and an oxide film is formed on the upper portion of the insulating film. Therefore, when the oxide layer thickly deposited on the nitride layer is etched, the nitride layer acts as an etch barrier, with an etching selectivity of about 20-30: 1. This is known to increase the etching selectivity by leaving a polymer on the surface of the nitride film exposed when etching the oxide film. On the other hand, the polymer acts to increase the etch selectivity and at the same time act as a contaminant that contaminates the chamber of the etching equipment, thereby acting as an obstacle when the etching process is performed on another wafer as a subsequent process, thereby reducing the reproducibility of the process. There is a problem.
또한, 콘택 영역의 산화막을 제거할 때 식각 소오스의 유량의 작은 변동에도 질화막과 산화막의 식각선택비가 심하게 차이가 나게 되어 공정마진이 너무 작다는 문제점이 있다. 예를들어 C4F8을 식각 소오스로 이용하는 경우 20 SCCM 일때 식각선택비가 10이 되고, 19 SCCM 일때는 식각선택비가 10으로 저하되고, 21 SCCM 일때는 질화막 상부에 있는 산화막이 완전히 제거되지 않는 문제가 발생된다.In addition, when removing the oxide layer in the contact region, the etching selectivity of the nitride layer and the oxide layer is severely different even with a small fluctuation in the flow rate of the etching source, resulting in a process margin that is too small. For example, when C 4 F 8 is used as an etching source, the etching selectivity is 10 at 20 SCCM, the etching selectivity is reduced to 10 at 19 SCCM, and the oxide layer on the upper part of the nitride film is not completely removed at 21 SCCM. Is generated.
그리고, 콘택 영역이 평탄한 경우와 단차를 갖는 경우에 서로 식각조건이 달라지고, 또한, 에스펙트 비에 따라 식각 조건이 달라져야 하는등 실제 생산에는 적용하기가 부적당하다.In addition, when the contact area is flat and when the step has a step, the etching conditions are different from each other, and the etching conditions must be changed according to the aspect ratio, which is not suitable for actual production.
본 발명은 상기와 같이 자기 정렬 콘택에서 산화막에 대한 식각베리어막으로 질화막을 이용할 때 발생되는 문제점을 해결하기 위하여 산화막에 대한 식각선택비가 높은 막을 이용하여 콘택홀을 형성하는 방법을 제공하는데 그 목적이 있다.The present invention provides a method for forming a contact hole using a film having a high etching selectivity for the oxide film to solve the problems caused when using the nitride film as an etching barrier film for the oxide film in the self-aligned contact as described above. have.
도 1 내지 도 3은 본 발명의 실시예에 의해 하부 도전배선 사이의 반도체기판이 노출되는 콘택홀을 형성하는 공정을 도시한 단면도.1 to 3 are cross-sectional views illustrating a process of forming contact holes in which semiconductor substrates between lower conductive wirings are exposed according to an exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : 도전배선1: semiconductor substrate 2: conductive wiring
3 : 마스크 절연막 4 : 스페이서 절연막3: mask insulating film 4: spacer insulating film
5 : 얇은 절연막 6 : 티타늄 산화막5: thin insulating film 6: titanium oxide film
7 : 평탄화용 절연막 8 : 감광막 패턴7: insulating film for planarization 8: photosensitive film pattern
10 : 콘택홀10: contact hole
상기한 목적을 달성하기 위한 본 발명은 반도체소자 제조방법에 있어서, 반도체기판 상부에 하부 도전배선을 형성하는 공정과, 전체적으로 노출된 표면에 얇은 절연막을 형성하는 공정과, 상기 절연막 상부에 식각베리어막으로 사용되는 티타늄 산화막을 형성하는 공정과, 상기 티타늄 산화막 상부에 평탄화용 절연막을 형성하는 공정과, 콘택 마스크를 이용한 식각 공정으로 상기 평탄화용 절연막을 식각하는 공정과, 상기 공정으로 노출된 티타늄 산화막을 식각하는 공정과, 상기 공정으로 노출된 얇은 절연막을 식각하여 콘택 영역이 오픈된 콘택홀을 형성하는 공정을 포함한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: forming a lower conductive wiring on an upper surface of a semiconductor substrate; forming a thin insulating film on an exposed surface; and an etching barrier layer on the insulating film. Forming a titanium oxide film to be used, forming a planarization insulating film on the titanium oxide film, etching the planarizing insulating film by an etching process using a contact mask, and exposing the titanium oxide film exposed by the process. And etching the thin insulating film exposed by the process to form a contact hole with an open contact region.
본 발명은 산화막 계통의 절연막에 대한 식각선택비가 높은 막으로 티타늄 산화막(TiO2)을 이용하는 것이다. 상기 티타늄 산화막은 산화막을 식각할때 이용되는 여러가지 식각 소오스에 대하여 식각선택비가 높고, 또한, 폴리머가 생성되지 않으므로 식각장비가 오염되는 문제가 발생되지 않는다. 그결과 식각 공정에 대한 재현성이 향상되고, 식각 공정의 마진이 높아 용이하게 공정을 진행할 수가 있다.The present invention uses a titanium oxide film (TiO 2 ) as a film having a high etching selectivity with respect to an insulating film of an oxide film system. The titanium oxide film has a high etching selectivity with respect to various etching sources used to etch the oxide film, and since the polymer is not generated, the etching equipment is not contaminated. As a result, the reproducibility of the etching process is improved, and the etching process has a high margin so that the process can be easily performed.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 3은 본 발명의 실시예에 의해 반도체기판 상부에 형성된 워드라인 사이에 상부 도전층을 콘택하기 위해 콘택홀을 형성하는 단계를 도시한 단면도이다.1 to 3 are cross-sectional views illustrating a step of forming a contact hole to contact an upper conductive layer between word lines formed on an upper surface of a semiconductor substrate according to an exemplary embodiment of the present invention.
도 1은 반도체기판(1) 상부에 하부 도전배선(2)으로 예를들어 워드라인을 형성하고, 그 상부에 얇은 절연막(5)으로 산화막을 형성하고, 그상부에 상부에 평탄화용 절연막에 대한 식각베리어막으로 이용되는 티타늄 산화막(6)을 적층한 것을 도시한 단면도이다.1 shows a word line, for example, with a lower conductive wiring 2 on top of a semiconductor substrate 1, an oxide film with a thin insulating film 5 thereon, and an insulating film for planarization thereon. It is sectional drawing which shows the lamination | stacking of the titanium oxide film 6 used as an etching barrier film.
참고로, 상기 티타늄 산화막(6)의 증착은 티타늄을 예를들어 5-1.5KWatt의 전력에서 챔버온도는 200-400℃정도에서 스퍼터링 증착하면서 산소를 500-1500 SCCM(Standard Cubic Centimeter)으로 유입시킨다.For reference, the deposition of the titanium oxide film 6 causes oxygen to flow into 500-1500 SCCM (Standard Cubic Centimeter) while sputtering deposition of titanium, for example, at a temperature of 200-400 ° C. at a power of 5-1.5KWatt. .
그리고, 상기 도전배선(2)의 상부에 마스크 절연막(3)이 구비되고, 상기 도전배선(2)의 측벽에는 스페이서 절연막(4)을 구비한 것을 도시한다.The mask insulating film 3 is provided on the conductive wiring 2, and the spacer insulating film 4 is provided on the sidewall of the conductive wiring 2.
도 2는 상기 티타늄 산화막(6) 상부에 평탄화용 절연막(7)으로 예를들어 BPSG(Boro Phospho Silicate Glass)막 또는 USG (Undoped Silica Glass)막을 적층한다음, 그 상부에 콘택 마스크용 감광막 패턴(8)을 형성한 단면도이다.2 is a BPSG (Boro Phospho Silicate Glass) film or USG (Undoped Silica Glass) film laminated on the titanium oxide film 6 as a planarization insulating film 7 above, and then a photoresist pattern for contact mask ( It is sectional drawing which formed 8).
참고로, 상기 콘택 마스크용 감광막 패턴(8) 형성시 미스얼라인이 발생되어 정확하게 하부 도전배선(2) 사이의 콘택영역에 오버랩되지 않고 약간 시프트되어 구비됨을 알수 있다.For reference, when the photoresist pattern 8 for the contact mask is formed, a misalignment is generated, and it is understood that the contact mask is shifted slightly without overlapping the contact region between the lower conductive lines 2.
도 3은 상기 감광막 패턴(8)을 마스크로 이용하여 상기 평탄화용 절연막(7)을 식각하고, 노출된 티타늄 산화막(6)을 식각한다음, 노출되는 얇은 산화막(6)을 식각하여 콘택영역이 오픈된 콘택홀(10)을 형성한 것을 도시한 것으로, 상기 콘택홀(10)이 우측으로 시프트되어 있으나, 상기 티타늄 산화막(6)이 식각베리어막으로 작용하여 상기 평탄화용 절연막(7)을 식각할때 하부의 도전배선(2)이 노출되는 것을 방지한다.3 shows that the planarization insulating film 7 is etched using the photoresist pattern 8 as a mask, the exposed titanium oxide film 6 is etched, and then the exposed thin oxide film 6 is etched to form a contact region. The open contact hole 10 is formed. The contact hole 10 is shifted to the right, but the titanium oxide film 6 acts as an etch barrier film to etch the planarization insulating film 7. When the lower conductive wiring (2) is prevented from being exposed.
참고로, 상기 평탄화용 절연막(7)을 식각할때 C와 F를 포함하는 개스 예를들어 CF4, CH3F, C2F6, C3F8, C4F8, CH2F2중에 하나 또는 두개이상의 혼합 개스를 이용하며, 식각 장비의 소오스 전력은 1000-3000Watt, 압력은 1-50mTorr, 척 온도는 -30 에서 50℃ 정도이다. 이러한 조건으로 평탄화용 절연막(7)을 식각하면 티타늄 산화막(6)과의 식각선택비가 40-300:1 정도가 된다.For reference, when etching the planarization insulating film 7, a gas including C and F, for example, CF 4 , CH 3 F, C 2 F 6 , C 3 F 8 , C 4 F 8 , CH 2 F 2 Either one or two or more mixed gases are used, the source power of the etching equipment is 1000-3000Watt, the pressure is 1-50mTorr, the chuck temperature is -30 to 50 ℃. When the planarization insulating film 7 is etched under such conditions, the etching selectivity with the titanium oxide film 6 is about 40-300: 1.
또한, 티타늄 산화막(6)은 CF4, Cl2, SF6의 개스의 하나 또는 혼합개스에서 식각이 가능하다.In addition, the titanium oxide film 6 can be etched in one or a mixture of gases of CF 4 , Cl 2 , SF 6 .
여기서, 상기 평탄화용 절연막(7)과 상기 티타늄 산화막(6)과의 식각선택비가 크기 때문에 상기 평탄화용 절연막(7)에 대해서 상기 티타늄 산화막(6)이 식각베리어막으로 적당하고, 이때 폴리머가 발생되지 않기 때문에 식각 챔버를 오염시키는 문제등이 발생되지 않게 된다. 또한, 티타늄산화막(6)은 CF4, Cl2, SF6의 개스에서 용이하게 제거되며, 식각 공정마진이 넓다.Here, since the etching selectivity between the planarization insulating film 7 and the titanium oxide film 6 is large, the titanium oxide film 6 is suitable as an etching barrier film with respect to the planarization insulating film 7, and a polymer is generated. Therefore, the problem of contaminating the etching chamber does not occur. In addition, the titanium oxide film 6 is easily removed from the gas of CF 4 , Cl 2 , SF 6 , the etching process margin is wide.
그리고, 후속 공정으로 상기 콘택홀에 상부 도전 배선을 채워서 상기 반도체 기판에 콘택되는 반도체소자를 제조한다.Subsequently, a semiconductor device contacted to the semiconductor substrate is manufactured by filling an upper conductive wiring in the contact hole.
상기한바와같이 본 발명에서 티타늄 산화막을 자기 정렬 콘택에서 식각베리어막으로 이용하는 경우 실리콘 산화막계통의 절연막과의 높은 식각선택비를 용이하게 얻을 수 있어 초 미세 크기의 콘택홀을 형성 할수있다. 그리고, 티타늄 산화막에 대한 높은 식각선택비와 함께 넓은 공정마진을 확보 할수 있으므로 마이크로 로딩 효과를 최소화 하고, 에스펙트비에 따른 식각베리어막에 식각선택비 변화를 줄일수 있다. 따라서, 한가지 식각조건으로 콘택홀의 크기나 에스펙트 비에 관계없이 콘택 식각을 진행할수가 있으므로 장비 운용이나 프로세스 적용성에서 월등한 장점을 질화막 자기 정렬 콘택에 비교하여 얻을수 있다. 따라서, 소자의 적용도 용이하고, 소자 개발도 앞당길 수 있다.As described above, when the titanium oxide film is used as the etching barrier film in the self-aligned contact, it is possible to easily obtain a high etching selectivity with the insulating film of the silicon oxide film system, thereby forming a very fine contact hole. In addition, it is possible to secure a wide process margin along with a high etching selectivity for the titanium oxide film, thereby minimizing the micro loading effect and reducing the etching selectivity change in the etching barrier film according to the aspect ratio. Therefore, the contact etching can be performed regardless of the size of the contact hole or the aspect ratio with one etching condition, and thus, the superior advantages in equipment operation or process applicability can be obtained by comparing with the nitride self-aligned contact. Therefore, the device can be easily applied and the device development can be accelerated.
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