KR20000008838A - Method for forming contact hole in semiconductor devices - Google Patents
Method for forming contact hole in semiconductor devices Download PDFInfo
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- KR20000008838A KR20000008838A KR1019980028866A KR19980028866A KR20000008838A KR 20000008838 A KR20000008838 A KR 20000008838A KR 1019980028866 A KR1019980028866 A KR 1019980028866A KR 19980028866 A KR19980028866 A KR 19980028866A KR 20000008838 A KR20000008838 A KR 20000008838A
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- contact hole
- etching
- insulating film
- groove
- forming
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229920000642 polymer Polymers 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 26
- 125000006850 spacer group Chemical group 0.000 claims abstract description 19
- 239000007789 gas Substances 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 239000011737 fluorine Substances 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 3
- 239000011229 interlayer Substances 0.000 description 13
- 239000010410 layer Substances 0.000 description 10
- 230000010354 integration Effects 0.000 description 2
- 229910019044 CoSix Inorganic materials 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 장치에 관한 것으로, 특히 반도체 장치의 콘택홀 형성방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly to a method for forming a contact hole in a semiconductor device.
반도체 장치의 집적도가 점차 증가됨에 따라, 반도체 셀을 구성하는 여러 가지 패턴들 뿐 아니라 배선의 넓이(width) 및 배선과 홈사이의 간격(space)에 있어서도 급격한 고집적화를 보이고 있다. 그러나 이처럼 고집적화되어 가는 반도체 장치에 있어 특히, 고립되어 있는 소자 영역들을 전기적으로 연결하기 위한 콘택은, 얼라인 마진(align margin), 소자분리 마진(isolation margin) 등을 고려하여 형성되어야 하기 때문에 소자의 구성에 있어서 상당한 면적을 차지하게 된다. 따라서, 반도체 장치의 콘택을 형성함에 있어서는, 얼라인 마진의 부족으로 인해 상부와 하부간의 물질막이 완전히 분리되어지지 않는 문제가 유발된다.As the degree of integration of a semiconductor device is gradually increased, not only various patterns constituting the semiconductor cell but also rapid high integration are shown in the width of the wiring and the space between the wiring and the groove. However, in such highly integrated semiconductor devices, the contact for electrically connecting the isolated device regions must be formed in consideration of an alignment margin, an isolation margin, and the like. It takes up a considerable area in construction. Therefore, in forming the contact of the semiconductor device, the problem that the material film between the top and the bottom is not completely separated due to the lack of the alignment margin.
따라서 본 분야에서는 이러한 얼라인 마진을 증가시키기 위해, CF4또는 CHF3가스를 이용한 경사식각 방법을 사용하였다. 상기 CF4또는 CHF3와 같은 가스들은 하부 막질에 대한 고 선택비를 갖지는 않지만 CFx 폴리머를 감광막 측벽에 형성시키며 식각이 진행되기 때문에 경사 식각이 가능해진다.Therefore, in order to increase the alignment margin in the art, a gradient etching method using CF 4 or CHF 3 gas was used. Gases such as CF 4 or CHF 3 do not have a high selectivity to the underlying film quality, but because of the formation of the CFx polymer on the photoresist sidewalls and the etching proceeds, oblique etching is possible.
그러나 점차 고 스피드의 제품이 요구되어 낮은 저항을 갖는 수백 Å의 TiSix 또는 CoSix등의 물질이 액티브 영역, 게이트 폴리 및 비트라인등에 적용되면서 식각시 상기 TiSix 또는 CoSix의 손실을 방지하기 위하여 하부도전막에 대해 고 선택비를 갖는 식각공정이 요구되고 있다. 이러한 고 선택적 식각을 위해서는 탄소(C)와 불소(F)의 비율이 큰 C4F8또는 C2F6등의 가스를 사용하여 하부도전막이 드러났을 때, 표면에 탄소 리치(rich) 폴리머(polymer)를 형성시켜 더 이상의 식각이 진행되는 것을 방해하여야 한다. 그러나, 상기 C4F8또는 C2F6가스와 같이 탄소와 불소의 비율이 큰 가스들은 감광막의 측벽에 CFx 폴리머를 거의 형성시키지 않아 경사 식각이 불가능해져 수직의 프로파일을 갖는 콘택이 형성된다. 이러한 수직의 프로파일을 갖는 콘택은 하부도전막에 대한 얼라인 마진을 감소시키는 문제를 발생시키며, 측벽에 폴리머가 형성되지 않으므로 식각시 감광막의 측벽 손실이 커지게 된다. 그러므로 식각이 진행될수록 감광막의 손실이 증가하게 되어 콘택홀의 상부의 임계치수(Critical Dimension)가 증가되는 문제점을 초래하게 된다.However, as high speed products are required, hundreds of microseconds of TiSix or CoSix with low resistance are applied to the active region, gate poly and bit line, and the lower conductive film is prevented from being lost during etching. There is a demand for an etching process having a high selectivity. For this highly selective etching, when the lower conductive film is exposed using a gas such as C 4 F 8 or C 2 F 6 having a large ratio of carbon (C) and fluorine (F), a carbon rich polymer ( Polymers should be formed to prevent further etching. However, gases having a large ratio of carbon and fluorine, such as C 4 F 8 or C 2 F 6 gas, hardly form CFx polymer on the sidewall of the photoresist film, thus making it impossible to incline etching, thereby forming a contact having a vertical profile. The contact having such a vertical profile causes a problem of reducing the alignment margin for the lower conductive film, and since the polymer is not formed on the sidewall, the sidewall loss of the photoresist film increases during etching. Therefore, as the etching proceeds, the loss of the photoresist film increases, which causes a problem of increasing the critical dimension of the upper portion of the contact hole.
따라서 본 발명의 목적은, 상기 종래의 문제점을 해소할 수 있는 콘택홀 형성방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for forming a contact hole that can solve the conventional problem.
본 발명의 다른 목적은, 콘택홀의 프로파일을 변화시키지 않는 콘택홀 형성방법을 제공함에 있다.Another object of the present invention is to provide a method for forming a contact hole that does not change the profile of the contact hole.
본 발명의 또 다른 목적은, 하부 배선과 충분한 얼라인 마진을 가지는 콘택홀 형성방법을 제공함에 있다.Another object of the present invention is to provide a method for forming a contact hole having a lower wiring and sufficient alignment margin.
상기의 목적들을 달성하기 위해서 본 발명은, 반도체 기판 상부의 절연막에 콘택홀을 형성하는 방법에 있어서: 절연막 상부에 감광막을 형성한 뒤, 이를 부분적으로 현상하여 상기 절연막을 식각하기 위한 마스크로서 패터닝하는 단계와; 상기 패터닝된 감광막을 통해 노출된 절연막을 하부로 부분 식각하여 홈을 형성함과 동시에 상기 패터닝된 감광막 측벽에서 상기 홈의 측벽으로 이어지는 폴리머 스페이서를 형성하는 단계와; 상기 폴리머 스페이서가 형성되어 있는 홈을 통해 노출된 절연막을 수직 식각하여 완전히 제거하는 단계를 포함함을 특징으로 하는 방법을 제공한다.SUMMARY OF THE INVENTION In order to achieve the above objects, the present invention provides a method for forming a contact hole in an insulating film on a semiconductor substrate: forming a photoresist film on the insulating film, and then partially developing the patterned film as a mask for etching the insulating film. Steps; Partially etching the insulating film exposed through the patterned photoresist downward to form a groove, and simultaneously forming a polymer spacer extending from the sidewall of the patterned photoresist to the sidewall of the groove; And vertically etching the insulating film exposed through the groove in which the polymer spacer is formed to completely remove the insulating film.
이때, 상기 홈 및 폴리머 스페이서는 CF4와 CO 혼합가스를 이용한 건식식각 공정을 통해 형성하는 것이 바람직하다.At this time, the groove and the polymer spacer is preferably formed through a dry etching process using a mixture of CF 4 and CO.
또한, 상기 홈을 통해 노출된 절연막은 C4F8과 같이 탄소와 불소의 비율이 큰 가스에 아르곤 및 산소가 첨가되어 있는 혼합가스를 이용하여 수직 식각하는 것이 바람직하다.In addition, the insulating film exposed through the groove is preferably vertically etched using a mixed gas in which argon and oxygen are added to a gas having a large ratio of carbon and fluorine, such as C 4 F 8 .
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 장치의 콘택홀 형성방법을 설명하기 위한 단면도들1A to 1C are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to an embodiment of the present invention.
이하, 본 발명의 바람직한 실시예들을 첨부한 도면을 참조하여 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 장치의 콘택홀 형성방법을 설명하기 위한 단면도들이다.1A to 1C are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.
먼저 도 1a를 참조하면, 하부도전막 102이 형성되어 있는 반도체 기판 100에 산화막 또는 질화막을 이용하여 층간절연막 104을 형성한다. 이어서, 상기 층간절연막 104 상부에 감광막(도시하지 않음)을 형성한 뒤, 패터닝하여 상기 층간절연막 104을 식각하기 위한 마스크층 106을 형성한다.First, referring to FIG. 1A, an interlayer insulating film 104 is formed on the semiconductor substrate 100 on which the lower conductive film 102 is formed by using an oxide film or a nitride film. Subsequently, a photoresist film (not shown) is formed on the interlayer insulating film 104, and then patterned to form a mask layer 106 for etching the interlayer insulating film 104.
도 1b를 참조하면, 상기 마스크층 106을 이용하여 상기 층간절연막 104을 소정 깊이로 제1건식식각하여 홈 108을 형성한다. 이때, 상기 홈 108은 층간절연막 104의 약 절반에 이르는 깊이로 형성하는 것이 바람직하다. 그리고 상기 제1건식식각은 상기 층간절연막 104이 식각됨과 동시에 CFx 폴리머가 상기 감광막으로 이루어진 마스크층 106과 홈 108의 측벽에 부착될 수 있는 조건에서 실시하는 것이 바람직하다. 이때, 상기 CFx 폴리머의 x는 임의의 자연수를 가짐을 의미하며, 상기 CFx 폴리머를 형성하기 위한 상기 제1건식식각은 MERIE 타입의 식각장비내에서 CF4와 CO 혼합가스를 이용하여 실시하는 것이 바람직하다. 상기와 같은 제1건식식각을 실시하게 되면 상기 CF4와 CO 혼합가스에서 플라즈마가 발생되어, 도면에 도시되어 있는 바와 같이 상기 마스크층 106과 홈 108의 측벽에 폴리머 스페이서 110가 형성된다. 이러한 폴리머 스페이서 110는 후속의 잔여 층간절연막 104 식각공정시, 마스크층으로서 기능하게 되어 경사진 프로파일을 갖는 콘택홀을 형성할 수 있게 된다.Referring to FIG. 1B, the interlayer insulating layer 104 is first dry-etched to a predetermined depth using the mask layer 106 to form a groove 108. At this time, the groove 108 is preferably formed to a depth of about half of the interlayer insulating film 104. The first dry etching may be performed under the condition that the interlayer insulating film 104 is etched and the CFx polymer is attached to the sidewalls of the mask layer 106 and the groove 108 formed of the photosensitive film. In this case, x of the CFx polymer means that it has an arbitrary natural number, and the first dry etching for forming the CFx polymer is preferably performed using a mixture of CF 4 and CO in an MERIE type etching equipment. Do. When the first dry etching is performed, plasma is generated in the CF 4 and CO mixed gas, and the polymer spacer 110 is formed on sidewalls of the mask layer 106 and the groove 108 as shown in the drawing. The polymer spacer 110 may function as a mask layer during the subsequent remaining interlayer insulating layer 104 etching process to form a contact hole having an inclined profile.
도 1c를 참조하면, 상기 폴리머 스페이서 110가 형성되어 있는 홈 108을 통해 노출되어 있는 층간절연막 104에 제2건식식각 공정을 실시한다. 이때, 상기 제2건식식각은 하부도전막 102과 층간절연막 104과의 식각선택비가 우수한 에천트를 이용하는 것이 바람직하며, 이러한 에천트로서는 탄소와 불소의 비율이 높은 C4F8가스에 아르곤(Ar) 및 산소(O2)를 첨가한 혼합가스가 적당하다. 상기와 같은 조건을 만족하는 제2식각공정을 실시한 결과, 상기 층간절연막 104의 소정영역에는 하부도전막 102의 표면에 이르는 콘택홀 112가 형성된다.Referring to FIG. 1C, a second dry etching process may be performed on the interlayer insulating layer 104 exposed through the groove 108 in which the polymer spacer 110 is formed. In this case, the second dry etching may use an etchant having an excellent etching selectivity between the lower conductive film 102 and the interlayer insulating film 104. The etchant may include argon (Ar) in a C 4 F 8 gas having a high ratio of carbon and fluorine. ) And a mixed gas to which oxygen (O 2 ) is added are suitable. As a result of performing the second etching process that satisfies the above conditions, a contact hole 112 reaching the surface of the lower conductive film 102 is formed in a predetermined region of the interlayer insulating film 104.
이때, 상술한 바와 같이 콘택홀 112 형성을 위한 건식식각 공정시에 상기 폴리머 스페이서 110가 마스크층으로 기능하여 상기 콘택홀 112의 상부는 경사진 프로파일을 가지게 되어 후속의 공정을 통해 형성되어질 상부도전막에 대한 오버랩 마진을 확보할 수 있게 된다. 또한 상기 폴리머 스페이서 110로 인해, 상기 제2건식식각시에 마스크층 106의 손실이 방지되어 콘택홀 112의 면적이 최초 설정된 면적보다 증가되는 문제점을 효과적으로 해소할 수 있게 된다. 보다 구체적으로 언급하면, 종래에서와 같이 한번의 식각공정으로 수직의 프로파일을 갖는 콘택홀을 형성하였을 경우에 비하여 본 발명에서와 같이 층간절연막을 소정 영역 식각하여 폴리머 스페이서를 미리 형성한 뒤, 콘택홀을 형성하게 되면, 최종적으로 형성된 콘택홀 상부의 임계치수는 약 80㎚가 감소되며, 하부의 임계치수 또한 약 170㎚감소되는 결과를 가져온다. 그러므로 본 발명에 따른 콘택홀 형성방법은 점차 고집적화되어가는 반도체 장치에 매우 적합한 기술임을 알 수 있다.In this case, as described above, the polymer spacer 110 functions as a mask layer during the dry etching process for forming the contact hole 112 so that the upper portion of the contact hole 112 has an inclined profile and is formed through a subsequent process. It is possible to secure an overlap margin for. In addition, due to the polymer spacer 110, the loss of the mask layer 106 during the second dry etching is prevented to effectively solve the problem that the area of the contact hole 112 is increased than the initially set area. More specifically, compared to the case where a contact hole having a vertical profile is formed in one etching process as in the related art, after forming the polymer spacer by etching the predetermined region as the interlayer insulating film as in the present invention, the contact hole is formed in advance. When forming the, the critical dimension at the top of the finally formed contact hole is reduced by about 80 nm, and the lower critical dimension is also reduced by about 170 nm. Therefore, it can be seen that the method for forming a contact hole according to the present invention is a very suitable technique for a semiconductor device which is becoming increasingly integrated.
상기한 바와 같이 본 발명에서는 반도체 장치의 콘택홀을 형성함에 있어서, 층간절연막을 소정 깊이로 식각하여 홈을 형성한 뒤, 상기 홈의 측벽에 폴리머 스페이서를 형성시킨다. 그리고 나서, 상기 폴리머 스페이서가 형성되어 있는 홈을 통해 노출되어 있는 상기 층간절연막을 식각하여 하부도전막에 이르는 콘택홀을 완성한다. 이때 상기 폴리머 스페이서로 인하여, 콘택홀의 상부는 임계치수의 변화없이 경사진 프로파일을 가지게 되며, 이러한 경사진 프로파일로 인해 상부도전막과의 오버랩 마진을 충분히 가질 수 있게 된다. 그리고 폴리머 스페이서가 형성되어 있는 홈을 통해 콘택홀을 완성하게 되므로 콘택홀의 하부 임계치수 또한 증가되지 않아 하도전막과 충분한 얼라인 마진을 가지게 되는 효과가 있다.As described above, in forming the contact hole of the semiconductor device, a groove is formed by etching the interlayer insulating film to a predetermined depth, and then a polymer spacer is formed on the sidewall of the groove. Then, the interlayer insulating film exposed through the groove in which the polymer spacer is formed is etched to complete the contact hole reaching the lower conductive film. At this time, due to the polymer spacer, the upper portion of the contact hole has an inclined profile without changing the critical dimension, it is possible to have a sufficient overlap margin with the upper conductive film due to this inclined profile. In addition, since the contact hole is completed through the groove in which the polymer spacer is formed, the lower critical dimension of the contact hole also does not increase, thereby having an effect of having sufficient alignment margin with the conductive film.
상술한 바와 같이 본 발명의 바람직한 실시예를 참조하여 설명하였지만 하기의 특허 청구 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위내에서 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although described with reference to the preferred embodiment of the present invention as described above, it will be understood that various modifications and changes can be made without departing from the spirit and scope of the present invention as set forth in the claims below.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980028866A KR20000008838A (en) | 1998-07-16 | 1998-07-16 | Method for forming contact hole in semiconductor devices |
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| KR1019980028866A KR20000008838A (en) | 1998-07-16 | 1998-07-16 | Method for forming contact hole in semiconductor devices |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030002364A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Method for manufacturing contact hole of semiconductor device |
| KR100796180B1 (en) * | 2006-10-27 | 2008-01-21 | 피에스케이 주식회사 | Method for forming semiconductor device |
| KR100959453B1 (en) * | 2007-12-27 | 2010-05-25 | 주식회사 동부하이텍 | Method for fabricating semiconductor device |
-
1998
- 1998-07-16 KR KR1019980028866A patent/KR20000008838A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030002364A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Method for manufacturing contact hole of semiconductor device |
| KR100796180B1 (en) * | 2006-10-27 | 2008-01-21 | 피에스케이 주식회사 | Method for forming semiconductor device |
| KR100959453B1 (en) * | 2007-12-27 | 2010-05-25 | 주식회사 동부하이텍 | Method for fabricating semiconductor device |
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