KR20050066369A - Method of forming a contact hole in a semiconductor device - Google Patents
Method of forming a contact hole in a semiconductor device Download PDFInfo
- Publication number
- KR20050066369A KR20050066369A KR1020030097645A KR20030097645A KR20050066369A KR 20050066369 A KR20050066369 A KR 20050066369A KR 1020030097645 A KR1020030097645 A KR 1020030097645A KR 20030097645 A KR20030097645 A KR 20030097645A KR 20050066369 A KR20050066369 A KR 20050066369A
- Authority
- KR
- South Korea
- Prior art keywords
- contact hole
- insulating film
- forming
- spacer
- interlayer insulating
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 절연막에 콘택홀을 형성하고 절연막과 선택비가 상이한 물질로 콘택홀의 측벽에 스페이서를 형성하여 후속의 식각 공정이나 세정 공정 시 콘택홀 측벽의 절연막이 식각되는 것을 방지함으로써, 콘택홀 사이에 절연막을 좁은 폭으로 잔류시켜도 절연막으로써의 역할을 정상적으로 수행할 수 있어 공정의 신뢰성을 향상시키고, 이를 통해 콘택 플러그의 면적을 증가시킬 수 있어 소자의 전기적 특성을 향상시킬 수 있다. The present invention relates to a method for forming a contact hole in a semiconductor device, wherein a contact hole is formed in an insulating film and a spacer is formed on the sidewall of the contact hole with a material having a different selectivity from the insulating film. By preventing the etching, even if the insulating film is left between the contact holes in a narrow width, it can function normally as the insulating film, thereby improving the reliability of the process, thereby increasing the area of the contact plug, thereby improving the electrical characteristics of the device. Can be improved.
Description
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 특히 식각 공정 시 절연막의 측벽 손실을 방지할 수 있는 반도체 소자의 콘택홀 형성 방법에 관한 것이다. The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device capable of preventing sidewall loss of an insulating layer during an etching process.
일반적으로, 하부의 접합 영역을 상부의 금속 배선과 연결하거나 접합 영역에 바이어스를 인가하기 위하여, 접합 영역 상부에는 콘택 플러그나 비아 플러그를 형성한다. In general, contact plugs or via plugs are formed on the junction areas in order to connect the bottom junction areas with the upper metal lines or to apply a bias to the junction areas.
이러한 콘택 플러그는 소자의 집적도가 높아짐에 따라 사이즈가 감소하기 때문에, 콘택 저항이 높아져 소자의 동작 속도와 신뢰성이 저하되는 원인이 된다. 이를 해결하기 위하여 콘택플러그의 면적을 증가시켜야 하는데, 소자의 집적도가 높아지면 콘택 플러그와의 간격도 좁아진다. 콘택 플러그의 간격이 좁아지면 콘택 플러그 사이에 잔류하는 절연막의 폭이 좁아진다. Since the size of the contact plug decreases as the degree of integration of the device increases, the contact resistance increases, which causes a decrease in operating speed and reliability of the device. In order to solve this problem, the area of the contact plug must be increased. As the degree of integration increases, the distance between the contact plug and the contact plug becomes narrow. As the distance between the contact plugs decreases, the width of the insulating film remaining between the contact plugs decreases.
이렇게, 절연막을 좁은 폭으로 형성하면, 콘택홀을 형성한 후 실시하는 세정 공정에서 절연막이 폭이 보다 더 좁아져 절연막이 그 역할을 수행하지 못하게 된다. In this way, when the insulating film is formed in a narrow width, the insulating film becomes narrower in width in the cleaning process performed after forming the contact hole so that the insulating film does not play its role.
이로 인해, 공정의 신뢰성이 저하되고 소자의 전기적 특성이 열화되며, 심한 경우 서로 인접한 콘택 플러그가 전기적으로 연결되어 불량이 발생될 수도 있다. As a result, the reliability of the process may be degraded, the electrical characteristics of the device may be degraded, and in severe cases, contact plugs adjacent to each other may be electrically connected to each other, thereby causing a defect.
이에 대하여, 본 발명이 제시하는 반도체 소자의 콘택홀 형성 방법은 절연막에 콘택홀을 형성하고 절연막과 선택비가 상이한 물질로 콘택홀의 측벽에 스페이서를 형성하여 후속의 식각 공정이나 세정 공정 시 콘택홀 측벽의 절연막이 식각되는 것을 방지함으로써, 콘택홀 사이에 절연막을 좁은 폭으로 잔류시켜도 절연막으로써의 역할을 정상적으로 수행할 수 있어 공정의 신뢰성을 향상시키고, 이를 통해 콘택 플러그의 면적을 증가시킬 수 있어 소자의 전기적 특성을 향상시킬 수 있다. In contrast, in the method of forming a contact hole in a semiconductor device according to the present invention, a contact hole is formed in an insulating film and a spacer is formed on the sidewall of the contact hole with a material having a different selectivity from the insulating film. By preventing the insulating film from being etched, even if the insulating film is left between the contact holes with a narrow width, the insulating film can function normally as an insulating film, thereby improving the reliability of the process, thereby increasing the area of the contact plug, thereby improving the electrical properties of the device. Properties can be improved.
본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성 방법은 반도체 기판 상에 층간 절연막을 형성하는 단계와, 콘택홀이 형성될 영역의 층간 절연막에 트렌치를 형성하는 단계와, 트렌치의 측벽에 스페이서를 형성하는 단계와, 콘택홀이 형성될 영역의 층간 절연막을 완전히 제거하여 콘택홀을 형성하는 단계, 및 세정 공정을 실시하는 단계를 포함한다. A method of forming a contact hole in a semiconductor device according to an embodiment of the present invention includes forming an interlayer insulating film on a semiconductor substrate, forming a trench in the interlayer insulating film in a region where the contact hole is to be formed, and forming a spacer on a sidewall of the trench. Forming a contact hole by completely removing the interlayer insulating film in the region where the contact hole is to be formed, and performing a cleaning process.
상기에서, 트렌치는 10Å 내지 1000Å의 깊이로 형성될 수 있다. In the above, the trench may be formed to a depth of 10 Å to 1000 Å.
본 발명의 다른 실시예에 따른 반도체 소자의 콘택홀 형성 방법은 반도체 기판 상에 층간 절연막을 형성하는 단계와, 층간 절연막에 콘택홀을 형성하는 단계와, 콘택홀의 측벽에 스페이서를 형성하는 단계, 및 세정 공정을 실시하는 단계를 포함한다. In another embodiment, a method of forming a contact hole in a semiconductor device may include forming an interlayer insulating film on a semiconductor substrate, forming a contact hole in the interlayer insulating film, forming a spacer on a sidewall of the contact hole, and Performing a cleaning process.
상기에서, 스페이서는 SiNx, SiO2 또는 SiON로 형성되거나, 이들 중 적어도 두개 이상이 적층된 구조로 형성될 수 있다. 이러한 스페이서는 10Å 내지 500Å의 두께로 형성될 수 있다.In the above, the spacer may be formed of SiNx, SiO 2 or SiON, or at least two or more of them may be formed in a stacked structure. Such spacers may be formed to a thickness of 10 kPa to 500 kPa.
한편, 층간 절연막이 SiO2로 형성되고 스페이서가 SiNx로 형성될 수 있으며, 층간 절연막이 SiNx로 형성되고 스페이서가 SiO2로 형성될 수도 있다.On the other hand, when the interlayer insulating film is formed of SiO 2, and the spacer can be formed of SiNx, an interlayer insulating film is formed of a SiNx may be formed from a spacer is SiO 2.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허 청구 범위에 의해서 이해되어야 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.
한편, 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다라고 기재되는 경우에 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제3의 막이 개재되어질 수도 있다. 또한 도면에서 각 층의 두께나 크기는 설명의 편의 및 명확성을 위하여 과장되었다. 도면 상에서 동일 부호는 동일한 요소를 지칭한다.On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도들이다.1A to 1D are cross-sectional views of devices for describing a method for forming contact holes in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(101) 상에 소정의 패턴을 형성한다. 이때, 소정의 패턴으로 다수의 게이트 전극(102)이 형성될 수 있다. 게이트 전극(102)의 측벽에는 절연막 스페이서(103)가 형성되며, 게이트 전극(102) 가장자리의 반도체 기판(101)에는 소오스 또는 드레인과 같은 접합 영역(104)이 형성된다. 접합 영역(104)은 이온주입 공정으로 형성할 수 있으며, 트랜지스터나 메모리 셀의 소오스/드레인 역할을 한다.Referring to FIG. 1A, a predetermined pattern is formed on the semiconductor substrate 101. In this case, a plurality of gate electrodes 102 may be formed in a predetermined pattern. An insulating layer spacer 103 is formed on the sidewall of the gate electrode 102, and a junction region 104 such as a source or a drain is formed in the semiconductor substrate 101 at the edge of the gate electrode 102. The junction region 104 may be formed by an ion implantation process, and serves as a source / drain of a transistor or a memory cell.
이어서, 게이트 전극(102)을 포함한 전체 구조 상에 층간 절연막(105)을 형성한다. 그리고, 층간 절연막(105) 상부에는 콘택홀이 형성될 영역이 정의된 포토레지스트 패턴(106)을 형성한다. Subsequently, an interlayer insulating film 105 is formed over the entire structure including the gate electrode 102. A photoresist pattern 106 is formed on the interlayer insulating layer 105 to define a region where a contact hole is to be formed.
도 1b를 참조하면, 콘택홀 영역의 층간 절연막(105)을 소정 깊이까지 식각하여 트렌치(107)를 형성한다. 이때, 트렌치는 10Å 내지 1000Å의 깊이로 형성할 수 있다. 이후, 포토레지스트 패턴(도 1a의 106)을 제거한다. Referring to FIG. 1B, the trench 107 is formed by etching the interlayer insulating layer 105 in the contact hole region to a predetermined depth. In this case, the trench may be formed to a depth of 10 kPa to 1000 kPa. Thereafter, the photoresist pattern 106 (in FIG. 1A) is removed.
도 1c를 참조하면, 트렌치(107)의 측벽에 스페이서(108)를 형성한다. 스페이서(108)는 콘택홀을 완전히 형성한 후 실시하는 세정 공정에서 콘택홀 측벽의 층간 절연막(105)이 식각되는 것을 방지하기 위하여 형성되며, 층간 절연막(105)과는 선택비가 다른 물질로 형성된다. 예를 들면, 스페이서(108)는 SiNx, SiO2 또는 SiON로 형성하거나, 이들 중 적어도 두개 이상이 적층된 구조로 형성할 수 있다. 그리고, 스페이서(108)는 10Å 내지 500Å의 두께로 형성할 수 있다.Referring to FIG. 1C, spacers 108 are formed on sidewalls of the trench 107. The spacer 108 is formed to prevent the interlayer insulating film 105 of the contact hole sidewall from being etched in the cleaning process performed after the contact hole is completely formed, and is formed of a material having a selectivity different from that of the interlayer insulating film 105. . For example, the spacer 108 may be formed of SiNx, SiO 2, or SiON, or may have a structure in which at least two or more of them are stacked. In addition, the spacers 108 may be formed to have a thickness of 10 μs to 500 μs.
한편, 층간 절연막(105)을 SiO2로 형성하고 스페이서(108)를 SiNx로 형성할 수 있으며, 반대로 층간 절연막(105)을 SiNx로 형성하고 스페이서(108)를 SiO2로 형성할 수도 있다.Meanwhile, the interlayer insulating film 105 may be formed of SiO 2 and the spacer 108 may be formed of SiNx. In contrast, the interlayer insulating film 105 may be formed of SiNx and the spacer 108 may be formed of SiO 2 .
도 1d를 참조하면, 콘택홀 영역에 잔류하는 층간 절연막(105)을 완전히 제거하여 콘택홀(109)을 형성한다. 이로써, 하부의 접합 영역(104)이 콘택홀(109)을 통해 노출된다. Referring to FIG. 1D, the interlayer insulating layer 105 remaining in the contact hole region is completely removed to form the contact hole 109. As a result, the lower bonding area 104 is exposed through the contact hole 109.
이때, 잔류 층간 절연막(105)을 제거하는 과정에서 콘택홀(109) 측벽의 층간 절연막(105)은 스페이서(108)에 의해 식각되지 않고 형태가 그대로 유지된다. 한편, 콘택홀(109)을 형성한 후에는 세정 공정이 실시되는데, 이 경우에도 콘택홀(109) 측벽의 층간 절연막(105)은 스페이서(108)에 의해 식각되지 않고 형태가 그대로 유지된다.At this time, in the process of removing the remaining interlayer insulating layer 105, the interlayer insulating layer 105 of the sidewall of the contact hole 109 is not etched by the spacer 108, and the shape is maintained. On the other hand, after the contact hole 109 is formed, a cleaning process is performed. In this case, the interlayer insulating layer 105 of the sidewall of the contact hole 109 is not etched by the spacer 108 and the shape is maintained.
이렇게, 콘택홀(109) 측벽의 층간 절연막(105)이 후속의 식각 공정이나 세정 공정에 의해 식각되지 않고 그대로 잔류되기 때문에, 콘택홀(109)의 간격을 좁히기 위하여 콘택홀(109) 사이의 층간 절연막(105) 폭을 좁히더라도 문제가 발생되지 않는다.As such, since the interlayer insulating film 105 of the sidewalls of the contact holes 109 is not etched by the subsequent etching process or the cleaning process, the interlayer insulating film 105 remains as it is, so that the interlayer between the contact holes 109 is narrowed in order to narrow the gap between the contact holes 109. Even if the width of the insulating film 105 is narrowed, no problem occurs.
한편, 상기에서는 층간 절연막(105)에 트렌치(107)를 먼저 형성하고 트렌치(107)의 측벽에 스페이서(108)를 형성한 후 콘택홀(109)을 형성하였으나, 콘택홀(109)을 완전히 형성하고 콘택홀(109)의 측벽에 스페이서(108)를 형성하여도 후속의 세정 공정에서 콘택홀(109) 측벽의 층간 절연막(105)이 식각되는 것을 방지할 수 있다. Meanwhile, although the trench 107 is first formed in the interlayer insulating layer 105 and the spacer 108 is formed on the sidewall of the trench 107, the contact hole 109 is formed, but the contact hole 109 is completely formed. In addition, even if the spacer 108 is formed on the sidewall of the contact hole 109, the interlayer insulating layer 105 of the sidewall of the contact hole 109 may be etched in a subsequent cleaning process.
상술한 바와 같이, 본 발명은 절연막에 콘택홀을 형성하고 절연막과 선택비가 상이한 물질로 콘택홀의 측벽에 스페이서를 형성하여 후속의 식각 공정이나 세정 공정 시 콘택홀 측벽의 절연막이 식각되는 것을 방지함으로써, 콘택홀 사이에 절연막을 좁은 폭으로 잔류시켜도 절연막으로써의 역할을 정상적으로 수행할 수 있어 공정의 신뢰성을 향상시키고, 이를 통해 콘택 플러그의 면적을 증가시킬 수 있어 소자의 전기적 특성을 향상시킬 수 있다.As described above, the present invention is formed by forming a contact hole in the insulating film and forming a spacer on the sidewall of the contact hole with a material having a different selectivity from the insulating film, thereby preventing the insulating film on the sidewall of the contact hole from being etched during the subsequent etching or cleaning process. Even if the insulating film is left between the contact holes in a narrow width, the insulating film can be normally operated to improve the reliability of the process, thereby increasing the area of the contact plug, thereby improving the electrical characteristics of the device.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도들이다. 1A to 1D are cross-sectional views of devices for describing a method for forming contact holes in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
101 : 반도체 기판 102 : 게이트 전극101 semiconductor substrate 102 gate electrode
103 : 절연막 스페이서 104 : 접합 영역103: insulating film spacer 104: junction region
105 : 층간 절연막 106 : 포토레지스트 패턴105: interlayer insulating film 106: photoresist pattern
107 : 트렌치 108 : 스페이서107: trench 108: spacer
109 : 콘택홀 109: contact hole
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030097645A KR20050066369A (en) | 2003-12-26 | 2003-12-26 | Method of forming a contact hole in a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030097645A KR20050066369A (en) | 2003-12-26 | 2003-12-26 | Method of forming a contact hole in a semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20050066369A true KR20050066369A (en) | 2005-06-30 |
Family
ID=37257453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030097645A KR20050066369A (en) | 2003-12-26 | 2003-12-26 | Method of forming a contact hole in a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20050066369A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7884014B2 (en) | 2007-07-10 | 2011-02-08 | Samsung Electronics Co., Ltd. | Method of forming contact structure with contact spacer and method of fabricating semiconductor device using the same |
| US9859163B2 (en) | 2015-08-12 | 2018-01-02 | Samsung Electronics Co., Ltd. | Methods for manufacturing a semiconductor device |
| US11929280B2 (en) | 2020-09-22 | 2024-03-12 | Changxin Memory Technologies, Inc. | Contact window structure and method for forming contact window structure |
| US12002748B2 (en) | 2020-09-22 | 2024-06-04 | Changxin Memory Technologies, Inc. | Contact window structure, metal plug and forming method thereof, and semiconductor structure |
-
2003
- 2003-12-26 KR KR1020030097645A patent/KR20050066369A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7884014B2 (en) | 2007-07-10 | 2011-02-08 | Samsung Electronics Co., Ltd. | Method of forming contact structure with contact spacer and method of fabricating semiconductor device using the same |
| KR101244456B1 (en) * | 2007-07-10 | 2013-03-18 | 삼성전자주식회사 | Method of forming a contact structure with a contact spacer and method of fabricating a semiconductor device using the same |
| US9859163B2 (en) | 2015-08-12 | 2018-01-02 | Samsung Electronics Co., Ltd. | Methods for manufacturing a semiconductor device |
| US11929280B2 (en) | 2020-09-22 | 2024-03-12 | Changxin Memory Technologies, Inc. | Contact window structure and method for forming contact window structure |
| US12002748B2 (en) | 2020-09-22 | 2024-06-04 | Changxin Memory Technologies, Inc. | Contact window structure, metal plug and forming method thereof, and semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20050066369A (en) | Method of forming a contact hole in a semiconductor device | |
| KR100945229B1 (en) | Method for manufacturing semiconductor device | |
| KR100244426B1 (en) | Method of forming contact hole in semiconductor device | |
| KR20010004237A (en) | A method for forming semiconductor memory device including self-aligned contact process | |
| KR100277905B1 (en) | Manufacturing Method of Semiconductor Memory Device | |
| KR101026370B1 (en) | Method for manufacturing semiconductor davice | |
| KR100743622B1 (en) | Method for manufacturing bit line contact of semiconductor device | |
| KR20030063642A (en) | Method of semiconductor device having a borderless contact hole | |
| KR100935197B1 (en) | Method for forming of semiconductor device | |
| KR100745057B1 (en) | Method for fabricating of semiconductor device | |
| KR100832019B1 (en) | Method for fabricating storage node contact in semiconductor device | |
| KR100504948B1 (en) | Method of forming contact plug in semiconductor devices | |
| KR100609523B1 (en) | A method for forming a self-aligned contact of a semiconductor device | |
| KR20060000681A (en) | Method for fabricating semiconductor devices | |
| KR20090123514A (en) | Semiconductor device and manufacturing method of the same | |
| KR20020049373A (en) | Method for Fabricating of Semiconductor Device | |
| KR20040060335A (en) | A method for forming a self-aligned contact of a semiconductor device | |
| KR20060109053A (en) | Method of manufacturing semiconductor device | |
| KR20080062011A (en) | Method of manufacturing semiconductor device | |
| KR19990024686A (en) | A semiconductor device having a pad electrode adjacent to a cell and a manufacturing method thereof | |
| KR20050022168A (en) | Method of manufacturing semiconductor device | |
| KR20040008482A (en) | A method for forming a semiconductor device | |
| KR20060075322A (en) | Method for fabricating semiconductor device | |
| KR20060075300A (en) | Method for fabricating semiconductor device | |
| KR20030057880A (en) | Method of manufacturing a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |