KR101026370B1 - Method for manufacturing semiconductor davice - Google Patents

Method for manufacturing semiconductor davice Download PDF

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KR101026370B1
KR101026370B1 KR1020030096915A KR20030096915A KR101026370B1 KR 101026370 B1 KR101026370 B1 KR 101026370B1 KR 1020030096915 A KR1020030096915 A KR 1020030096915A KR 20030096915 A KR20030096915 A KR 20030096915A KR 101026370 B1 KR101026370 B1 KR 101026370B1
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gate
etching
buffer oxide
insulating film
depositing
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KR1020030096915A
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KR20050065147A (en
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정태오
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

본 발명은 버티컬한 게이트 프로파일을 확보할 뿐만 아니라, 게이트와 랜딩 플러그 간 SAC 페일을 확보할 수 있도록 하는 반도체 소자의 제조 방법에 관한 것으로, 상기 반도체 소자의 제조 방법은 소정의 하부 구조가 형성된 반도체 기판상의 하드 마스크용 질화막 패턴을 이용한 식각 공정으로 게이트 전극을 형성하는 단계와; 상기 게이트 전극이 덮히도록 버퍼 산화막을 증착하는 단계와; 상기 버퍼 산화막 상부에 제 1 포토레지스트 패턴을 형성하는 단계와; 상기 제 1 포토레지스트 패턴을 마스크로 게이트 전극 상부가 노출되도록 상기 버퍼 산화막을 식각하는 단계와; 상기 버퍼 산화막을 식각한 결과물에 전면에 절연막을 증착하는 단계와; 상기 절연막 상부에 제 2 포토레지스트 패턴을 형성하고 식각 공정을 진행하여 상기 절연막이 역 사다리꼴이 되도록 하는 단계와; 상기 절연막을 식각한 결과물 전면에 스페이서 물질을 증착하고 식각 공정을 진행하여 게이트 스페이서를 형성하는 단계를 포함하여 구성된다.
The present invention relates to a method of manufacturing a semiconductor device that not only secures a vertical gate profile but also secures a SAC fail between a gate and a landing plug. The method of manufacturing a semiconductor device includes a semiconductor substrate having a predetermined substructure. Forming a gate electrode by an etching process using a nitride film pattern for a hard mask on the substrate; Depositing a buffer oxide layer to cover the gate electrode; Forming a first photoresist pattern on the buffer oxide layer; Etching the buffer oxide layer using the first photoresist pattern as a mask to expose an upper portion of the gate electrode; Depositing an insulating film on the entire surface of the result of etching the buffer oxide film; Forming a second photoresist pattern on the insulating film and performing an etching process so that the insulating film becomes an inverted trapezoid; And depositing a spacer material on the entire surface of the resultant of etching the insulating film and performing an etching process to form a gate spacer.

하드마스크, 게이트 절연막, 랜징 플러그, 프로파일Hard Mask, Gate Insulation, Ranging Plug, Profile

Description

반도체 소자의 제조 방법{Method for manufacturing semiconductor davice} Method for manufacturing semiconductor device             

도1a 내지 도1g는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 순차적인 공정 단면도들이다.
1A to 1G are sequential process cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

- 도면의 주요부분에 대한 부호의 설명 -   -Explanation of symbols for the main parts of the drawings-

100 : 실리콘 기판 110 : 필드 산화막100 silicon substrate 110 field oxide film

120 : 게이트 산화막 130 : 폴리실리콘120: gate oxide film 130: polysilicon

140 : 텅스텐 실리사이드 150 : 하드 마스크140: tungsten silicide 150: hard mask

160 : 버퍼 산화막 170 : 게이트 절연막160: buffer oxide film 170: gate insulating film

180 : 콘택홀 190 : 게이트 스페이서
180: contact hole 190: gate spacer

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 게이트 프로파일을 특성을 향상시키고 랜딩 플러그와 게이트간 SAC 페일 유발을 방지함으 로써 소자의 신뢰성을 향상시킬 수 있도록 하는 반도체 소자의 제조 방법에 관한 것이다.
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device to improve the reliability of the device by improving the characteristics of the gate profile and preventing the SAC failure between the landing plug and the gate. It is about.

반도체 장치가 고집적화 됨에 따라 메모리 셀 크기가 점점 감소되어 워드 라인 또는 비트라인 사이의 콘택 마진이 점차 작아지고 있다. 이에 따라, 콘택 마진을 높이기 위한 방안으로서, 자기 정렬 콘택(self-aligned contact : 이하 SAC라 함) 제조 기술이 있다. As semiconductor devices are highly integrated, memory cell sizes are gradually reduced, and contact margins between word lines and bit lines are gradually decreasing. Accordingly, there is a technique for manufacturing a self-aligned contact (hereinafter referred to as SAC) as a method for increasing the contact margin.

상기 SAC 제조 방법은 주변 구조물의 단차를 이용하여 콘택홀을 형성하는 것으로, 주변 구조물의 높이, 콘택홀이 형성될 절연 물질의 두께 및 식각 방법 등에 의해 다양한 크기의 콘택홀을 마스크 없이 형성할 수 있기 때문에 고집적화에 의해 미세화되는 반도체 장치의 실현에 적합한 방법으로 이용된다.The SAC manufacturing method is to form a contact hole using a step of the peripheral structure, it is possible to form a contact hole of various sizes without a mask by the height of the peripheral structure, the thickness of the insulating material to be formed and the etching method, etc. Therefore, it is used as a method suitable for realization of a semiconductor device which is miniaturized by high integration.

종래의 SAC 방식의 랜딩 플러그(Landing plug)는 게이트 전극 사이를 층간 절연막으로 채우고 랜딩 플러그가 형성될 부분을 게이트 전극의 스페이서에 의해 SAC 식각하여 콘택홀을 형성한 다음, 상기 콘택홀에 도프트 폴리실리콘을 매립하고 나서 평탄화 공정을 진행하여 제조하게 된다.The conventional SAC landing plug fills the gate electrodes with an interlayer insulating film, forms a contact hole by SAC etching the portion where the landing plug is to be formed by the spacer of the gate electrode, and then forms a doped poly in the contact hole. The silicon is buried and then the planarization process is performed.

그런데, 종래의 SAC 방식의 랜딩 플러그 제조 방법에 의하면 게이트 식각시 하드 마스크로 질화막을 이용함으로써, 질화막의 두께가 높을 경우 게이트 프로파일이 버티컬(Vertical)하지 못하고, 질화막 두께가 낮을 경우 후속 랜딩 플러그 콘택 형성시에 게이트의 단락을 유발하는 문제점이 있었다.However, according to the conventional method of manufacturing a landing plug of the SAC method, by using a nitride film as a hard mask during gate etching, when the thickness of the nitride film is high, the gate profile cannot be vertical, and when the thickness of the nitride film is low, subsequent landing plug contacts are formed. There was a problem that caused a short circuit in the gate.

상기와 같은 문제점을 해결하기 위한 본 발명은 하드 마스크 두께를 기존 대비 낮게 하여 게이트 프로파일을 개선할 뿐만 아니라, 게이트 상부에 절연 물질을 추가로 절연 물질을 증착함으로써 후속 형성되는 랜딩 플러그와 게이트의 SAC 페일 유발을 방지할 수 있도록 하는 반도체 소자의 제조 방법을 제공하기 위한 것이다.
In order to solve the above problems, the present invention not only improves the gate profile by lowering the hard mask thickness, but also deposits an insulating material on top of the gate, and subsequently forms a landing plug and a SAC fail of the gate. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing the occurrence of the chip.

본 발명의 일 관점은, 반도체 기판상의 하드 마스크용 질화막 패턴을 식각 마스크로 이용하여 게이트 전극을 위한 층을 식각하여 게이트 전극을 형성하는 단계와; 상기 게이트 전극 및 하드 마스크용 질화막 패턴이 덮히도록 버퍼 산화막을 증착하는 단계와; 상기 버퍼 산화막 상부에 제 1 포토레지스트 패턴을 형성하는 단계와; 상기 제 1 포토레지스트 패턴을 마스크로 상기 하드 마스크용 질화막 패턴이 노출되도록 상기 버퍼 산화막을 식각하는 단계와; 상기 버퍼 산화막을 식각한 결과물 전면에 절연막을 증착하는 단계와; 상기 절연막 상부에 제 2 포토레지스트 패턴을 형성하고 식각 공정을 진행하여 상기 절연막이 역 사다리꼴이 되도록 하는 단계와; 상기 절연막을 식각한 결과물 전면에 스페이서 물질을 증착하고 식각 공정을 진행하여 게이트 스페이서를 형성하는 단계를 포함하는 반도체 소자의 제조 방법을 제시한다. One aspect of the present invention includes the steps of forming a gate electrode by etching a layer for the gate electrode using the nitride film pattern for a hard mask on the semiconductor substrate as an etching mask; Depositing a buffer oxide film to cover the gate electrode and the nitride film pattern for the hard mask; Forming a first photoresist pattern on the buffer oxide layer; Etching the buffer oxide layer using the first photoresist pattern as a mask to expose the nitride layer pattern for the hard mask; Depositing an insulating film on the entire surface of the result of etching the buffer oxide film; Forming a second photoresist pattern on the insulating film and performing an etching process so that the insulating film becomes an inverted trapezoid; A method of fabricating a semiconductor device includes depositing a spacer material on an entire surface of a resultant of etching the insulating film and performing an etching process to form a gate spacer.

이와 같은 본 발명에 의한 반도체 소자의 제조 방법에 의하면, 게이트 상부 의 하드 마스크 두께를 종래 대비 낮춤으로써 버티컬한 게이트 프로파일을 확보하고, 게이트 상부의 높은 절연 물질 확보 및 최상부 절연 물질의 면적을 넓게 형성시킴으로써 랜딩 플러그와 게이트의 SAC 페일 유발을 방지할 수 있는 이점이 있다.
According to the method of manufacturing a semiconductor device according to the present invention, by lowering the thickness of the hard mask on the upper gate, the vertical gate profile is secured, the high insulating material on the gate is secured, and the uppermost insulating material is broadened. This has the advantage of preventing the landing plug and gate from causing SAC fail.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same symbols and names.

도1a 내지 도1g는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 순차적인 공정 단면도들이다.1A to 1G are sequential process cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

우선, 도1a에 도시된 바와 같이 실리콘 기판(100)에 필드 산화막(110)을 형성하여 액티브 영역과 필드 영역을 분리한 후에 게이트 산화막(120), 게이트 폴리실리콘(130) 및 텅스텐(140)을 차례로 형성한다. 그런 후에 텅스텐 상부에 하드 마스크용 질화막(150) 패턴을 형성하고, 상기 질화막(150) 패턴을 식각 마스크로 식각 공정을 진행함으로써 게이트 전극을 패터닝한다. 이때, 질화막은 10~1500Å 범위에서 기존 대비 낮게 함으로써 버티컬한 게이트 프로파일을 형성할 수 있다.First, as shown in FIG. 1A, the field oxide layer 110 is formed on the silicon substrate 100 to separate the active region and the field region, and then the gate oxide layer 120, the gate polysilicon 130, and the tungsten 140 are removed. Form in turn. Thereafter, the nitride film 150 pattern for the hard mask is formed on the tungsten, and the gate electrode is patterned by performing an etching process using the nitride film 150 pattern as an etching mask. In this case, the nitride film may be formed in a vertical gate profile by lowering it in the range of 10 to 1500 kHz.

이후 도시되지는 않지만, 게이트 전극 양측 하부의 실리콘 기판에 소오스/드레인 접합 영역을 형성한다.Although not shown, a source / drain junction region is formed in the silicon substrate under both sides of the gate electrode.

이어서, 도1b에 도시된 바와 같이 버퍼 산화막(160)을 전면에 증착하되, 상기 버퍼 산화막은 게이트를 충분히 덮고 후속 게이트 상부의 절연 물질의 두께를 충분히 확보할 수 있을 정도로 2000Å 이상 증착한다.Subsequently, as illustrated in FIG. 1B, the buffer oxide layer 160 is deposited on the entire surface, and the buffer oxide layer is deposited to be 2000 mu m or more to sufficiently cover the gate and to sufficiently secure the thickness of the insulating material on the subsequent gate.

그런 다음, 도시되지는 않지만 네거티브 포토레지스트 패턴을 이용하여 게이트 전극 상부에 증착되어 있는 버퍼 산화막(160)을 식각하여 도1c와 같이 형성한다. 이때, 식각 공정은 버퍼 산화막에 약간의 슬로프가 형성되도록 식각하여 게이트 상부를 오픈시킨다.Then, although not shown, the buffer oxide layer 160 deposited on the gate electrode is etched using a negative photoresist pattern to form the same as in FIG. 1C. At this time, the etching process is etched so that a slight slope is formed in the buffer oxide layer to open the gate top.

이어서, 도1d에 도시된 바와 같이 게이트 상부 절연 물질로 질화막(170)을 10~5000Å 증착하여 상기 버퍼 산화막(160)이 식각된 부분을 매립한다. Subsequently, as illustrated in FIG. 1D, the nitride film 170 is deposited by using 10 to 5000 Å with a gate upper insulating material to fill the etched portion of the buffer oxide film 160.

그리고 나서, 도1e에 도시된 바와 같이 포지티브 포토레지스트 패턴(미도시함)을 이용하여 상기 질화막(170) 및 버퍼 산화막(160)을 식각하여 실리콘 기판(100)의 액티브 영역이 드러나도록 콘택홀(180)을 형성한다. 이때, 상기 게이트 상부 질화막(170)이 역사다리꼴 모양이 되도록 함으로써, 절연 물질의 면적을 넓게 하여 후속 랜딩 플러그와 게이트와의 SAC 페일 유발을 방지할 수 있다.Then, as illustrated in FIG. 1E, the nitride layer 170 and the buffer oxide layer 160 are etched using a positive photoresist pattern (not shown) to expose the active region of the silicon substrate 100. 180). In this case, the gate upper nitride film 170 may be formed in an inverted trapezoidal shape, thereby increasing the area of the insulating material, thereby preventing a subsequent SAC fail between the landing plug and the gate.

상기 콘택홀을 형성한 결과물에 도1f에 도시된 바와 같이 게이트 스페이서로 이용할 질화막을 증착한 후 건식 식각 공정을 진행하여 도1g와 같이 스페이서(190)를 형성한다.As shown in FIG. 1F, a nitride film to be used as a gate spacer is deposited on the resultant of the contact hole, followed by a dry etching process to form a spacer 190 as shown in FIG. 1G.

이와 같이 본 발명에 의한 반도체 소자의 제조 방법에 의하면, 게이트 하드 마스크의 두께를 기존 대비 낮게 하여 게이트 프로파일을 개선하고, 후속 공정시 게이트 상부에 절연막을 추가로 형성함으로써, 기존 보다 높은 절연막 두께를 확보함으로써 후속 형성되는 랜딩 플러그와 게이트의 SAC 페일을 방지할 수 있다.
As described above, according to the method of manufacturing a semiconductor device according to the present invention, the thickness of the gate hard mask is lowered compared to the existing one, thereby improving the gate profile, and further forming an insulating film on the gate during the subsequent process, thereby securing a higher insulating film thickness than the existing one. As a result, it is possible to prevent SAC failing of subsequent landing plugs and gates.

상기한 바와 같이 본 발명은 하드 마스크 두께를 낮춤으로써 버티컬한 게이트 프로파일을 확보하고, 게이트 상부의 높은 절연 물질 확보 및 최상부 절연 물질의 면적을 넓게 형성시킴으로써 랜딩 플러그와 게이트의 SAC 페일 유발을 방지할 수 있는 이점이 있다.As described above, the present invention can secure the vertical gate profile by lowering the hard mask thickness, and secure a high insulating material on the gate and widen the area of the top insulating material, thereby preventing SAC failing of the landing plug and the gate. There is an advantage to that.

Claims (6)

반도체 기판상의 하드 마스크용 질화막 패턴을 식각 마스크로 이용하여 게이트 전극을 위한 층을 식각하여 게이트 전극을 형성하는 단계와;Etching the layer for the gate electrode using the nitride film pattern for a hard mask on the semiconductor substrate as an etching mask to form a gate electrode; 상기 게이트 전극 및 하드 마스크용 질화막 패턴이 덮히도록 버퍼 산화막을 증착하는 단계와;Depositing a buffer oxide film to cover the gate electrode and the nitride film pattern for the hard mask; 상기 버퍼 산화막 상부에 제 1 포토레지스트 패턴을 형성하는 단계와;Forming a first photoresist pattern on the buffer oxide layer; 상기 제 1 포토레지스트 패턴을 마스크로 상기 하드 마스크용 질화막 패턴이 노출되도록 상기 버퍼 산화막을 식각하는 단계와;Etching the buffer oxide layer using the first photoresist pattern as a mask to expose the nitride layer pattern for the hard mask; 상기 버퍼 산화막을 식각한 결과물 전면에 절연막을 증착하는 단계와;Depositing an insulating film on the entire surface of the result of etching the buffer oxide film; 상기 절연막 상부에 제 2 포토레지스트 패턴을 형성하고 식각 공정을 진행하여 상기 절연막이 역 사다리꼴이 되도록 하는 단계와;Forming a second photoresist pattern on the insulating film and performing an etching process so that the insulating film becomes an inverted trapezoid; 상기 절연막을 식각한 결과물 전면에 스페이서 물질을 증착하고 식각 공정을 진행하여 게이트 스페이서를 형성하는 단계를Depositing a spacer material on the entire surface of the resultant of etching the insulating film and performing an etching process to form a gate spacer 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.A method of manufacturing a semiconductor device, comprising. 제 1항에 있어서, 상기 제 1 포토레지스트 패턴은 네거티브 포토레지스트인 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the first photoresist pattern is a negative photoresist. 제 1항에 있어서, 상기 하드 마스크는 질화막을 10~1500Å 두께로 증착하여 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the hard mask is formed by depositing a nitride film having a thickness of 10 to 1500 Å. 제 1항에 있어서, 상기 버퍼 산화막은 2000Å 인 것을 특징으로 하는 반도체 소자의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein said buffer oxide film is 2000 microseconds. 제 1항에 있어서, 상기 절연막은 질화막으로 10~5000Å 높이로 증착하는 것을 특징으로 하는 반도체 소자의 제조 방법. The method of claim 1, wherein the insulating film is deposited to a nitride film having a height of 10 to 5000 GPa. 제 1항에 있어서, 상기 제 2 포토레지스트 패턴은 포지티브 포토레지스트 인 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the second photoresist pattern is a positive photoresist.
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