KR20090123514A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent the loss of an oxide barrier layer due to the dielectric layer etching process by forming an oxidation barrier layer in the sidewall of the dielectric layer and a control gate layer. CONSTITUTION: A tunnel insulation layer(103), a floating gate layer(105), a dielectric layer(107) are formed on a semiconductor substrate(101). A control gate layer(114) is formed on the dielectric layer. The control gate layer is patterned to expose the dielectric layer. The dielectric layer is patterned to expose the floating gate layer. An oxidation barrier layer(119) is formed in a sidewall of the dielectric layer and the control gate layer which are patterned. The floating gate layer is patterned to expose the tunnel insulation layer. The oxidation process is performed in a temperature of 700 to 1000 degrees centigrade.

Description

Semiconductor device and manufacturing method of the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same, which can widen the spacing between floating gates even when a metal film is introduced to reduce the resistance of the control gate.

As semiconductor devices have been highly integrated, various conductive patterns constituting the semiconductor devices have been miniaturized. Accordingly, since the resistance of the conductive pattern is increasing, various methods for reducing the resistance of the conductive pattern have been proposed. As an example, a method of introducing a metal film into a control gate of a flash device has been proposed.

The flash device includes a gate pattern including a floating gate film, a dielectric film, and a control gate film. Among them, the control gate layer is formed of a structure in which a metal film is stacked on top of polysilicon and polysilicon in order to reduce resistance and improve driving speed of a semiconductor device. The gate pattern of this structure is formed by providing a tunnel insulating film, a floating gate film, and a semiconductor substrate on which a dielectric film is formed, and then forming a control gate film in which a polysilicon film and a metal film are laminated on the dielectric film and patterning them.

In detail, the process of patterning the floating gate film, the dielectric film, and the control gate film is performed. After forming a hard mask pattern on the control gate film, the metal film of the control gate film is first etched using the hard mask. Metal contaminants are generated due to the metal film etching process, and the metal contaminants need to be removed because they contaminate the tunnel insulating film and the like, which degrades the characteristics of the semiconductor device. In order to remove metal contaminants, an oxidation process must be performed after the metal film etching process. Since the metal film may be oxidized when the metal film is exposed during the oxidation process for removing metal contaminants, the metal film is etched to form an anti-oxidation film on the sidewall of the metal film to prevent oxidation. Thereafter, an etching process is performed to sequentially etch the polysilicon film, the dielectric film, and the floating gate film of the control gate. At this time, the polysilicon film, the dielectric film, and the floating gate film of the control gate formed under the metal film and the anti-oxidation film are not exposed to the etching material and thus remain without being removed. On the other hand, the antioxidant film may be formed including the same material as the dielectric film. As a result, a portion of the antioxidant layer may be lost during the etching of the dielectric layer. In order to prevent the metal film from being exposed due to the loss of the antioxidant film, the thickness of the antioxidant film formed on the sidewall of the metal film should be increased. When the thickness of the antioxidant layer is increased, the width of the floating gate pattern formed under the antioxidant layer and the metal layer after the etching process is also increased. As a result, the spacing between the floating gate patterns adjacent to each other becomes close, and thus, the threshold voltage Vt distribution characteristic of the semiconductor device becomes poor due to the interference of the neighboring floating gates.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same, which can widen the spacing between floating gates even when a metal film is introduced to reduce the resistance of the control gate.

The semiconductor device according to the present invention is a floating gate formed on a semiconductor substrate with a tunnel insulating film interposed therebetween, a dielectric film formed on the floating gate, a control gate formed on the dielectric film, and an oxide formed on the sidewall of the control gate and the sidewall of the dielectric film. It contains a prevention film.

A method of manufacturing a semiconductor device according to the present invention includes providing a semiconductor substrate having a tunnel insulating film, a floating gate film, and a dielectric film, forming a control gate film on the dielectric film, patterning the control gate film so that the dielectric film is exposed, and floating. Patterning the dielectric film to expose the gate film, forming an oxide film on sidewalls of the patterned control gate film and the dielectric film, and patterning the floating gate film to expose the tunnel insulating film.

After patterning the floating gate layer, the method may further include performing an oxidation process at a temperature of 700 ° C to 1000 ° C.

The oxidation process is carried out so that the sidewalls of the patterned floating gate are oxidized to a thickness of 20 kPa to 30 kPa.

In the step of patterning the dielectric film so that the floating gate film is exposed, an upper portion of the exposed floating gate film is further etched.

The floating gate layer remaining under the patterned dielectric layer is formed in a trapezoidal shape having a narrower upper portion than the lower portion.

The antioxidant film extends to the upper sidewall of the floating gate film.

The antioxidant film formed on the upper sidewall of the floating gate film is formed thinner toward the bottom.

Forming an anti-oxidation film on the sidewalls of the patterned control gate film and the dielectric film may include forming an anti-oxidation film on the floating gate film including the patterned control gate film and the sidewalls of the dielectric film, and forming an antioxidant film formed on the upper surface of the floating gate film. Etching the antioxidant film to remove it.

In the step of forming the antioxidant film on the floating gate film including the patterned control gate film and the sidewalls of the dielectric film, the thickness of the antioxidant film is preferably 70 kPa to 100 kPa.

The etching of the antioxidant film is performed using an etching gas containing at least one of CFH ₃ and CH ₂ F ₂ .

The etching of the antioxidant film is performed by targeting a thickness of 100% to 200% of the thickness of the antioxidant film.

Patterning the floating gate film to expose the tunnel insulating film is performed using a mixed gas containing HBr and O ₂ .

The antioxidant film includes a nitride film.

The control gate film includes a polysilicon film and a metal film stacked over the polysilicon film.

The metal film contains tungsten.

The floating gate film includes a polysilicon film.

After patterning the floating gate layer, forming a spacer using an oxide layer on sidewalls of the gate pattern including the floating gate layer, the dielectric layer, the control gate layer, and the anti-oxidation layer, and etching the nitride layer on the surface of the spacer. And forming a stop film.

According to the present invention, since an oxide film is formed on sidewalls of the control gate film and the dielectric film after the dielectric film is etched, the oxidation film may be prevented from being lost due to the dielectric film etching process.

Since the present invention can prevent the loss of the antioxidant film, it is possible to prevent the metal film from being exposed to maximize the capping capability of the metal film.

Since the present invention can prevent the metal film from being exposed, the metal film can be prevented from being oxidized even when the reoxidation process is performed.

The present invention can prevent the loss of the antioxidant film under the influence of the dielectric film etching process, thereby minimizing the thickness of the antioxidant film.

The present invention can minimize the thickness of the antioxidant film, thereby reducing the width of the floating gate.

The present invention can minimize the width of the floating gate can reduce the interference between the floating gates.

Since the present invention can reduce the interference between the floating gates, it is possible to improve the threshold voltage distribution.

The present invention can remove metal contaminants and plasma damage generated in the tunnel insulating film by performing the reoxidation process, thereby improving data retention characteristics of the semiconductor device.

In the present invention, the anti-oxidation layer may serve as an etch stop layer to prevent the gate pattern from being exposed during the subsequent process of forming a contact hole exposing the junction region, and thus the double etch stop layer together with the etch stop layer formed after the gate pattern is formed. Can be provided.

Since the present invention can provide a double etching prevention structure, it is effective in improving SAC Fail.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 1A, a patterned dielectric film 107 and a control gate film 114 are formed on a semiconductor substrate 101 on which a tunnel insulating film 103 and a floating gate film 105 are formed. 107 and the process of patterning the control gate film 114 will be described in detail.

First, a semiconductor substrate 101 on which a tunnel insulating film 103 and a floating gate film 105 are formed is provided. The floating gate film 105 includes a polysilicon film. The tunnel insulating layer 103 and the floating gate layer 105 may be patterned by forming a device isolation layer (not shown) that separates the active region of the semiconductor substrate 101.

Thereafter, the dielectric film 107 and the control gate film 114 are formed on the semiconductor substrate 101 on which the tunnel insulating film 103 and the floating gate film 105 are formed.

The dielectric film 107 may have an ONO (Oxide / Nitride / Oxide) structure in which a first oxide film, a nitride film, and a second oxide film are stacked as an insulating film. In addition, the dielectric film 107 includes a contact hole exposing the floating gate film 105. In the case of a flash memory device, the semiconductor substrate 101 includes a memory cell region in which memory cells are to be formed and a select transistor region in which select transistors are to be formed. The contact holes included in the dielectric film 107 are formed in the select transistor region. In addition, the contact hole included in the dielectric layer 107 may be formed by forming a photoresist pattern on the dielectric layer 107 and then etching the dielectric layer 107 using the photoresist pattern as an etching mask. Meanwhile, when the dielectric film 107 is etched using only the photoresist pattern, the capping polysilicon film 109 before the photoresist pattern is formed to prevent the loss of the dielectric film 107 except for the portion where the contact hole is formed. ) May be further formed. The capping polysilicon layer 109 is patterned by an etching process using a photoresist pattern as an etching mask before the contact hole is formed in the dielectric layer 107. Thereafter, the dielectric film 107 is etched using the patterned capping polysilicon film 109 as an etching mask to form a contact hole for exposing the floating gate film 105 in the dielectric film 107. The photoresist pattern may be removed after the contact hole is formed in the dielectric layer 107.

The control gate layer 114 includes a metal layer 113. In more detail, the control gate film 114 has a structure in which the polysilicon film 111 and the metal film 113 are stacked. The polysilicon layer 111 is electrically connected to the floating gate layer 105 through a contact hole formed in the dielectric layer 107. The metal film 113 is added to lower the resistance of the control gate film 114 and includes a metal having a lower specific resistance than polysilicon such as tungsten (W). Between the polysilicon film 111 and the metal film 113, the metal ions contained in the metal film 113 are prevented from being diffused into the dielectric film 107, and the metal film 113 is formed at the lower portion thereof. A metal nitride film may be further formed to prevent the thickness from changing in response. The metal nitride film includes a tungsten nitride film WN.

The hard mask pattern 117 is formed on the control gate layer 114. The hard mask pattern 117 is a pattern defining a region in which the control gate layer 114 and the dielectric layer 107 are to be patterned. Before the hard mask pattern 117 is formed, a SiON film 115 may be further formed to improve the adhesion between the metal film 113 and the hard mask pattern 117.

After the hard mask pattern 117 is formed, the etching process is performed using the hard mask pattern 117 as an etching mask to pattern the SiON film 115, the metal film 113, and the polysilicon film 111 to form a dielectric. The membrane 107 is exposed. Thereafter, the dielectric film 107 is patterned by etching the exposed dielectric film 107 using a mixed gas containing CF ₄ , CHF ₃ , and O ₂ gas. As the dielectric film 107 is patterned, the floating gate film 105 is exposed, and the exposed floating gate film 105 is further etched by the mixed gas injected to etch the dielectric film 107 so that the dielectric film 107 is exposed. ) Can be clearly distinguished by pattern. At this time, the floating gate film 105 is not completely patterned and remains on the tunnel insulating film 103 in a thickness of 200 mW to 500 mW to prevent the tunnel insulating film 103 from being damaged or contaminated. In this case, the sidewall of the etched floating gate layer 105 is formed to be inclined at 20 ° to 50 ° with respect to the semiconductor substrate 101 due to the etching process. As a result, the floating gate layer 105 remaining under the dielectric layer 107 becomes a trapezoidal shape whose width is narrower than the width of the lower portion.

As described above, the patterned control gate layer 114 becomes a word line in the memory cell region and becomes a select line in the select transistor region. The select line includes a source select line and a drain select line. The plurality of word lines are formed side by side between the source select line and the drain select line. Here, the spacing between the select lines is wider than the spacing between word lines.

Referring to FIG. 1B, metal contaminants such as tungsten polymer (W polymer) generated during etching of the metal layer 113 are removed by a wet cleaning process. Thereafter, the surface of the hard mask pattern 117, the patterned SiON film 115, the control gate film 114, the capping polysilicon film 109, the sidewalls of the dielectric film 107, and the exposed floating gate film 105. The anti-oxidation film 119 is formed on the surface.

The antioxidant film 119 includes a nitride film. In addition, since the anti-oxidation film 119 is formed after the dielectric film 107 is patterned as described above with reference to FIG. 1A, the anti-oxidation film 119 may be formed with a thin thickness without considering a thickness to be additionally lost. Here, the thickness of the antioxidant film 119 is preferably deposited to a thickness of 70 kPa to 100 kPa. Since the floating gate layer 105 under the patterned dielectric layer 107 is formed in a trapezoidal shape having a narrow upper portion as described above with reference to FIG. 1A, the thickness of the anti-oxidation layer 119 formed on the sidewall of the floating gate layer 105 is formed. Is thinner toward the bottom.

Referring to FIG. 1C, the antioxidant layer 119 formed on the upper portion of the hard mask pattern 117 and the floating gate layer 105 is removed by an etching process.

During the process of etching the antioxidant layer 119, the floating gate layer 105 may be etched to expose the tunnel insulating layer 103. Since the tunnel insulating film 103 affects the reliability of the semiconductor device, it should be protected as much as possible so as not to be contaminated during the manufacturing process. Accordingly, in order to prevent the tunnel insulating layer 103 from being exposed, an etching material having a large difference in select etch ratio between the floating gate layer 105 and the antioxidant layer 119 is used. In more detail, during the process of etching the antioxidant layer 119, an etching material for etching the antioxidant layer 119 more than the floating gate layer 105 may be used. Considering that the antioxidant film 119 includes a nitride film and the floating gate film 105 includes polysilicon, at least one of CFH ₃ and CH ₂ F ₂ is an etching material for etching the antioxidant film 119. It is preferable to use an etching gas containing one.

In addition, the thickness of the antioxidant film 119 to be etched during the process of etching the antioxidant film 119 is preferably set to 100% to 200% of the thickness when the antioxidant film 119 is formed. When 100% or more, the oxide film 119 formed on the top of the hard mask pattern 117 and the floating gate film 105 is removed, and the antioxidant film 119 formed on the sidewall of the floating gate film 105 is removed. It can be etched. Accordingly, since the sidewall of the floating gate layer 105 is exposed, the width of the floating gate layer 105 may be further reduced in the process of finally patterning the floating gate layer 105 in a subsequent process. The reason for limiting to 200% or less is to prevent the dielectric film 107 from being exposed due to excessive etching of the antioxidant film 119.

Referring to FIG. 1D, the floating gate layer 105 is patterned by etching the exposed floating gate layer 105. As a result, a gate pattern 121 including the floating gate layer 105, the dielectric layer 107, and the control gate layer 114 separated by patterns is formed.

The etching process of the floating gate layer 105 may be stopped at the tunnel insulating layer 103 to prevent the semiconductor substrate 101 from being exposed and damaged. To this end, an etching material having a large difference in select etch ratio between the floating gate layer 105 and the tunnel insulating layer 103 may be used during the etching process of the floating gate layer 105. In more detail, during the process of etching the floating gate layer 105, an etching material for etching the floating gate layer 105 more than the tunnel insulating layer 103 may be used. When the floating gate layer 105 includes polysilicon and the tunnel insulating layer 103 includes an oxide layer, a mixture including HBr and O ₂ as an etching material for etching the floating gate layer 105 is included. It is preferable to use a gas.

The junction region 101a may be formed in the semiconductor substrate 101 on both sides of the gate pattern 121 by implanting impurity ions into the semiconductor substrate 101 using the gate pattern 121 formed by the above process as a mask.

Referring to FIG. 1E, a re-oxidation process is performed to remove plasma damage and metal contaminants generated in the tunnel insulating layer 103 under the influence of an etching process. In order to remove plasma damage and metal contaminants, the reoxidation process is preferably carried out at a high temperature of 700 ° C to 1000 ° C. In addition, the floating gate layer 105 exposed through the reoxidation process may be oxidized. Due to oxidation of the floating gate layer 105, the coupling ratio between the floating gate layer 105 and the control gate layer 114 may be reduced. In order to prevent this, the reoxidation process is preferably stopped at the time when the sidewall of the floating gate film 105 is oxidized to a thickness of 20 kPa to 30 kPa.

Referring to FIG. 1F, spacers 123 are formed on sidewalls of the gate pattern 121 after the reoxidation process.

The spacer 123 forms an oxide film on the tunnel insulating film 103 including the sidewalls of the gate pattern 121 to fill the gap between the gate patterns 121, and then the oxide film on the junction region 101a formed in the select transistor region. It is formed by performing an etching process such as etch-back to remove it. The gap between the gate patterns 121 of the memory cell region may be filled through the oxide layer when the oxide layer is formed. This is because the interval between the gate patterns 121 in the memory cell region is formed to be smaller than the interval between the gate patterns 121 included in the select transistor region.

Referring to FIG. 1G, an etch stop layer 125 may be further formed on the exposed junction region 101a and on the surface of the spacer 123. The etch stop layer 125 includes a nitride layer and prevents the gate pattern 121 from being exposed during the subsequent etching process for forming the contact hole exposing the junction region 101a. The anti-oxidation layer 119a formed to prevent oxidation of the metal layer 113 may also prevent the gate pattern 121 from being exposed together with the etch stop layer 125. As a result, the present invention can prevent double exposure of the gate pattern 121 when the etch stop layer 125 is introduced, so that a SAC defect in which a contact plug formed inside the contact hole is connected to the gate pattern 121 in a subsequent process is performed. (self align contact fail) can be improved.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1G are cross-sectional views illustrating a method of forming a gate pattern of a semiconductor device in accordance with the present invention.

<Explanation of symbols for main parts of the drawings>

101: semiconductor substrate 101a: junction region

103 tunnel insulating film 105 floating gate film

107 dielectric film 109 capping polysilicon film

111 polysilicon film 113 metal film

114: control gate film 115: SiON film

117: hard mask pattern 119: antioxidant film

121: gate pattern 123: spacer

125: etch stop film

Claims (25)

A floating gate formed on the semiconductor substrate with the tunnel insulating film interposed therebetween; A dielectric film formed on the floating gate; A control gate formed on the dielectric film; And And an anti-oxidation film formed on sidewalls of the control gate and sidewalls of the dielectric film. The method of claim 1, The anti-oxidation film extends to the upper sidewall of the floating gate. The method of claim 2, The oxide layer formed on the upper sidewall of the floating gate is formed thinner toward the bottom. The method of claim 1, The antioxidant film comprises a nitride film. The method of claim 1, The floating gate is a semiconductor device formed in a trapezoidal shape having a narrow upper portion than the lower portion. The method of claim 1, The control gate includes a polysilicon layer and a metal layer stacked on the polysilicon layer. The method of claim 6, The metal film comprises tungsten. The method of claim 1, A spacer formed on the sidewall of the gate pattern including the floating gate, the dielectric layer, the control gate, and the antioxidant layer; And The semiconductor device further comprises an etch stop film formed on the surface of the spacer using a nitride film. Providing a semiconductor substrate having a tunnel insulating film, a floating gate film, and a dielectric film; Forming a control gate layer on the dielectric layer; Patterning the control gate layer to expose the dielectric layer; Patterning the dielectric film to expose the floating gate film; Forming an anti-oxidation film on sidewalls of the patterned control gate film and the dielectric film; And And patterning the floating gate layer to expose the tunnel insulating layer. The method of claim 9, After patterning the floating gate layer, The method of manufacturing a semiconductor device further comprising the step of performing an oxidation process at a temperature of 700 ℃ to 1000 ℃. The method of claim 10, And the oxidation process is performed so that sidewalls of the patterned floating gate are oxidized to a thickness of 20 kPa to 30 kPa. The method of claim 9, And patterning the dielectric layer to expose the floating gate layer to etch the upper portion of the exposed floating gate layer. The method of claim 12, And the floating gate layer remaining under the patterned dielectric layer is formed in a trapezoidal shape having a narrower upper portion than the lower portion. The method of claim 12, And the anti-oxidation film extends to the upper sidewall of the floating gate film. The method of claim 14, And an oxide film formed on the upper sidewall of the floating gate film is formed thinner toward the bottom. The method of claim 9, Forming an oxide film on sidewalls of the patterned control gate layer and the dielectric layer; Forming an anti-oxidation layer on the floating gate layer including sidewalls of the patterned control gate layer and the dielectric layer; And Etching the antioxidant film to remove the antioxidant film formed on the upper surface of the floating gate film. The method of claim 16, And forming an oxide film on the floating gate film including the patterned sidewalls of the control gate film and the dielectric film, wherein the thickness of the antioxidant film is 70 kPa to 100 kPa. The method of claim 16, Etching the antioxidant layer is performed using an etching gas comprising at least one of CFH ₃ and CH ₂ F ₂ . The method of claim 16, Etching the antioxidant film A method of manufacturing a semiconductor device to target the thickness of 100% to 200% of the thickness of the antioxidant film. The method of claim 9, And patterning the floating gate layer to expose the tunnel insulating layer using a mixed gas including HBr and O ₂ . The method of claim 9, The antioxidant film is a manufacturing method of a semiconductor device comprising a nitride film. The method of claim 9, The control gate layer may include a polysilicon layer and a metal layer stacked over the polysilicon layer. The method of claim 22, The metal film is a manufacturing method of a semiconductor device containing tungsten. The method of claim 9, The floating gate layer includes a polysilicon layer. The method of claim 9, After patterning the floating gate layer, Forming a spacer using an oxide layer on sidewalls of a gate pattern including the floating gate layer, the dielectric layer, the control gate layer, and the antioxidant layer; And And forming an etch stop layer on the surface of the spacer by using a nitride film.

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