KR101010837B1 - Manufacturing method of spacer for semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a spacer of a semiconductor device which prevents the semiconductor substrate from being damaged.

The present invention reduces the thickness difference of the deposited film caused by the difference in density of the gate pattern through the etching process to form a spacer. Accordingly, the present invention can provide a semiconductor device having improved reliability by preventing the semiconductor substrate in the cell array region from being excessively etched and damaged when the spacer is formed.

Spacer, loading effect

Description

Manufacturing method of spacer for semiconductor device

The present invention relates to a method of forming a spacer of a semiconductor device, and more particularly, to a method of forming a spacer of a semiconductor device which prevents the semiconductor substrate from being damaged.

The semiconductor device is divided into a cell array region in which memory cells storing data and a peripheral region in which circuits for applying driving signals to memory cells are formed.

A plurality of string structures are formed in the cell array region. Each string structure includes a source select transistor, a drain select transistor, and a plurality of memory cells connected in series between the source select transistor and the drain select transistor.

The peripheral area includes a high voltage NMOS transistor (hereinafter referred to as "HVN") transistor, a low voltage NMOS transistor (hereinafter referred to as "LVN") transistor, and a low voltage PMOS (hereinafter referred to as "LVP"). A transistor).

Such a semiconductor device includes a gate pattern constituting each transistor and a cell, a junction region formed on a semiconductor substrate on both sides of the gate pattern, an interlayer insulating film formed on the semiconductor substrate, and metal wirings formed on the interlayer insulating film. The metal wires formed on the interlayer insulating film are electrically connected to the memory cell and the transistor by a contact plug electrically connected to the junction region through the interlayer insulating film.

The contact plug is formed in the contact hole exposing the junction region through the interlayer insulation layer after forming the interlayer insulation layer on the semiconductor substrate on which the gate pattern and the junction region are formed. However, as semiconductor devices become more highly integrated, it becomes difficult to secure a space for forming contact holes as the gate patterns are closer to each other, resulting in device defects in which contact holes expose the gate patterns and contact plugs are connected to the gate patterns. In order to solve this problem, a method of forming a spacer on the sidewall of the gate pattern and preventing the gate pattern from being exposed through the contact hole has been proposed.

The spacer is formed by forming a sealing film and a spacer film on a semiconductor substrate on which a gate pattern and a junction region are formed, and then etching the sealing film and the spacer film by an etch back process or the like. In general, the film deposited on the semiconductor substrate on which the gate pattern is formed is formed to have a different thickness because the density of the gate pattern is different for each region of the semiconductor substrate. In more detail, the spacing between the gate patterns of the cell array region is smaller than the spacing between the gate patterns of the peripheral region. As a result, a loading effect occurs in which a film deposited on the semiconductor substrate on which the gate pattern is formed is thicker in the peripheral region than in the cell array region.

Due to the loading effect, the semiconductor substrate of the cell array region is exposed before the peripheral region and excessively etched in the process of removing the sealing film and the spacer layer formed on the semiconductor substrate of the peripheral region during the etching process for forming the above-described spacer. Problem occurs. When the semiconductor substrate in the cell array region is excessively etched, the resistance of the junction region formed in the cell array region is increased, which causes a failure of the semiconductor device.

The present invention provides a method for forming a spacer of a semiconductor device which prevents the semiconductor substrate from being damaged.

According to an embodiment of the present disclosure, a method of forming a spacer of a semiconductor device may include providing a semiconductor substrate including a first region having first gate patterns and a second region having second gate patterns that are denser than the first gate patterns. Forming a deposition film on the semiconductor substrate on which the first and second gate patterns are formed, etching the upper portion of the deposition film in the first region so as to reduce the difference in thickness of the deposition film in the first and second regions, and depositing the deposition film in the second region And simultaneously etching the deposition film remaining in the first region to form a spacer on sidewalls of the first and second gate patterns.

The vapor deposition film includes a spacer film.

The spacer film includes an LP-TEOS film.

The first and second gate patterns may include a tungsten layer, and the deposition layer may further include a sealing layer formed under the spacer layer.

The sealing film includes an MS-HTO film.

The sealing film and the spacer film are each formed in different deposition equipment, and the sealing film is formed under a higher pressure condition than the spacer film.

In the etching of the upper portion of the deposition layer of the first region, a photoresist pattern that opens the first region and covers the second region is used as an etching mask.

The etching of the upper portion of the deposition layer in the first region may be performed so that the thickness difference between the deposition layers in the first and second regions is less than or equal to 100 μs.

In the step of etching the upper portion of the deposited film of the first region, the deposited film is etched to a thickness of 100 ~ 300Å.

After forming the spacer, the method may further include forming a first junction region in the semiconductor substrate on both sides of the first gate patterns.

After providing the semiconductor substrate on which the first and second gate patterns are formed, the method may further include forming a second junction region in the semiconductor substrate on both sides of the second gate patterns.

The present invention reduces the thickness difference of the deposited film caused by the density difference of the gate pattern through an etching process, and then forms a spacer. Accordingly, the present invention can provide a semiconductor device having improved reliability by preventing the semiconductor substrate in the cell array region from being excessively etched and damaged when the spacer is formed.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1A through 1D are cross-sectional views illustrating a method of forming a spacer of a semiconductor device in accordance with an embodiment of the present invention. A semiconductor device according to an embodiment of the inventive concept is divided into a cell array region in which memory cells storing data and a peripheral region in which circuits for applying driving signals to memory cells are formed.

Referring to FIG. 1A, gate patterns 121 are formed on a semiconductor substrate 101 on which a gate insulating layer 105 is formed. For example, the gate pattern 121 may include the first conductive layer 107, the dielectric layer 109, the second conductive layer 111, the third conductive layer 113, the capping layer 117, and the hard layer. The mask pattern 119 may be stacked.

The first conductive film 107 is a floating gate film and may be formed using polysilicon.

The dielectric film 109 includes a first oxide film, a nitride film, and a second oxide film. The first conductive layer 107 is exposed to the dielectric layer 109 formed in the region where the select lines SSL and DSL of the transistor are to be formed in the cell array region and the region where the gate line GL of the transistor is to be formed in the peripheral region. Grooves are formed.

The second conductive layer 111 may be formed using polysilicon as the control gate layer 115. In the regions where the select lines SSL and DSL of the cell array region and the gate lines GL of the peripheral region are to be formed, the second conductive layer 111 is formed through the grooves formed in the dielectric layer 109. Is electrically connected to the

The third conductive layer 113 is a control gate layer 115 added to lower the resistance, and preferably includes tungsten (W) having a low specific resistance.

The capping film 117 is formed to prevent a phenomenon in which the third conductive film 113 including tungsten is oxidized. In more detail, the third conductive film 113 may be oxidized under the influence of an oxide film deposition process for forming a hard mask film. The oxidized portion of the third conductive film 113 may be lost in a subsequent cleaning process or the like. The capping film 117 is formed to prevent the loss of the third conductive film 113.

The hard mask pattern 119 is a pattern defining a region in which the gate pattern 121 is to be formed. The hard mask pattern 119 is formed by forming a hard mask film formed of any one of a PEOX film (Plasma Enhanced Oxidation) or a TEOS (Tetra Ethyl Ortho Silicate) oxide film on the capping film 117, and then patterning the hard mask film.

The gate pattern 121 formed in the cell array region includes a plurality of word lines WL and a source select line SSL and a drain select line formed in parallel with the word lines WL with the plurality of word lines WL interposed therebetween. (DSL). The gate pattern 121 formed in the peripheral area includes gate lines GL of each of the NMOS transistors and the PMOS transistors constituting the circuit unit. In this case, the gate pattern 121 is formed at a higher density in the cell array region than in the peripheral region. After the gate pattern 121 is formed, a selective oxidation process or a reoxidation process is performed to remove damage occurring to the gate pattern 121 during the etching process for forming the gate pattern 121.

Thereafter, an ion implantation process is performed on the semiconductor substrate 101 on both sides of the gate pattern 121 of the cell array region to form the cell junction region 103. The cell junction region 103 may be formed by opening a cell array region and implanting ions into the photoresist pattern covering the peripheral region and the gate pattern 121 of the cell array region with a mask.

Referring to FIG. 1B, a sealing film 123 and a spacer film 125 are formed on the semiconductor substrate 101 on which the gate pattern 121 is formed.

The sealing film 123 is to improve the charge loss caused by the tungsten contamination generated by introducing the third conductive film 113 including tungsten, and is formed of monosilane-high temperature oxide (MS-HTO). It is preferable to be. The sealing film 123 may be formed to have a thin thickness to minimize the width of the spacers remaining on the sidewalls of the gate pattern 121 in a subsequent process. For this purpose, the sealing film 123 is preferably formed to a thickness thinner than the spacer film 125 that remains on the sidewall of the gate pattern 121 to serve as a substantially spacer. Such a sealing film 125 is formed in a single deposition equipment and is formed under a higher pressure condition than the spacer film 125. As a result, the average pressure applied to the entire surface of the semiconductor substrate 101 when the sealing film 125 is formed is more uneven than when the spacer film 125 is formed. As a result, the loading effect by the sealing film 125 is larger than that of the spacer film 124. In more detail, the sealing film 123 has a greater thickness difference in the peripheral region having a lower density of the gate pattern 121 and the cell array region having a relatively higher density than the spacer layer 125. As a result, the total thicknesses of the sealing film 123 and the spacer film 125 are formed as the first thickness h1 in the cell array region and the second thickness h2 thicker than the first thickness h1 in the peripheral region.

The spacer film 125 is formed in the sealing film 123 and other deposition equipment, and in a subsequent process, contacts between the source select line SSL, the drain select line DSL, or the gate line GL in the peripheral region. When forming the hole, the gate pattern 121 is formed to prevent exposure. In this case, the spacer layer 125 is formed of a low-pressure tetra-ethyl-ortho-silicate (LP-TEOS) film to seal the gate pattern 121 formed on the semiconductor substrate 101 at different densities for each region. It may be formed to have a uniform thickness than the film 123.

Referring to FIG. 1C, a photoresist pattern 127 covering a cell array region and opening a peripheral region to reduce the thickness difference between the sealing layer 123 and the spacer layer 125 in the cell array region and the peripheral region described above. To form. The second layer h2 is reduced by etching the spacer layer 125 formed in the peripheral area using the photoresist pattern 127 as a mask. The etching process of the spacer layer 125 may be performed until the difference between the first thickness h1 and the second thickness h2 is 100 kΩ or less. To this end, the spacer film 125 formed in the peripheral region is preferably etched by a thickness of 100 Å to 300 Å. After the spacer layer 125 formed in the peripheral region is etched, the thickness of the spacer layer 125 formed in the peripheral region becomes thinner than the thickness of the spacer layer 125 formed in the cell array region, but the density of the gate pattern 121 is increased. The loading effect by the car can be compensated for.

Thereafter, the remaining photoresist pattern 127 is removed by a strip process.

Referring to FIG. 1D, the sealing film and the spacer film are etched by an etch back process to leave the spacer 129 including the sealing pattern 123a and the spacer pattern 125a on the sidewall of the gate pattern 121. The etching of the sealing film and the spacer film is performed using an etching gas in which CFx, CHFy, Ar, and O ₂ gas are mixed. In this case, the gate insulating layer 103 between the spacers 129 may be removed to expose the semiconductor substrate 101. During the etching process for forming the spacer 129, the uniformity of the final thicknesses of the sealing film and the spacer film is improved in the cell array region and the peripheral region as described above with reference to FIG. 1C, thereby improving the problem of damaging the semiconductor substrate 101. can do.

After the spacer 129 is formed, an ion implantation process is performed using a photoresist pattern covering the cell array region and opening the peripheral region using a mask to peripherally bond the semiconductor substrate 101 on both sides of the gate pattern 121 formed in the peripheral region. The region 131 may be formed.

In the above, a case of improving the loading effect of the sealing film 123 and the spacer film 123 has been described as an example. However, in the present invention, when only the spacer film 125 is formed without the sealing film 123 forming process, the spacer film ( 125 may also be applied to improve the loading effect. Furthermore, the present invention provides a first region (eg, a peripheral region) in which first gate patterns (eg, a GL of a circuit transistor) is formed, and second gate patterns (eg, more densely than the first region). For example, it is possible to improve loading effects of various deposition films formed on a semiconductor substrate including a second region (eg, a cell array region) in which SSL, DSL, and WL are formed.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A through 1D are cross-sectional views illustrating a method of forming a spacer of a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101 semiconductor substrate 103 cell junction region

105: gate insulating film 107: first conductive film

109 dielectric film 111 second conductive film

113: third conductive film 115: control gate film

117: capping film 119: hard mask pattern

121: gate pattern 123: sealing film

125 spacer film 127 photoresist pattern

129: spacer 131: peripheral junction area

Claims (11)

Providing a semiconductor substrate including a first region in which first gate patterns are formed and a second region in which second gate patterns are denser than the first gate patterns; Forming a deposition film on the semiconductor substrate on which the first and second gate patterns are formed; Etching an upper portion of the deposited film in the first region so that a difference in thickness of the deposited film is reduced in the first and second regions; And Forming a spacer on sidewalls of the first and second gate patterns by simultaneously etching the deposition film in the second region and the deposition film remaining in the first region. The method of claim 1, The deposition film is a spacer forming method of a semiconductor device comprising a spacer film. The method of claim 2, The spacer layer is a spacer forming method of a semiconductor device comprising an LP-TEOS film. The method of claim 2, The first and second gate patterns include a tungsten film, The deposition layer further comprises a sealing film formed under the spacer film. The method of claim 4, wherein The sealing film is a spacer forming method of a semiconductor device comprising an MS-HTO film. The method of claim 4, wherein The sealing film and the spacer film are each formed in different deposition equipment, The sealing film is a spacer forming method of a semiconductor device is formed under a higher pressure than the spacer film. The method of claim 1, Etching the upper portion of the deposition layer in the first region A method of forming a spacer in a semiconductor device using the photoresist pattern opening the first region and covering the second region as an etching mask. The method of claim 1, Etching the upper portion of the deposition layer in the first region is performed such that a thickness difference between the deposition layer in the first and second regions is 100 占 퐉 or less. The method of claim 1, And etching the upper portion of the deposition layer in the first region, wherein the deposition layer is etched to a thickness of about 100 mW to about 300 mW. The method of claim 1, After forming the spacer, Forming a first junction region in the semiconductor substrate on both sides of the first gate patterns. The method of claim 1, After the step of providing a semiconductor substrate on which the first and second gate patterns are formed, Forming a second junction region in the semiconductor substrate on both sides of the second gate patterns.

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