KR100440081B1 - A method for forming a conductive line of a semiconductor device - Google Patents
A method for forming a conductive line of a semiconductor device Download PDFInfo
- Publication number
- KR100440081B1 KR100440081B1 KR10-1999-0063607A KR19990063607A KR100440081B1 KR 100440081 B1 KR100440081 B1 KR 100440081B1 KR 19990063607 A KR19990063607 A KR 19990063607A KR 100440081 B1 KR100440081 B1 KR 100440081B1
- Authority
- KR
- South Korea
- Prior art keywords
- interlayer insulating
- insulating film
- photoresist pattern
- silicon
- semiconductor device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000010410 layer Substances 0.000 claims abstract description 38
- 239000011229 interlayer Substances 0.000 claims abstract description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 20
- 239000007789 gas Substances 0.000 claims description 11
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 4
- 229910001882 dioxygen Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 도전배선 형성방법에 관한 것으로,The present invention relates to a method for forming a conductive wiring of a semiconductor device,
제1도전배선 상부에 유기 저유전층으로 층간절연막을 형성하고 상기 층간절연막 상부에 실리콘 함유 감광막패턴을 형성한 다음, 상기 실리콘 함유 감광막패턴을 마스크로하여 상기 층간절연막을 식각하여 패터닝하되, 산소가스와 질소가스를 이용한 플라즈마로 실시하여 상기 감광막패턴 상측에 실리콘산화막이 형성되고 상기 실리콘산화막 및 감광막패턴을 제거하는 공정으로 공정을 단순화하여 반도체소자의 생산성을 향상시키는 기술이다.An interlayer insulating film is formed on the first conductive wiring using an organic low dielectric layer, and a silicon-containing photosensitive film pattern is formed on the interlayer insulating film. Then, the interlayer insulating film is etched and patterned using the silicon-containing photosensitive film pattern as a mask. It is a technique for improving the productivity of the semiconductor device by simplifying the process by the process of removing the silicon oxide film and the photoresist pattern by forming a silicon oxide film on the photoresist pattern by performing plasma using nitrogen gas.
Description
본 발명은 반도체소자의 도전배선 형성방법에 관한 것으로, 특히 유기 저유전층 ( organic low-k layer ) 을 층간절연막으로 이용하고 별도의 마스크절연막없이 실리콘이 함유된 감광막을 이용한 식각공정으로 공정을 단순화시켜 반도체소자의 생산성을 향상시키는 기술에 관한 것이다.The present invention relates to a method of forming a conductive wiring of a semiconductor device, and in particular, by using an organic low-k layer as an interlayer insulating film and simplifying the process by etching using a photosensitive film containing silicon without a separate mask insulating film. The present invention relates to a technique for improving the productivity of a semiconductor device.
일반적으로, 반도체소자는 다수의 도전층이 구비되고, 상기 도전층 간의 절연특성을 향상시키기 위하여 층간절연막을 형성하였다.In general, a semiconductor device includes a plurality of conductive layers, and an interlayer insulating film is formed in order to improve insulating properties between the conductive layers.
이때, 상기 층간절연막은 플로우 ( flow ) 가 잘되는 절연물질, 산화막을 이용하여 형성하였다.In this case, the interlayer insulating film is formed using an insulating material and an oxide film having a good flow.
그러나, 반도체소자의 알.씨. 딜레이 ( RC delay ) 효과로 인하여 반도체소자의 특성이 열화되는 단점이 있다.However, R. of the semiconductor device. Due to the delay (RC delay) effect, the characteristics of the semiconductor device is deteriorated.
최근에는 RC 딜레이를 최소화시키기 위하여 층간절연막으로 유기 저유전층 ( inorganic low-k ) 을 사용하였다.Recently, an organic low dielectric layer (inorganic low-k) has been used as an interlayer dielectric to minimize the RC delay.
도 1 은 종래기술에 따른 반도체소자의 도전배선 형성방법을 도시한 단면도로서, 유기 저유전층을 층간절연막으로 사용하는 방법으로 금속배선을 형성하는 공정을 도시한다.1 is a cross-sectional view illustrating a method of forming conductive wirings of a semiconductor device according to the prior art, and illustrates a process of forming metal wirings by using an organic low dielectric layer as an interlayer insulating film.
먼저, 제1금속배선(11) 상부에 층간절연막(13)을 형성한다. 이때, 상기 층간절연막(13)은 유기 저유전층으로 형성한다.First, an interlayer insulating film 13 is formed on the first metal wiring 11. In this case, the interlayer insulating layer 13 is formed of an organic low dielectric layer.
여기서, 상기 유기 저유전층(13)은 폴리머의 형태를 가지며 산화막보다 낮은 유전율을 갖는 물질로서, 반도체 제조공정을 진행할 수 있는 높은 온도에서도 견딜 수 있으며 산화막과 높은 친밀성을 가지고, 열적 안정성이 우수하다. 그리고, 그 예로는 플레어 ( flare ) 와 실크 ( silk ) 와 같은 상품명을 갖는 물질이 있으며, 산화막이나 질화막보다 식각이 잘되는 식각특성을 갖는다.Here, the organic low dielectric layer 13 is a material having a polymer form and having a lower dielectric constant than the oxide film, and may withstand high temperatures at which the semiconductor manufacturing process can be performed, have high affinity with the oxide film, and have excellent thermal stability. . In addition, examples thereof include materials having trade names such as flare and silk, and have better etching characteristics than oxide or nitride layers.
그 다음, 상기 층간절연막(13) 상부에 마스크산화막(15)을 일정두께 형성한다.Next, a mask oxide film 15 is formed on the interlayer insulating film 13 at a predetermined thickness.
그 다음, 상기 마스크산화막(15) 및 층간절연막(13)을 식각하여 상기 반도체기판(11)을 노출시키는 콘택홀(17)을 형성한다.Next, the mask oxide layer 15 and the interlayer dielectric layer 13 are etched to form a contact hole 17 exposing the semiconductor substrate 11.
이때, 상기 식각공정은 비아콘택마스크(도시안됨)를 이용한 사진식각공정으로 실시한 것이다. (도 1)In this case, the etching process is performed by a photolithography process using a via contact mask (not shown). (Figure 1)
상기한 바와같이 종래기술에 따른 반도체소자의 도전배선 형성방법은, 비아콘택공정시 식각장벽으로 사용하는 마스크산화막을 별도의 증착공정으로 형성하여 반도체소자의 제조공정을 복잡하게 하는 문제점이 있다.As described above, the method of forming a conductive wiring of a semiconductor device according to the related art has a problem of complicated manufacturing process of a semiconductor device by forming a mask oxide film used as an etching barrier in a via contact process by a separate deposition process.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 실리콘이 함유된 감광막을 이용하여 콘택 식각공정을 실시함으로써 식각장벽층인 마스크절연막의 형성공정이 불필요하게 되어 반도체소자의 공정을 단순화시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 도전배선 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the process of forming a mask insulating film as an etch barrier layer is unnecessary by performing a contact etching process using a photoresist film containing silicon, thereby simplifying the process of a semiconductor device. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming conductive wirings of a semiconductor device capable of improving the characteristics and reliability of the semiconductor device.
도 1 는 종래기술에 따른 반도체소자의 도전배선 형성방법을 도시한 단면도.1 is a cross-sectional view showing a method for forming a conductive wiring of a semiconductor device according to the prior art.
도 2a 내지 도 2c 는 본 발명의 실시예에 따른 반도체소자의 도전배선 형성방법을 도시한 단면도.2A to 2C are cross-sectional views illustrating a method of forming conductive wirings in a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,21 : 제1금속배선 13,23 : 층간절연막11,21 first metal wiring 13,23 interlayer insulating film
15 : 마스크절연막 17,29 : 콘택홀15 mask insulating film 17,29 contact hole
25 : 감광막패턴 27 : 실리콘산화막25 photosensitive film pattern 27 silicon oxide film
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 도전배선 형성방법은,제1도전배선 상부에 유기 저유전층으로 층간절연막을 형성하는 공정과,상기 층간절연막 상부에 실리콘 함유 감광막패턴을 형성하는 공정과,상기 실리콘 함유 감광막패턴을 마스크로 하여 산소/질소 가스를 이용한 플라즈마식각공정으로 상기 층간절연막을 식각하되, 상기 층간절연막의 식각공정시 실리콘이나 수소가 함유된 가스를 이용하는 공정과,상기 층간절연막 식각공정시 상기 감광막패턴 상부에 형성된 실리콘산화막과 감광막패턴을 제거하는 공정을 포함하는 것을 특징으로한다.In order to achieve the above object, a method of forming a conductive wiring of a semiconductor device according to the present invention includes: forming an interlayer insulating film as an organic low dielectric layer on an upper portion of a first conductive wiring; and forming a silicon-containing photosensitive film pattern on the interlayer insulating film. And etching the interlayer insulating film by a plasma etching process using oxygen / nitrogen gas using the silicon-containing photoresist pattern as a mask, and using a gas containing silicon or hydrogen during the etching process of the interlayer insulating film, and the interlayer insulating film And removing the silicon oxide film and the photoresist pattern formed on the photoresist pattern during the etching process.
이하, 첨부된 도면을 참고로 하여 본 발명은 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c 는 본 발명의 실시예에 따른 반도체소자의 도전배선 형성방법을 도시한 단면도로서, 도전배선의 일종인 금속배선을 형성하는 공정을 예로 하여 도시한 것이다.2A to 2C are cross-sectional views illustrating a method of forming conductive wirings of a semiconductor device according to an exemplary embodiment of the present invention, and illustrating a process of forming a metal wiring, which is a kind of conductive wiring, as an example.
먼저, 반도체기판(도시안됨) 상에 활성영역을 정의하는 소자분리막(도시안됨)을 형성하고, 워드라인(도시안됨), 비트라인 및 캐패시터를 형성하고 그 상부를 평탄화시키는 하부절연층(도시안됨)을 형성한다.First, an isolation layer (not shown) defining an active region is formed on a semiconductor substrate (not shown), and a lower insulating layer (not shown) is formed to form word lines (not shown), bit lines, and capacitors and planarize an upper portion thereof. ).
그리고, 상기 반도체기판에 접속되는 제1금속배선(21)을 형성한다.Then, the first metal wiring 21 connected to the semiconductor substrate is formed.
그리고, 제1금속배선(21) 표면 상부를 평탄화시키는 층간절연막(23)을 형성한다.An interlayer insulating film 23 is formed to planarize the upper surface of the first metal wiring 21.
이때, 상기 층간절연막(23)은 유기 저유전층으로 형성하고 이를 베이킹 및 큐어링한다.In this case, the interlayer insulating layer 23 is formed of an organic low dielectric layer and baked and cured.
여기서, 상기 유기 저유전층은 폴리머의 형태를 가지며 산화막보다 낮은 유전율을 갖는 물질로서, 반도체 제조공정을 진행할 수 있는 높은 온도에서도 견딜 수 있으며 산화막과 높은 친밀성을 가지고, 열적 안정성이 우수하다. 그리고, 그 예로는 플레어 ( flare ) 와 실크 ( silk ) 와 같은 상품명을 갖는 물질이 있으며, 산화막이나 질화막보다 식각이 잘되는 식각특성을 갖는다.Here, the organic low dielectric layer is a material having a polymer form and having a lower dielectric constant than that of the oxide film. The organic low dielectric layer can withstand the high temperature at which the semiconductor manufacturing process can proceed, has high affinity with the oxide film, and has excellent thermal stability. In addition, examples thereof include materials having trade names such as flare and silk, and have better etching characteristics than oxide or nitride layers.
그 다음, 상기 층간절연막(23) 상부에 감광막패턴(25)을 형성한다.Next, a photosensitive film pattern 25 is formed on the interlayer insulating film 23.
이때, 상기 감광막패턴(25)은 실리콘 함유 감광막을 도포하고 이를 비아콘택마스크를 이용하여 노광 및 현상하여 형성한 것이다. (도 2a)In this case, the photoresist pattern 25 is formed by coating a silicon-containing photoresist and exposing and developing the photoresist using a via contact mask. (FIG. 2A)
그 다음, 감광막패턴(25)을 마스크로하여 상기 층간절연막(13)을 식각하여 상기 제1금속배선(21)을 노출시키는 비아콘택홀(29)을 형성한다.Next, the interlayer insulating layer 13 is etched using the photoresist pattern 25 as a mask to form a via contact hole 29 exposing the first metal wiring 21.
이때, 상기 식각공정은 산소가스와 질소가스를 이용하여 플라즈마 식각한다.In this case, the etching process is plasma-etched using oxygen gas and nitrogen gas.
그리고, 상기 플라즈마 식각공정으로 인하여 상기 감광막패턴(25)의 상측이 산화되어 실리콘산화막(27)이 형성되고 상기 실리콘산화막(27)이 식각장벽으로 사용됨으로써 별도의 마스크절연막이 불필요하게 된다.The upper surface of the photoresist pattern 25 is oxidized by the plasma etching process to form a silicon oxide layer 27, and the silicon oxide layer 27 is used as an etch barrier so that a separate mask insulating layer is unnecessary.
그리고, 상기 층간절연막(23)인 유기 저유전층의 식각공정은 언더컷 유발 방지를 위하여 실리콘이나 수소가 함유된 SO2, H2O2, C2H4및 이들의 조합으로 이루어지는 군으로부터 선택된 어느 하나의 가스를 이용하여 실시한다. (도 2b)The etching process of the organic low-k dielectric layer, which is the interlayer insulating layer 23, is any one selected from the group consisting of SO 2 , H 2 O 2 , C 2 H 4, and combinations thereof containing silicon or hydrogen to prevent undercut. It is carried out using gas. (FIG. 2B)
그리고, 상기 층간절연막(23) 식각공정시 유발되는 폴리머는 일반적인 화학 용액으로 제거하되, 상기 감광막패턴(25)과 그 상측에 형성된 실리콘산화막(27)을 동시에 제거한다.The polymer caused during the interlayer insulating layer 23 etching process is removed with a general chemical solution, and the photoresist pattern 25 and the silicon oxide layer 27 formed on the upper side are simultaneously removed.
한편, 상기 실리콘산화막(27)은 C2F6, C3F8, C4F8, C5F8및 C4F6를 포함하는 군으로부터 선택된 C-F 계 가스 플라즈마를 이용한 식각공정으로 제거할 수도 있다.Meanwhile, the silicon oxide layer 27 may be removed by an etching process using a CF-based gas plasma selected from the group consisting of C 2 F 6 , C 3 F 8 , C 4 F 8 , C 5 F 8, and C 4 F 6 . It may be.
그리고, 상기 플라즈마 식각공정은, C-F 계 가스의 식각선택비 차이를 증가시키기 위하여 상기 CH2F2, C2HF5및 C3H2F6를 포함하는 군으로 부터 선택된 C-H-F 계 가스를 이용하여 첨가하여 상기 층간절연막(23)을 식각할 수도 있다.The plasma etching process may be performed by using a CHF-based gas selected from the group including CH 2 F 2 , C 2 HF 5 and C 3 H 2 F 6 to increase the difference in etching selectivity of CF-based gas. In addition, the interlayer insulating layer 23 may be etched.
또한, 상기 실리콘산화막(27)을 먼저 제거하고 후속공정으로 상기 감광막패턴(25)을 제거할 수도 있다. (도 2c)In addition, the silicon oxide layer 27 may be removed first, and the photoresist layer pattern 25 may be removed in a subsequent process. (FIG. 2C)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 도전배선 형성방법은, 층간절연막 상부에 마스크절연막을 형성하는 대신 실리콘이 함유된 감광막패턴을 형성하고 이를 이용하여 식각공정을 실시함으로써 공정을 단순화시켜 반도체소자의 생산성을 향상시키는 효과를 제공한다.As described above, in the method of forming conductive wirings of the semiconductor device according to the present invention, instead of forming a mask insulating film on the interlayer insulating film, a photosensitive film pattern containing silicon is formed and an etching process is used to simplify the process. It provides the effect of improving the productivity of the device.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0063607A KR100440081B1 (en) | 1999-12-28 | 1999-12-28 | A method for forming a conductive line of a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0063607A KR100440081B1 (en) | 1999-12-28 | 1999-12-28 | A method for forming a conductive line of a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010061121A KR20010061121A (en) | 2001-07-07 |
| KR100440081B1 true KR100440081B1 (en) | 2004-07-15 |
Family
ID=19630930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-1999-0063607A KR100440081B1 (en) | 1999-12-28 | 1999-12-28 | A method for forming a conductive line of a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100440081B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100780594B1 (en) * | 2001-11-19 | 2007-11-29 | 주식회사 하이닉스반도체 | Method of dry etching in semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04155816A (en) * | 1990-10-19 | 1992-05-28 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| KR970018101A (en) * | 1995-09-21 | 1997-04-30 | 김광호 | Small contact hole formation method using photoresist |
| KR970052946A (en) * | 1995-12-26 | 1997-07-29 | 김주용 | Metal wiring method of semiconductor device |
| JPH10289952A (en) * | 1997-04-16 | 1998-10-27 | Sony Corp | Method of manufacturing semiconductor device |
-
1999
- 1999-12-28 KR KR10-1999-0063607A patent/KR100440081B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04155816A (en) * | 1990-10-19 | 1992-05-28 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| KR970018101A (en) * | 1995-09-21 | 1997-04-30 | 김광호 | Small contact hole formation method using photoresist |
| KR970052946A (en) * | 1995-12-26 | 1997-07-29 | 김주용 | Metal wiring method of semiconductor device |
| JPH10289952A (en) * | 1997-04-16 | 1998-10-27 | Sony Corp | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010061121A (en) | 2001-07-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6444557B1 (en) | Method of forming a damascene structure using a sacrificial conductive layer | |
| US20070134917A1 (en) | Partial-via-first dual-damascene process with tri-layer resist approach | |
| US20030219988A1 (en) | Ashable layers for reducing critical dimensions of integrated circuit features | |
| US6589880B2 (en) | Fine pattern formation method and semiconductor device or liquid crystal device manufacturing method employing this method | |
| US20010016405A1 (en) | Unique via patterning scheme which utilizes hard mask cap for low dielectric constant materials | |
| US6878637B2 (en) | Method for fabricating semiconductor device capable of improving process margin of self align contact | |
| US20010023990A1 (en) | Semiconductor device and method for fabricating same | |
| KR100440081B1 (en) | A method for forming a conductive line of a semiconductor device | |
| KR100400300B1 (en) | Forming method for metal line of semiconductor device | |
| KR100436288B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100909174B1 (en) | How to form a dual damascene pattern | |
| KR100964116B1 (en) | Method for fabricating of semiconductor device | |
| US6284645B1 (en) | Controlling improvement of critical dimension of dual damasceue process using spin-on-glass process | |
| KR100248142B1 (en) | Method of fabricating semiconductor device | |
| KR100306374B1 (en) | Method for forming contact hole in semiconductor device | |
| KR101024871B1 (en) | Method of forming a dual damascene pattern | |
| KR100917099B1 (en) | Method of forming a dual damascene pattern | |
| KR100366612B1 (en) | Method for manufacturing semiconductor device having flat field isolation layer | |
| KR100290466B1 (en) | Method of manufacturing a semiconductor device | |
| KR100468694B1 (en) | Method for forming contact for semiconductor device | |
| KR100443515B1 (en) | method for manufacturing via hole | |
| JPH11176935A (en) | Manufacture of semiconductor device | |
| JPH05206083A (en) | Production of semiconductor device | |
| KR20010059538A (en) | Method for forming metal line in semiconductor device | |
| KR20060038597A (en) | Method for forming pattern of semicondutor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100624 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |