JPS6324622A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a wiring life, increase the yield of a semiconductor device product, and improve its quality and reliability, by covering the surface with an insulating layer containing no material to increase the dry etching speed of a conductive layer. CONSTITUTION:On a semiconductor substrate 1 on the surface of which a diffusion region 2 is formed, an oxide film 3 is arranged which has a contact window 3 on the region 2, and one wiring 4a connected to the region 2 via the contact window and the other wiring 4b are arranged on the oxide film 3. Further, a contact window is made on the wiring 4b, a nitride film 5 the surface of which is covered with an oxide film 6 is formed and, on the oxide film 6, a wiring 7a and a wiring 7b connected to the wiring 4b via a contact window are arranged. Thus a multilayer interconnection structure is constituted. Accordingly, the surface of the nitride film 5 under the wirings 7a and 7b is covered with the oxide film 6, so that the nitrogen gas to accelerate a reaction at the time of dry eyching process does not generate, and the undercut of the wirings 7a and 7b does not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a plurality of conductor layers stacked with insulating layers interposed therebetween.

[Conventional technology]

Recently, as the demand for higher speeds and higher densities of semiconductor devices has become stronger, technology for forming devices with fine patterns and multilayer wiring structures has become increasingly important in order to realize these demands.

In particular, in order to form internal circuits and constituent elements with fine patterns that must meet minute processing dimensional accuracy, butterning is usually performed using a parallel plate type dry etching device, so that the etched portions are The cross-sectional shape of the edge must be steep.

Therefore, in semiconductor devices in which fine patterned internal circuits and constituent elements are connected by a multilayer wiring structure, breaks in the wiring are likely to occur where the wiring crosses a step with a steep edge cross-section. This tendency becomes very strong when the width of the wiring is narrow and extremely thin. This significantly reduces the product yield of semiconductor devices and seriously affects quality and reliability.

In conventional semiconductor devices, in order to prevent such disconnections in wiring, plasma nitride film formation technology using low pressure vapor phase growth is used to coat the surface of steep step portions at a low temperature that does not melt the wiring metal. A 1-lagma nitride film has been deposited to smooth the cross-sectional shape, and a plasma nitride film has been used as an insulating film between the eyebrows of multilayer wiring.

FIG. 3 is a sectional view of an example of a conventional semiconductor device.

In this example, a wiring 4' is provided on a semiconductor substrate 1' via an oxide film 3', a plasma nitride film 5' is provided to smooth the steep edges of the wiring 4', and a plasma nitride film 5' is further provided. A wiring 7' is provided above the line 7'.

However, in the dry etching process for metal wiring, a chlorine-based etching gas is generally introduced into a reduced pressure chamber in which a wafer is set, plasma discharge is caused by high-frequency power, and the excited etching gas is applied to the conductors that make up the wiring. It is reacted with the metal of the layer and etched to form a predetermined wiring pattern. Therefore, when the etching of the metal of the semiconductor layer constituting the wiring approaches the end point and the surface of the underlying plasma nitride film begins to appear, the surface of the plasma nitride film is exposed to the etching gas and etched. It becomes like this. As a result, nitrogen gas is generated, which in turn further accelerates the etching of the metal of the conductor layer constituting the wiring, resulting in plasma nitridation [of the wiring 7' on the wiring 5'] as shown in FIG. The lower side is undercut.

[Problem that the invention seeks to solve]

As shown in the conventional example, the above-mentioned conventional semiconductor device uses a substance (in the conventional example, nitrogen) that further accelerates the dry etching of the conductive layer constituting the wiring and increases the etching rate in the insulator between the wiring layers. Therefore, there is a drawback that undesirable abnormal etching such as undercutting causes deterioration of the life of the wiring, disconnection, etc., resulting in a decrease in manufacturing yield and a marked deterioration in quality and reliability.

An object of the present invention is to prevent undercuts caused by accelerated etching during dry etching of the conductor layers constituting the wiring by using a substance contained in the glabella insulating film for insulating the conductor layers constituting the multilayer wiring. The purpose of the present invention is to provide semiconductor devices with high manufacturing yield, quality, and reliability.

[Means for solving problems]

In a semiconductor device according to the present invention, in a semiconductor device having a plurality of conductor layers laminated with insulating layers interposed therebetween, the surface of the insulating layer is dry-etched when the conductor layer on the insulating layer is dry-etched. It is covered with another insulating layer that does not contain any speed-increasing substances.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of an embodiment of the present invention.

This embodiment consists of a semiconductor substrate vi having a diffusion region 2 on its surface.
1, an oxide film 3 with a contact window formed on the diffusion region 2 is provided, a wiring 4a connected to the diffusion region 2 through the contact window and another wiring 4b are provided on the oxide film 3, and further on the wiring 4b. A contact window is opened in the nitride film 6, the surface of which is covered with an oxide film 6. It has a multilayer wiring structure including a wiring 7a and a wiring 7b connected to the wiring 4b through a contact window. In this structure, distribution! Since the surface of the nitride film 5 below i7a and 7b is covered with the oxide film 6, nitrogen gas that accelerates the reaction is not generated during the dry etching process of the wires 7a and 7b, and therefore the wires 7a and 7b are dry-etched.
a and 7b are not undercut.

FIGS. 2(a) to 2(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention.

In this manufacturing method, as shown in FIG. 2(a), first, an oxide film 3 with a contact window is formed on the surface of a semiconductor substrate 1 on which a diffusion region 2 is formed, and then the diffusion region is formed through the contact window. Wiring 4a connected to 2 and other wiring 4b
A plasma nitride film 5 of the glabella insulating film is formed on top of the film with a thickness of about 1 μm and a width of about 2 μm, and is coated smoothly on the edges of the steep steps of the wiring without melting the metal of the wiring. Next, as shown in FIG. 2(b), an oxide film of about 1,000 layers is grown on the plasma nitride film 5 by vapor phase growth at a growth temperature of 400°C. form 6.

Next, as shown in FIG. 2(c), a contact for connecting to the wiring 4b is formed on the plasma nitride film 5 whose surface is covered with an oxide film 6 using ordinary photolithography technology and dry etching technology. Open window 8.

Finally, if a conductor layer is formed by a normal sputtering method and then wirings 7a and 7b are formed by using a normal photolithography technique and a dry etching technique, an embodiment of the present invention as shown in FIG. 1 can be obtained. The example semiconductor chip is made.

In this example, nitrogen is the speed-enhancing substance when etching the conductor layer, but of course the speed-enhancing substance is not limited to nitrogen. For example, oxygen may be increased by changing the material of the conductor layer to be etched, etc. If nitrogen is not a speed-enhancing substance, an oxide film whose surface is covered with a nitride film or a nitride film itself is used as an insulating film between the eyebrows.

〔Effect of the invention〕

As explained above, in the present invention, even if an insulating film contains a substance that increases the etching rate during dry etching of a conductor layer constituting wiring on the insulating film, the material that increases the etching rate on the surface of the insulating film can be removed. By covering the conductor layer with another insulating film that does not contain the etchant, abnormal etching such as undercuts will not occur during dry etching of the conductor layer on top of the conductor layer, thereby preventing deterioration of the life of the wiring and disconnection, etc., and improving the performance of semiconductor devices. This has the effect of improving product yield as well as improving quality and reliability.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an embodiment of the present invention, and FIGS. 2(a) to (
c) is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining the m-embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 3 is a cross-sectional view of an example of a conventional semiconductor device. 1.1'...Semiconductor substrate, 2...Diffusion region, 3゜3
'...Oxide film, 4a, 4b, 4'-wiring, 5°5
'... Plasma nitride film, 6... Oxide film, 7a, 7b
. 7'...Wiring, 8...Contact window. 1st leap '30

Claims (1)

[Claims] In a semiconductor device having a plurality of conductor layers laminated with an insulating layer interposed therebetween, the surface of the insulating layer includes a substance that increases the dry etching rate of the conductor layer when dry etching the conductor layer on the insulating layer. A semiconductor device characterized in that the semiconductor device is covered with no other insulating layer.