JPS6120353A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the disconnection of wiring layers by eliminating stepwise differences by filling the gap between wiring layers with an interlayer insulation film. CONSTITUTION:An Al layer and a photo resist layer 11 are formed on a semiconductor substrate 1, and the first wiring layer 2 is formed by patterning. An SiO2 film 12 as the first interlayer insulation film is formed to a thickness approximately the same as that of the first wiring layer 2. A flat surface consisting of the first wiring layer 2 and the SiO2 film 12 can be obtained by removing the photo resist layer 11. An Si3N4 film 13 is formed as the second interlayer insulation film. This second interlayer insulation film is sufficient if its etching characteristic is different from that of the first interlayer insulation film. Next, a contact aperture 14 is provided in the Si3N4 film 13. Successively, Al is adhered by sputtering and patterned, thus forming the second wiring layer 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming multilayer interconnections.

[Prior art]

2. Description of the Related Art Semiconductor integrated circuits have gradually become larger in capacity and more highly integrated, and along with this, multilayer wiring has been implemented. Multilayering requires forming a plurality of wiring layers via interlayer insulating films, but as processing such as film deposition is performed, steep steps are formed, causing disconnections in the wiring layers. In addition, it is necessary to make contact between the first layer (lower layer) wiring and the second layer (upper layer) wiring by providing a through hole in a desired part of the interlayer insulating film, but in order to deal with problems such as misalignment, contact The part where , was taken as wide direct product. The manufacturing method will be explained below with reference to the drawings.

Figure 1 + al, (bl is a plan view and a cross-sectional view taken along the line A-A' of a contact portion of a semiconductor device having a conventional multilayer wiring. First, A/ is applied to the surface of the semiconductor substrate 1 by sputtering or the like). The first wiring layer 2 is formed by depositing and patterning. Note that although the details of the cross section of the illustrated semiconductor substrate 1 are omitted, the semiconductor substrate 1 referred to here has, for example, circuit elements such as transistors and resistors formed thereon, and its surface is made of Si.
n, a silicon substrate covered with a film, in which predetermined contact holes and the like are provided in the silicon film on the circuit element;

Next, 1) a first interlayer insulator 1[3 made of a SiOx film is formed on the entire surface using a CVD method or the like. Subsequently, a contact opening 4 is formed in the first interlayer insulating film 3 on the wide area portion 2a of the first wiring layer 2, and then A/I sputtering is performed and patterned to form the second wiring layer 5. Form.

In the semiconductor device having multilayer wiring manufactured as above, the step coverage of the second wiring layer formed on the step portion of the first interlayer insulating film 3 is poor (as indicated by the arrow). ), there was a drawback that it caused wire breakage.

Further, the contact portion of the first wiring layer 2 is connected to the wide area portion 2a.
The reason for doing so is as follows. That is, if the mask alignment accuracy is poor and the contact opening 4 is displaced from the first wiring layer 2, the etching process for forming the opening 4 may be performed as shown in FIG. Even the insulation on the underlying semiconductor substrate is etched, which adversely affects the circuit elements, and also causes a disconnection in the second wiring layer 5 due to the deep opening 4a. To avoid this, as shown in Figure #I1,
It is necessary to provide the wide-area portion 2at- on the first wiring layer so that the opening 4 is always provided on the first wiring layer 2 even if there is some positional deviation. However, this requires a margin l for forming the wide area portion 2af, which is a drawback that inevitably impedes an improvement in the degree of integration.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device having multilayer wiring, which eliminates the above-mentioned drawbacks, eliminates disconnections in wiring layers, and improves the degree of integration.

[Structure of the invention]

The method for manufacturing a semiconductor device of the present invention includes the steps of: forming a first wiring layer on a semiconductor substrate on which a circuit element is formed; filling spaces between the first wiring layers with a first interlayer insulating film; A second layer is formed on the entire surface including the first wiring layer and the first interlayer insulating film.
The method includes a step of forming an interlayer insulating film, and a step of forming a second wiring layer on the second interlayer insulating film.

[Explanation of Examples]

Next, an embodiment of the present invention will be described with reference to the drawings. Figures 3a-3d are cross-sectional views of a process for explaining an embodiment of the present invention.

First, as shown in FIG. 3(a), K and A are placed on the semiconductor substrate 1.
/ layer and photoresist layer 11f: are formed and patterned to form the first wiring layer 2. Note that although the details of the semiconductor substrate 1 are omitted here, circuit elements such as transistors and resistors are formed thereon as in the case of FIG. It was formed.

Next, as shown in FIG. 3(b), while leaving the photoresist layer 11 on the first wiring layer 2, for example, an electron cyclotron resonance plasma CVD method (hereinafter referred to as ECR plasma CVD method) is applied. ), S as the first interlayer insulating film
In, the film 12t is formed to have the same thickness as the first wiring layer 2.

SiO film formed by ECR plasma CVD method.

Film 12 has poor directionality in film formation compared to other CVD methods, 8
i0,1x12 is deposited faithfully in the shape of a step, and hardly adheres to the sidewalls of the photoresist layer 11 in the lateral direction. Therefore, by removing the photoresist layer 11)
, the 5i01 film 12' on the photoresist layer 11 is also removed at the same time, and a flat surface consisting of the first wiring layer 2 and the 5jOz film 12 is obtained.

Next, as shown in FIG. 3, the first wiring layers 2 and 8i0. A 18isN4 film 13 is formed as a second interlayer insulating film on the surface including the film 12 by, for example, the CVD method.

The second interlayer insulating film may have etching characteristics (selectivity) different from those of the first interlayer insulating film.

Next, as shown in FIG. 3 (td), the 74,8isN4 film 13
A contact opening 14 is provided at a predetermined portion of the contact hole 14 . Opening part 1
It is desirable that the position 4 is provided in the surface of the first wiring layer 2 like 14a, but if the position of the mask is shifted,
Even if it is formed as in b, it does not affect the circuit elements unlike the conventional case.

That is, when plasma etching the 5isN4 film 13 using CF'3H gas, the S i Ox film 12 having a small etch rate ratio (selectivity) is hardly etched. Therefore, the formation of the opening 14b in the 5ilN4 film 13 will not damage the circuit elements on the semiconductor substrate 1.

Subsequently, the second wiring layer 15 is formed by depositing and patterning by Alt sputtering.

FIG. 4 is a plan view of FIG. 3 tdl. Even if the opening 14 for connecting the wiring layer 2 and the second wiring layer 15 in FIG. Therefore, as shown in FIG.
Since this becomes unnecessary, the degree of integration of the semiconductor device is improved.

In the above embodiment, a two-layer wiring was explained, but the first
By repeating a series of steps starting from the formation of the interlayer insulating film, it is possible to form a multilayer wiring having three or more layers.

FIG. 5 is a sectional view for explaining another embodiment of the present invention, and shows a three-layer wiring structure.

3 (at to (d)) on the semiconductor substrate 1.
After forming the first wiring layer 2, the S I 0g film 12°5isN4 film 13, and the second wiring layer 15 through the steps shown in FIG. A 5-ins film 12a is formed. Subsequently, after providing the second wiring layer 15 and the Si3N4 film 13a as an interlayer insulating film on the top 2a of the SiO* film 12, an opening 16t- is formed. Next, A/ is sputtered and patterned to form the third wiring layer 17, thereby completing 93-layer wiring.

In the above embodiment, the 8i0* film and the 5isN4 film were alternately used as the interlayer insulating film, but any insulating film with significantly different etching rate ratios (selectivity) may be used.

〔Effect of the invention〕

As described above in detail, according to the present invention, disconnections in wiring layers can be eliminated by filling the spaces between wiring layers with an interlayer insulating film to eliminate steps. Furthermore, since it is not necessary to make the contact portion of the wiring large in area, the degree of integration can be improved. Furthermore, since there is no need to increase the alignment accuracy of the openings, work efficiency and top manufacturing yield can be improved.

[Brief explanation of the drawing]

1(a), (bl is a plan view and a cross-sectional view of a contact portion of a semiconductor device having a conventional Ω multilayer wiring, FIG. 2 is a cross-sectional view for explaining the cross-section of the wiring in FIG. 1, Figures +a) to (d) are process sectional views for explaining one embodiment of the present invention, Figure 4 is a plan view of Figure 3(d),
FIG. 5 is a sectional view for explaining another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1: Semiconductor substrate, 2: First wiring layer, 1: First interlayer insulating film, 4: Opening part, 5: Second wiring layer,
11- Photoresist layer, 12- Siot film
13...5i1N4 membrane, 14...-opening part, 15...
second wiring layer, 16 opening, 17... third wiring layer; Agent Patent Attorney Oto Uchihara Figure 1 A, Figure 2 Kaya Figure 3 Figure 3

Claims (2)

[Claims] (1) A step of forming a first wiring layer on a semiconductor substrate on which a circuit element is formed; a step of filling a space between the first wiring layer with a first interlayer insulating film; A semiconductor device comprising the steps of forming a second interlayer insulating film on the entire surface including the first interlayer insulating film, and forming a second wiring layer on the second interlayer insulating film. manufacturing method. (2) The method for manufacturing a semiconductor device according to claim (1), wherein the first interlayer insulating film is formed by an electron cyclotron resonance plasma CVD method.