JPH03181134A - Formation of multi-layer wiring - Google Patents

Abstract

PURPOSE:To increase an etching rate of a nitride film, to facilitate etching in a lateral direction and to remove a corner part by lowering vacuum degree in a reaction chamber as regards a part of a specific depth of a surface layer in a process for forming a plasma nitride film. CONSTITUTION:A plasma nitride film 4 to be an interlayer insulation film is deposited and formed on a silicon wafer 1 and a first layer of wiring 2. In a process for forming this film 4, vacuum degree in a reaction chamber is lowered from the degree used as regards a part of a specific depth of a surface layer. Thus silicon nitride molecules on the deposited layer are deposited in a non-dense state as gas other than silane an ammonia in the plasma is collected at the time of film formation. Therefore during dry etching to be done in a subsequent process, an etching rate of the surface of the film 4 is increased and etching in the lateral direction is facilitated so that the corner of the film 4 is in a round shape.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a method of forming a plasma nitride film used as an interlayer insulating film in multilayer wiring.

<Prior Art> FIG. 2 is a cross-sectional view of a multilayer wiring formed by a conventional method.

The conventional method is shown below.

First, the first layer AlSi wiring 20 is placed on the silicon wafer 10.
After forming, a plasma nitride film 40 is deposited as an interlayer insulating film. Thereafter, the window is opened by a photo process, and anisotropic dry etching is further performed. Therefore, the plasma nitride film 40 is etched vertically, forming a steep surface. Next, on the silicon wafer 10 and AlSi
A second layer AlSi wiring 30 is formed on the wiring 20, but
In this step, a through hole 5 that reaches the end surface of the plasma nitride film 40 that has been opened and is substantially perpendicular to the end surface.
0 is formed. This through hole 50 has been a cause of disconnection in the formation of multilayer wiring.

<Problems to be Solved by the Invention> As explained above, disconnection of the second layer wiring caused by vertically processed through holes has been a major problem in the multilayer wiring process. In the method of the invention, the UT
The purpose is to form a second layer wiring without lines.

Means for Solving the Problems> The method for forming a multilayer wiring of the present invention includes forming a first layer wiring on a wafer, then forming an interlayer insulating film spanning over the wafer and the first layer wiring, and then forming the first layer wiring on the wafer. After forming a patterned resist on the interlayer insulating film, dry etching the interlayer insulating film using the resist as a mask, and then removing the resist. In the method for forming wiring, the above-mentioned interlayer insulating film is formed using a plasma nitride film at a predetermined degree of vacuum, and during the process of forming the nitride film, the degree of vacuum in the reaction chamber is reduced only to a predetermined depth of the surface layer. It is characterized by lowering the degree of vacuum below that of .

<Function> The method for forming a multilayer wiring according to the present invention is to perform deposition by lowering the degree of vacuum in the reaction chamber from the previous degree of vacuum only for a predetermined depth portion of the surface layer in the process of forming a plasma nitride film. As a result, in the dry etching performed in the subsequent process, the etch rate of the surface of the plasma nitride film becomes faster and etching in the lateral direction is promoted, so that the corners of the plasma nitride film have a rounded shape.

Due to the above, in the subsequent formation of the second layer wiring,
It is possible to eliminate constrictions in the through-hole portion, and a second layer wiring without disconnection is formed.

<Example> FIG. 1 is a schematic sectional view showing an example according to the method of the present invention over time.

(a) As shown in the figure, first, a first layer of AlSi wiring 2 is formed on a silicon wafer 1.

Next, as shown in FIG. 3B, an interlayer insulating film extending over the silicon wafer 1 and the first layer AlSi wiring 2 is formed by depositing a plasma nitride film 4 using the plasma CVD method. The plasma nitride film 4 is formed to a thickness of up to 6000 mm, but during the formation process, the degree of vacuum in the reaction chamber is reduced to 0. Deposition is performed by changing the temperature from 2 Torr to 09 Torr. By lowering the degree of vacuum by 0.1 Torr in this way, gases other than silane and ammonia in the plasma are incorporated into the silicon nitride molecules in the deposited layer during film formation.
The silicon nitride molecules are deposited in a sparse state compared to a layer deposited under the conditions of vacuum degree Q and 2 Torr. The etch rate near the surface of the plasma nitride film 4 formed in this manner becomes faster in the etching process described later.

Next, as shown in FIG. 3(C), a photoresist film 5 is formed.

Next, as shown in Figure (d), the photoresist film 5 patterned by the photo process is opened.

Next, as shown in FIG. 3(e), the plasma nitride film 4 is anisotropically dry etched using the photoresist film 5 as a mask to remove the photoresists r1g and 5. In this dry etching, highly anisotropic etching is performed using plasma, but at the same time, sputter etching is also performed to strip away material on the surface.
The photoresist film 5 also gradually recedes in the lateral direction in the portion of the photoresist film 5 where the window is opened. Furthermore, since the surface area of the plasma nitride film 4 formed by the plasma CVD method described above is loosely bonded, the etch rate becomes faster. The selectivity ratio of the etch rate becomes small, and the step due to the difference in etch rate that occurs in the conventional technique does not occur. Further, the opening of the through hole has a rounded shape.

Next, as shown in the figure (f), the second layer AlSi wiring 3
Formation of In particular, the thickness of the second layer AlSi wiring 3 is 1
．． When formed with a thickness of 4 μm, a shape without disconnection can be obtained.

<Effects of the Invention> According to the method of the present invention, multilayer wiring without disconnection can be manufactured, and it is possible to meet the increasing needs of recent years. In other words, according to multilayer interconnection, VL with a high degree of integration
This will greatly contribute to future high integration, such as by shortening the wiring of the SI and preventing the wiring from occupying the chip area and preventing signal delays.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view showing an embodiment according to the method of the present invention over time, and FIG. 2 is an explanatory diagram of a conventional example. Silicon wafer 1st layer AlSi wiring 2nd layer AlSi wiring Plasma nitride film Photoresist film

Claims (1)

[Claims] First layer wiring is formed on the wafer, then an interlayer insulating film is formed over the wafer and the first layer wiring, a patterned resist is formed on the interlayer insulating film, and then the resist is masked. After dry etching the interlayer insulating film and removing the resist,
In the method for forming the second layer wiring over the interlayer insulating film and the first layer wiring, the interlayer insulating film is formed using a plasma nitride film at a predetermined degree of vacuum, and in the process of forming the nitride film, a predetermined portion of the surface layer is formed. A method for forming multilayer interconnection characterized by lowering the degree of vacuum in the reaction chamber compared to the previous degree of vacuum only in the depth portion.