JP3348564B2 - Method for manufacturing dielectric capacitor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a dielectric capacitor having an upper electrode, a lower electrode and a dielectric film.

[0002]

2. Description of the Related Art When patterning various films, etc.,
2. Description of the Related Art Conventionally, it has been frequently used to process a resist into a desired pattern by lithography and perform etching using the resist as a mask.

However, in a dielectric capacitor using a perovskite type dielectric film as a dielectric film, a high melting point noble metal film is generally used as an electrode thereof. It is also necessary to raise the temperature of the wafer to about 300 ° C. in order to increase the reactivity between the etching species and the high melting point noble metal. Therefore, the resist is not suitable for an etching mask, and an inorganic film such as a SiO ₂ film or an SOG film is used as an etching mask.

FIG. 2 shows a conventional example of a method for manufacturing a dielectric capacitor as described above. In this conventional example, as shown in FIG. 2A, an adhesion layer 12 to the interlayer insulating film 11, a high melting point noble metal film 13,
The dielectric film 14, the high melting point noble metal film 15, and the inorganic film 16 are sequentially deposited.

[0005] Next, as shown in FIG.
The resist 17 is processed into an upper electrode pattern by lithography, and the inorganic film 16 is etched using the resist 17 as a mask. Then, as shown in FIG. 2C, after removing the resist 17, the high melting point noble metal film 15 is etched using the inorganic film 16 as a mask.

[0006] Next, as shown in FIG.
Another inorganic film 21 is deposited, and a resist 22 is processed into a pattern of a lower electrode by lithography on the inorganic film 21. Then, as shown in FIG. 2E, the inorganic film 21 is etched using the resist 22 as a mask, and after removing the resist 22, the dielectric film 14, the high melting point noble metal film 13 and the inorganic film 21 are used as a mask. The adhesion layer 12 is continuously etched to complete the dielectric capacitor 23.

[0007]

The inorganic film 1
Since the layers 6 and 21 cannot be easily removed like the resists 17 and 22, they are usually left on the dielectric capacitor 23. However, if the two inorganic films 16 and 21 remain on the dielectric capacitor 23, the step due to the dielectric capacitor 23 is large. For this reason, in the above-described conventional example, it is not easy to deposit and planarize an interlayer insulating film (not shown) by the later CVD method.

[0008]

According to a first aspect of the present invention, there is provided a method for manufacturing a dielectric capacitor, comprising the steps of sequentially laminating a first conductive film, a dielectric film, and a second conductive film; Forming a film on the second conductive film, etching the second conductive film and the dielectric film using the inorganic film as a mask, and forming the inorganic film on the upper electrode after the etching. Processing into a pattern, and using the inorganic film of the pattern of the upper electrode as a mask,
And etching the first conductive film using the dielectric film as a mask.

According to a second aspect of the present invention, there is provided a method of manufacturing a dielectric capacitor, comprising:
It is characterized in that a perovskite type dielectric film is used as the dielectric film.

A third aspect of the present invention is directed to a method of manufacturing a dielectric capacitor according to the second aspect.
Using a PZT film as the perovskite type dielectric film,
A Pt film is used as the first and second conductive films.

[0011]

In the method of manufacturing a dielectric capacitor according to the present invention, the same inorganic film is used as a mask when etching the upper electrode and the lower electrode, and the film of the inorganic film is etched by etching both the upper electrode and the lower electrode. Since the thickness is reduced, the thickness of the inorganic film remaining after the end of the etching is small.

Further, since the inorganic film is initially formed as a lower electrode pattern but later as an upper electrode pattern, the inorganic film remains only in the upper electrode pattern, and the range of the inorganic film remaining after etching is narrow.

Further, since the same inorganic film is used as a mask when etching the upper electrode and the lower electrode, the step of forming the inorganic film as a mask may be performed only once, and the number of steps is small.

[0014]

An embodiment of the present invention will be described below with reference to FIG. In this embodiment, as shown in FIG.
On the underlying interlayer insulating film 31, a 200 nm thick TiN film 32 as an adhesion layer to the interlayer insulating film 31, a 200 nm thick Pt film 33, and a 200 nm thick PZ
A T film 34, a Pt film 35 having a thickness of 200 nm, and a thickness 1
μm, and a SiO ₂ film 36 is sequentially deposited by a CVD method.

Next, as shown in FIG. 1B, the resist 37 is processed into a pattern of a lower electrode on the SiO ₂ film 36 by lithography, and the SiO ₂ film 36 is etched using the resist 37 as a mask.

Next, as shown in FIG.
7 is removed, and the SiO ₂ film 36 is used as a mask to remove O ₂
The Pt film 35 is etched with a / Cl ₂ mixed gas.
The PZT film 34 is etched with a Cl ₂ / Ar mixed gas. Note that the SiO ₂ film 3 is formed by these etchings.
6 is also etched to some extent in the film thickness direction, but a sufficient film thickness remains as a mask for etching performed later.

Next, as shown in FIG. 1D, the resist 42 is processed into a pattern of an upper electrode by lithography on the SiO ₂ film 36, and the SiO ₂ film 36 is etched using the resist 42 as a mask.

Next, as shown in FIG.
2 is removed, the Pt film 35 is etched with an O ₂ / Cl ₂ mixed gas using the SiO ₂ film 36 as a mask, the Pt film 33 is etched using the PZT film 34 as a mask, and the PZT film 34 is further etched. Use Ti as a mask with F-based gas
By etching the N film 32, the dielectric capacitor 43
To complete.

In the above embodiment, the SiO ₂ film 36 is used.
Are masks for both the etching of the Pt film 35 and the PZT film 34 in the step of FIG. 1C and the etching of the Pt film 35 in the step of FIG. For this reason, in the conventional example described above, the SiO _{2 is} more thicker than the final film thickness of the inorganic film 16 which is only a mask for etching the high melting point noble metal film 15 in the step of FIG.
The final thickness of the film 36 is smaller.

Moreover, as is clear from FIG. 1 (e),
The pattern of the upper electrode is not the pattern of the entire dielectric capacitor 43, that is, the pattern of the lower electrode, but only the SiO ₂ film 36 remains. Therefore, in this embodiment, the step due to the dielectric capacitor 43 is small, and
The deposition of the interlayer insulating film (not shown) by the VD method and its planarization are easy.

[0021]

In the method for manufacturing a dielectric capacitor according to the present invention, since the thickness of the inorganic film as a mask remaining after the etching of the upper electrode and the lower electrode is thin and its range is narrow, a step due to the dielectric capacitor is reduced. It is easy to deposit and planarize the interlayer insulating film thereafter. Further, the step of forming the inorganic film as a mask may be performed only once, and the number of steps is small, so that a dielectric capacitor can be manufactured at low cost.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing an embodiment of the present invention in the order of steps.

FIG. 2 is a side sectional view showing a conventional example of the present invention in the order of steps.

[Explanation of symbols]

32 TiN film 33 Pt film 34 PZT film 35 Pt film 36 SiO ₂ film 43 Dielectric capacitor

Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/822 H01L 21/28 H01L 27/04 H01L 27/108 H01L 21/8242

Claims (3)

(57) [Claims] A step of sequentially laminating a first conductive film, a dielectric film, and a second conductive film; a step of forming an inorganic film having a pattern of a lower electrode on the second conductive film; Etching the second conductive film and the dielectric film using an inorganic film as a mask; processing the inorganic film into an upper electrode pattern after the etching; and the inorganic film having the upper electrode pattern Etching the second conductive film with the mask as a mask, and etching the first conductive film with the dielectric film as a mask. 2. The method according to claim 1, wherein a perovskite type dielectric film is used as said dielectric film. 3. The method according to claim 1, wherein the perovskite dielectric film is P
3. The method according to claim 2, wherein a ZT film is used, and a Pt film is used as the first and second conductive films.