JPH03110849A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to decrease the inter-wiring capacity between a wiring and a lower layer wiring without augmenting a wiring resistance by a method wherein the base area of the wiring is formed small and the upper layer part of the wiring is made to overhang in the lateral direction to enlarge the sectional area of the upper part. CONSTITUTION:An interlayer insulating film 1, such as an oxide film or the like, is formed on a lower layer wiring, which is not shown in the diagram, and a barrier metal wiring 2, a gold-plated electrode metal wiring 3 and a first gold wiring 4 are laminated in order on this film 1 same with wiring width. A second gold wiring 5, whose wiring width is wider than the above width, is provided on the wiring 4. Here, the total sectional area of the wirings 4 and 5 is the same area as that in a conventional embodiment and even if this wiring structure is used as a power wiring, no difference is generated in the potential drop. Moreover, as the wiring width at the base part of this wiring is formed narrow, the installation area of the wiring becomes small and the inter-wiring capacity between the lower layer wiring and the wiring can be suppressed low.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the shape of wiring used in a multilayer wiring structure.

[Conventional technology]

Conventionally, the cross-sectional shape of the wiring used in this type of multilayer wiring structure is rectangular. A conventional example using gold wiring is shown in FIG. Barrier metal 2. on interlayer insulating film 1. A plating electrode metal 3 is sequentially deposited, and a rectangular gold wiring 10 is provided on the top layer. When such wiring is used as a power supply line, the cross-sectional area becomes large when considering the potential drop due to the length of the wiring, and the base that contacts the lower layer also becomes large.

[Problem to be solved by the invention]

The wiring structure of the conventional semiconductor device mentioned above has a rectangular cross-sectional shape as shown in Figure 5, so there is a large ground plane gap with the lower layer, and the interconnection with the lower layer wiring becomes large, which reduces the operating speed of the semiconductor device. The disadvantage is that it is slow.

Also, when wiring is used as a power supply wiring, if the cross-sectional shape is rectangular, the height of the wiring will increase if the cross-sectional area is determined, taking into account the potential drop due to the wiring length, and then the base is designed to be smaller. Since this results in a structurally unstable state, it is difficult to make the base smaller and the wiring pitch cannot be made smaller.

An object of the present invention is to provide a wiring shape that can suppress wiring capacitance with lower layer wiring without increasing wiring resistance.

[Means to solve the problem]

A semiconductor device of the present invention includes a first wiring provided in a predetermined shape on a semiconductor substrate, an interlayer insulating film provided on the first wiring, and a predetermined shape provided on the interlayer insulating film. In the semiconductor device having a multilayer wiring structure having a second wiring, a wiring width at a bottom surface portion of the second wiring is formed to be narrower than a wiring width at a portion other than the bottom surface portion.

With such a configuration, the capacitance value formed between the second wiring and the first wiring can be reduced. Also,
The reduction in cross-sectional area due to the narrower wiring width at the bottom is compensated for by extending the upper layer, thereby suppressing an increase in wiring resistance.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic cross-sectional view showing a first embodiment of the present invention. An interlayer insulating film 1 such as an oxide film is formed on the lower wiring (not shown).
is formed, and a barrier metal 2. such as titanium tungsten (T i W) is formed on this interlayer insulating film l with the same wiring width. Gold plating electrode metal 3 and first gold wiring 4 are sequentially laminated. A second gold wiring 5 having a wider wiring width is provided on the first gold wiring 4. Here the first and second
The total cross-sectional area of the gold wires 4 and 5 is the same as that in FIG. 5 as a conventional example. Further, the insulating film around the wiring is omitted from the drawing. In other words, the wiring resistance is the same as that of a conventional wiring having a square cross section, and there is no difference in potential drop even if this wiring structure is used as a power supply wiring. Furthermore, since the wiring width at the bottom part is narrow, the ground area is small, and the capacitance between the wiring and the lower layer wiring can be kept small.
To shorten the delay time of a semiconductor device and enable high-speed operation of a circuit.

Next, one method of manufacturing the wiring structure of the present invention will be described with reference to FIGS. 2 and 3. As shown in FIG. 3, an interlayer insulating film 1 is formed of an oxide film or the like on the lower wiring (not shown), and a T
A barrier metal 2 such as jW is sputtered to a thickness of about 0.1 μm.

Furthermore, gold plating electrode metal 3 for gold plating growth is sputtered to a thickness of about 0.1 μm on the upper layer. Subsequently, after coating the entire surface with photoresist 6, the photoresist 6 is removed by etching into a predetermined wiring shape with a wiring width of 5 μm, for example.
The gold-plated electrode metal 3 is exposed. Next, gold is applied to the gold plated electrode metal 3 to a thickness of, for example, 5 μm.

The first gold wiring 4 is formed by plating growth to a width of 5 μm. Further, after coating the entire surface with photoresist 7, patterning is performed so as to have the predetermined wiring shape and widen the wiring width. Subsequently, using the first gold wiring 4 as an electrode metal, gold is again plated to a thickness of about 5 μm and a width of about 15 μm to form a second gold wiring 5. Subsequently, after peeling off the photoresists 6 and 7, the exposed plating electrode metal 3 is etched with aqua regia and the barrier metal 2 is etched with hydrogen peroxide to obtain the wiring structure shown in FIG.

FIG. 4 is a schematic cross-sectional view of a second embodiment of the invention.

In this example, the process of forming the gold wiring similar to that of the first example, that is, the photoresist patterning process and the gold plating growth process, was repeated several times, and the horizontally expanding height of the gold wiring was The wiring is shifted. Also, the fourth
The width of each wiring shown in the figure is set so that the cross-sectional area is equal. By forming the horizontally expanding portions of the gold wiring in an alternating manner in this manner, there is an advantage that the height of the wiring can be suppressed and the wiring pitch can be made smaller than in the conventional gold wiring.

〔Effect of the invention〕

As explained above, the present invention makes the bottom area of the wiring small and makes the upper layer of the wiring protrude laterally to increase the cross-sectional area, so that the wiring resistance can be increased without increasing the wiring resistance. This has the effect of reducing inter-wiring capacitance. In addition, when forming wiring, the horizontally protruding parts of the upper layer of wiring are alternated vertically between adjacent wirings, which reduces the height of the wiring compared to conventional wiring. This has the effect of reducing the wiring pitch.

In the embodiments, the wiring has a T-shaped cross-section, but the present invention is not limited to this, and may be cross-shaped or the like. Furthermore, the present invention is not limited to gold wiring, but similar effects and effects can be obtained as long as a wiring material with good adhesion or a metal material that can be grown by plating is used.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the first embodiment of the present invention, FIGS. 2 and 3 are cross-sectional process diagrams of the first embodiment of the present invention, and FIG. 4 is a cross-sectional view of the second embodiment of the present invention. The cross-sectional view, FIG. 5, is a cross-sectional view of a conventional gold wiring. DESCRIPTION OF SYMBOLS 1... Interlayer insulating film, 2... Barrier metal, 3... Plated electrode metal, 4... First gold wiring, 5... Second Gold wiring, 6, 7...
・Photoresist, 8...Third gold wiring, 9...
...Fourth gold wiring, IO...gold wiring.

Claims (1)

[Claims] a first wiring provided in a predetermined shape on a semiconductor substrate;
In a semiconductor device having a multilayer wiring structure having an interlayer insulating film provided on the first wiring and a second wiring provided in a predetermined shape on the interlayer insulating film, the bottom surface of the second wiring A semiconductor device characterized in that a wiring width at a portion of the bottom portion is narrower than a wiring width at a portion other than the bottom portion.