JPS5917540B2 - Wiring formation method for semiconductor devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming wiring in a semiconductor device, and more particularly, an object of the present invention is to provide a wiring method for a semiconductor device including an improved method for forming an A wiring layer of a semiconductor element.

In a conventional example of stacking a semiconductor device, the wiring layer j0 of a semiconductor element, a part of which is shown in cross-sectional view in FIG. 1, is arranged as follows.

That is, the silicon substrate 1 indicated by dotted lines in FIG. 1 is shown with the electrode regions formed thereon omitted from illustration. SiO2 layers 2, 2', . ' Prepare for... A semiconductor device having such a structure is manufactured as follows. That is, a SiO2 film 2 is deposited on the main surface of the substrate 1, an opening is formed in it, and impurities are diffused and introduced to form a predetermined electrode region (not shown). Deposited in 0 cases of evaporation. After a photoresist is applied to the layer A, resist layers 4, 4', . . . are formed in a predetermined wiring pattern using a mask. Next, using the resist layer as a mask, the exposed portion of the A layer is removed by etching with H3PO4, thereby forming an A layer having a 5-line pattern. Afterwards, the resist layer is removed to complete the formation of the semiconductor element. In the production of the conventional semiconductor device described above, the problem of adhesion between the resist layer and the A layer causes variations in the taper angle, and the control range is also narrow. ■
Another disadvantage is that it is not possible to form a sufficient taper angle due to poor adhesion. The present invention provides a method for forming interconnections in a semiconductor device that eliminates the above-mentioned conventional drawbacks.

The wiring forming method for a semiconductor device according to the present invention includes depositing a layer of SiC or Si3N4 on an aluminum wiring layer on the surface of a semiconductor 35 element by a low-temperature plasma method to form an interface layer between the two layers, and forming an interface layer between the two layers.
The present invention is characterized in that when etching the aluminum wiring layer using the N4 layer as a mask, the interface layer is preferentially etched to give a taper to the side surface of the aluminum wiring layer.

Next, the present invention will be described in detail with reference to the drawings regarding one embodiment of a method for forming wiring in a semiconductor device.

FIG. 2 shows a part of the manufacturing process of a semiconductor device. Figure a shows SiO2 layers 2, 2', which are an example of an insulating coating, on the main surface of the substrate 1.
- is formed, impurities are diffused and introduced into the substrate through the opening of the insulating film in the portion where the electrode region is to be formed to form an electrode region (not shown), and then the A layer 3 is deposited on the main surface by an example of vapor deposition. do. Next, layer it with SiC or Si3.
A coating 14 of N4 is applied. This film is deposited at low temperatures (4
00℃ or less) plasma depot (PlaSmaDepOS
Approximately 2,000 people will be coached at itiOn). Further, the above is laminated and coated with resist to form resist layers 15, 151, etc. in a predetermined wiring pattern (Figure a).
. Next, using the resist layers 15, 151, . . . as a mask, an example of CF4 is applied to the SiC or Si3N4 film 14.
The SiC or Si3N4 patterned coating 14 is etched by means such as plasma etching by etching.
a914a'... (Figure b). Next, the above Si
C or Si3N4 patterned coatings 14a, 14a'
The exposed surface of the A layer 3 is etched using a mixed acid etching solution containing H3PO4 as a main component, using the mask as a mask to form electrodes 3a and 3a1 (FIG. c). In addition to the above, the end face of the A layer of the electrode can be formed into a desired slope. As explained in Fig. 3, this is already possible with SiC or Si3.
When a layer consisting of N4 is plasma deposited on layer A, an interphase layer 34 (Figure a) is formed at the adhesive interface between both layers, and Aj! , the etching rate is much higher than that of . Therefore, etching in the direction in which the interphase layer extends progresses more rapidly than etching in the thickness direction of the A layer. That is, since the upper surface of the side etching of the A layer is expanded over time by the etching of the interphase layer, a desirable etched surface can be formed. Diagram b
The above state will be explained and the intermediate process of etching the \A layer will be shown. Figure c shows that the etching of the interphase layer has progressed further than in the state shown in Figure b, and the A layer has already disappeared in some parts of the lower layer (an example of the SiO2 layer).
is exposed. Taper etching is accomplished as described above. Further, FIG. 4 shows the shape of the etching according to the method of the present invention in comparison with that of the conventional method. Is the diagram cut off? SE of shape
This is a copy of the M observation photograph, and the magnification is approximately 6000x.
Fig. a shows the etching situation according to the conventional method, and Fig. b shows the etching situation according to the present invention. Etching was done at 30℃, conventional etching solution was H3PO4: 760 parts, CH3CO
Mixing ratio of OH: 150 parts, HNO3: 30 parts, H2O: 50 parts, the one of the present invention\the etching solution is H3PO4:
760 parts of CH3COOH, 150 parts of HNO3:8, and 50 parts of old H2O.

Further, in the method of the present invention, the taper angle can be easily controlled by changing and combining the temperature, composition, etc. of the etching solution. The above is illustrated in FIG.
T. for the product produced by the method of the present invention. c. T
1CyclingTeSt) was applied to check for breakage in the conventional method product and the A wiring layer of the multilayer wiring element.

Above T. C. T is -50℃~+125℃ cooling history 1
It is applied 00 times. As a result of the above, the method of the present invention has 100 non-defective products out of 100 products, and the non-defective product rate is 100%.
However, the conventional method had a 90% non-defective rate for the same number of products, which was a large difference. From the above to multilayer wiring}
An example of the wiring layer A is formed such that, for example, the taper of the first layer A is in very good contact with the second layer A which is disposed thereon via an insulating film. Further, in the above, the device according to the present invention has SiC or Si on the wiring layer.
Since the 3N4 film is left in place, it has a large blocking effect against harmful impurities added to the device from other sources, and has remarkable effects such as improving the electrical characteristics of the semiconductor device and maintaining it in good condition for a long time. The method of the present invention
O is extremely effective for multilayer wiring elements such as large-scale integrated circuit devices (LSIs) and

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device manufactured by a conventional manufacturing method.
FIGS. 2a to 2c are cross-sectional views of a semiconductor element showing a method for forming interconnections in a semiconductor device according to an embodiment of the present invention in the order of steps, and FIGS. 3a to 3c illustrate etching steps according to the present invention. 4A is a conventional etched cross section, FIG. 4B is an etched cross section according to the present invention, and FIG. 5 is a model diagram for explaining the present invention. The same reference numerals in the drawings indicate the same or corresponding parts, respectively. 3...A layer, 14, 14&, 14&
1...SiC or Si3N4 layer.

Claims (1)

[Claims] 1. A layer of SiC or Si_3N_4 is deposited on the aluminum wiring layer on the surface of the semiconductor element by a low-temperature plasma method to form an interface layer between the two layers.
A method for forming wiring in a semiconductor device, characterized in that when etching the aluminum wiring layer using an iC or Si_3N_4 layer as a mask, the interface layer is preferentially etched to give a taper to the side surface of the aluminum wiring layer.