JPS60150648A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To flatten steps created in an interlayer insulating film and thereby to prevent a second and following layer wirings from breaks by a method wherein protrusions created in the interlayer insulating film due to the first layer wiring are removed by photoetching wherefor the mask is used that served the process of forming the first layer wiring pattern. CONSTITUTION:A first layer wiring 13 is patterned on a substrate 11 with the intermediary of an insulating film 12, to be covered by an SiO2 interlayer insulating film 14 formed on the entire surface by the vapor phase growth method. The surface of the interlayer insulating film 14 is coated with a positive type photoresist 15 to melt when exposed to light, and the photoresist 15 is exposed to light with the intermediary of the mask 19 used in the photoetching of the first layer wiring 13. Protrusions on the first layer wiring 13 are kept from the light due to a mask pattern 20, and are removed by a later developing process. Next, the remaining resist serves as a mask when the interlayer insulating film 14 is subjected to etching, whereby the protrusions caused by and located just over the wiring 13 are removed from the interlayer insulating film 14. Finally, a stripping solvent or the plasma-aided peeling method is employed to remove the remaining resist 15.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, which includes forming dedicated wiring in multiple layers on a semiconductor substrate.

1. Prior Art Conventionally, when forming a multi-layer structure on a semiconductor substrate, as shown in the cross-sectional view of the product in FIG.
An insulating film 2 such as Sing, PSG or 5isN4 is formed on top of the insulating film 2, and A7゜kl-Cu, A
A predetermined first layer wiring pattern 3 is formed by photoetching on the entire deposited conductor layer, such as 1-8t% MoAu or polycrystalline silicon doped with impurities, and then a free wiring pattern 3 is formed by vapor phase epitaxy. interlayer insulation covering Ig
A second layer wiring 5 is formed on the entire surface of the interlayer insulating film 4 using the same method as the first layer wiring, and a glabella insulating film 6 is overlaid, and a through hole 8 is used to form a second layer wiring 5 on the first layer. It was also formed in the same way as the third layer wiring 7 which passed through the eye wiring 5.

In this way, in the conventional method, the first layer wiring, the interlayer insulating film, and the second layer wiring are stacked in order to form a multilayer packaging. The surface is uneven due to the step, and the wiring after the 2nd rFT arrangement 1i15 is broken at the step part surrounded by circles 9 and 10 in Figure 1, and the wire is widened and the resistance increases. do. Bota,
During the second photo-etching process, when the photoresist is coated, the pattern accuracy decreases due to the reflection of light from the step part, thinning of the wiring, occurrence of cracks, etc., reducing the reliability of the handera tai-so-ryu. Improve the accumulation rate 1)! It was causing 1tr.

C1 Purpose of the Invention The object of the present invention is to planarize -P in the step part of the insulating film between the eyebrows on the wiring due to the selected corner of the arrangement, and therefore, to planarize the step part of the insulating film between the eyebrows on the wiring. An object of the present invention is to provide a method for manufacturing a semiconductor device in which film formation and the like do not occur.

20 Structure of the Invention According to the present invention, the isolation j=Ul formed on the semiconductor substrate
Depositing a dedicated layer on i4 and forming a predetermined first layer distribution pattern by photo-etching.

Next, a step of forming an interlayer insulating film covering the first layer wiring pattern on the entire surface by vapor phase epitaxy, and photoetching using the same mask as the one used for forming the first layer wiring pattern are performed. Interlayer insulation film + 1 gq
A semiconductor device comprising the steps of: removing a convex portion on a target haze pattern down to the center of a substantially flat surface; and forming a second layer wiring on the almost flat interlayer insulating film. A manufacturing method is obtained.

Talent 1. Example Next, all embodiments of the present invention will be explained.

FIG. 2 (al □-'x Ishik e) is a cross-sectional view of the work-in-progress of step J-, which is an example of the present invention. “
First, as shown in FIG. 1(a), an insulating film 12 is placed on a semiconductor substrate 11, and tit 1 is formed on the insulating film 12 by photo-etching.
An h-th wiring butter/13 is formed, and then an interlayer insulating film 14 of f:1iQ2 is formed over the entire surface by vapor phase growth.

The thickness of the interlayer insulating film 14 at the recessed portion is approximately 2 to 2.5 μm. Pigeon r! A positive type photoresist (15) is further coated on the single-transfer film (14) so that the exposed portion is exposed to light. Then, the entire exposure is performed using the same mask 19 used in the photo-etching of the first layer of wiring butter. Due to this flashing, the mask pattern 20 is not exposed to the hμ portion of the convex portion on the third layer mark #13, and the current 1W process is not caused by the mask pattern 20 (see FIG. 2).
b) is removed. Next, use the remaining resist as a mask and, for example, use Buff Art Fu enemy to create Masuma Haen +
By etching *14t, the convex portion of the interlayer insulation 8!414 above the wiring w13 is removed, as shown in FIG. 2tc). Next, the remaining resist 15 in FIG. 2 (as shown in dJ) is removed using a stripping solution or the plasma i stripping method. At this time, small protrusions 16t of SiOzlM are formed at the ends of the resist, so the entire surface is etched with the buffered hydrofluoric acid solution to round off the protrusions 16. Then, as shown in FIG. 2(e), a glabella insulating film 23 is formed on the entire surface, covering the second layer wiring 22 and the wiring 22'lt on the interlayer insulation layer 14.
A layer gap A (formed on the film 23) is formed, and a third layer wiring 24 is connected to the second layer wiring 22 through a through hole 8.

Although both a positive resist and a negative resist were used on the upper side, the method of the present invention can be carried out using only a positive resist, using a mask for forming a wiring pattern and an inverted mask of this mask.

As described in detail in Section 1 of the invention, in the present invention, by flattening the unevenness that occurs on the interlayer insulating hood, unevenness in the thickness of the layer 1 on the interlayer insulating film when there is an unevenness is eliminated. This has the effect of improving reliability, reducing wiring film thickness and wiring spacing, and making semiconductor devices more compact.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device manufactured by a conventional method, and FIGS. 2+a) to (e) are cross-sectional views of unmanufactured products in process order to explain an embodiment of the present invention. . -1, 11... Semiconductor substrate, 2, 12...
...Insulating film, 3.13...1st Wl interconnect%4
, 14...first and second interlayer insulating film, 5.22.
...2nd layer onwards, 6゜22...Group, 20th 3rd
Interlayer insulation gland, 7,24°°゛...Third layer wiring, 8.
...Through hole, 15.Old...Neka type resist, 16.River/protrusion, 19..Mask, 2゜.
・・・・・・Mask pattern, ,・・２；＼ Agent Patent attorney Susumu Uchihara;″) Tsumugi 1st Ward 2B

Claims (1)

[Claims] In a method of manufacturing a semiconductor device, which includes forming a multilayer wiring board on a semiconductor substrate, a conductor layer is deposited on an insulating film formed on the semiconductor substrate, and the first layer of the multilayer wiring is formed by photo-etching. a step of forming a first layer wiring pattern, a step of forming an interlayer insulating film for the first layer wiring pattern by vapor phase epitaxy;
a step of removing the convex portions on the first layer wiring pattern of the interlayer dielectric film by photoetching using the same mask as that used for forming the WJ wiring pattern until it becomes a substantially flat surface; A method for manufacturing a semiconductor device, which is characterized in that it includes a step of forming a second layer wiring on this substantially flattened interlayer insulating film and gold.