JP3119021B2 - Method for forming contact hole in semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an contact hole forming method for a semiconductor device, a contact hole forming method for a semiconductor device for forming a contact hole and more particularly by etching the SiO ₂ film in a semiconductor integrated circuit manufacturing process.

[0002]

2. Description of the Related Art Conventionally, in the manufacture of semiconductor devices (semiconductor integrated circuits), photolithography in which a mask pattern is transferred to a resist in order to form a contact hole in an SiO ₂ film formed on the surface of a semiconductor substrate. Technology and S using the patterned resist as a mask
A process combining an etching technique for processing an iO ₂ film is employed. As a method for forming the contact hole, a method combining wet etching and dry etching is also known.

First, a general photolithography and etching process for forming a contact hole is shown in FIG.
It will be described based on. First, S on the Si substrate 31
An iO ₂ film 32 is formed, a resist 33 made of a photosensitive polymer is applied, and then prebaking is performed to remove an organic solvent contained in the resist 33 (FIG. 9).
(A)). Next, the pattern of the mask 34 is transferred onto the resist 33 by exposure (FIG. 9B), and then the resist 33 is developed to form a resist pattern 33a corresponding to the pattern of the mask 34. Next, post-baking is performed to remove moisture contained in the resist 33 to harden the resist 33, thereby increasing the adhesion to the SiO ₂ film 32 (FIG. 9C). Further, the resist pattern 33
A reactive ion etching process is performed on the SiO ₂ film 32 using “a” as a mask to form a contact hole 35 (FIG. 9D). Next, the unnecessary resist 33 is dissolved and removed (FIG. 9E). As described above, FIG.
A general photolithography and etching process is composed of five main processes as shown in FIGS.

Next, a method of combining wet etching and dry etching will be described with reference to FIG. In this method, first, S
An iO ₂ film 42 is formed, and a resist 43 made of a photosensitive polymer is applied on the SiO ₂ film 42. Thereafter, prebaking is performed to remove the organic solvent contained in the resist 43, and a pattern (not shown) on the mask is transferred onto the resist 43 by exposure, and then developed. Next, post-baking is performed to harden the resist 43 to increase the adhesion to the base (FIG. 10A). Further, using the resist 43 as a mask, for example, a 10: 1 BHF solution (H
The upper portion of the SiO ₂ film 42 is isotropically etched by wet etching using a mixed solution of F, HNO ₃ and H ₂ O (see FIG. 10B). After this,
Anisotropic etching by dry etching
A chamfered pattern is formed on the O ₂ film 42 (FIG. 10).
(C)). Next, by dissolving and removing the unnecessary resist 43, a bowl-shaped contact hole 45 is obtained (FIG. 10D).

[0005]

In recent years, in a semiconductor device, it has become necessary to obtain a pattern of 1 μm or less in accordance with the miniaturization of wirings and the like, and with this, the aspect of the pattern has been increased. .

In the photolithography and etching steps shown in FIG. 9, a rectangular resist pattern 3 is formed.
3a is formed. For this reason, the resist pattern 33a
Has a width to be etched (hereinafter referred to as a pattern size) such as a space between wirings and a contact hole diameter of 1 μm or less, there are the following problems at the time of etching. That is, when the pattern size is small as described above, the upper corners of the rectangular resist pattern 33a prevent the flow of the etching gas ions into the pattern, and the etching gas ions hardly penetrate into the SiO ₂ film 32, Even if the ions can enter, it is difficult for the reaction product of the ions and the SiO ₂ film 32 to come out of the opening. For this reason, the etching rate decreases.
FIG. 11 is a graph showing the relationship between the pattern size and the normalized etch rate, where the etch rate at an infinite pattern size is 1. From FIG. 11, it can be seen that for a small pattern size of 1 μm or less, the etch rate gradually decreases as the pattern size decreases. For this reason, for example, when a pattern having a size of 2.0 μm and small patterns having a size of 0.8 μm and 0.6 μm are present in one resist pattern (FIG. 12).
(A)), when the etching process is stopped when the 2.0 μm-sized pattern is just etched, 0.8
Etching becomes insufficient with patterns having a size of μm and 0.6 μm (FIG. 12B). Also, if the etching process is performed until the 0.6 μm size portion is sufficiently etched, the etching proceeds excessively in the 2.0 μm size pattern portion. Therefore, there is a problem that etching failure occurs due to the so-called microloading effect, uniform etching cannot be performed, and a desired pattern size cannot be obtained.

When the aspect ratio of the contact hole 35 is large, a wiring material 36 is formed in the contact hole 35.
Is embedded (FIG. 13), the embedding characteristics in the stepped portion are deteriorated, the film thickness of the wiring material 36 in the stepped portion is reduced, and the value of b / a is reduced. Therefore, there is a problem that the step coverage of the wiring is deteriorated, and the probability of causing a conduction failure is increased.

On the other hand, in the method using both wet etching and dry etching, since the pattern of the resist 43 has a rectangular shape, when dry etching is performed, the etching gas ion S
Intrusion into the iO ₂ film 42 and release of reaction products are inhibited,
There is a problem that etching failure occurs due to the microloading effect, uniform etching cannot be performed, and a desired pattern size cannot be obtained.

Further, in this method, a bowl-shaped contact hole 45 is formed by adding an isotropic etching step by wet etching, and the upper portion of the bowl-shaped contact hole 45 is largely opened, and a stepped portion is formed. Is gentle, so that the substantial aspect ratio is reduced. Therefore, as shown in FIG.
6 is improved, the value of b / a is increased, and the step coverage of the wiring is improved. However, there is a problem that the number of steps of wet etching increases.

Further, if the adhesion between the resist 43 and the SiO ₂ film 42 is poor, the etching solution permeates in the horizontal direction from the interface between the resist 43 and the SiO ₂ film 42, and the etching spreads in the horizontal direction. Therefore, there has been a problem that reproducibility and controllability are deteriorated, and disadvantages also occur in fine processing.

The present invention has been made in view of the above-mentioned problems, and provides a micro-loading effect while improving the step coverage of wiring without increasing the number of steps even if the pattern size is 1 μm or less. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device, which can prevent a poor etching and can form a contact hole having a desired pattern excellent in reproducibility and controllability.

[0012]

In order to achieve the above object, a method of forming a contact hole in a semiconductor device according to the present invention comprises forming an SiO ₂ film on a substrate, and exposing a resist on the SiO ₂ film. In the step, coating is performed by controlling the film thickness so that a node of a standing wave is generated on the resist surface, and the resist is subjected to overall exposure and mask exposure and developed, and after forming a bowl-shaped resist pattern, the SiO ₂ film is formed. And forming a contact hole in the semiconductor device by performing reactive ion etching on the mask, wherein a mask having a pattern size of 1 μm or less is used for the mask exposure.

Further, in the above-described method for forming a contact hole in a semiconductor device, a PEB (Post Exposure Bake) process is performed after the entire surface exposure or the mask exposure.

[0014]

Since the inhibitor (development inhibitor) in the resist is decomposed by exposing the resist, if the intensity of the entire exposure is adjusted, only the surface of the resist is strongly exposed, and the inhibitor concentration is reduced. It becomes ready for development. Further, as the depth becomes deeper, the intensity of the exposed light becomes weaker, the inhibitor density becomes higher, and the development becomes impossible. That is, the inhibitor concentration after the entire surface exposure shows a concentration distribution in which the inhibitor concentration increases as the depth from the surface of the resist increases.

Further, when mask exposure is performed using a mask having a pattern size of 1 μm or less, in the mask exposure, light is irradiated to the resist only from the opening, and the light intensity distribution in the opening is close to the surface. The more the state that can be dissolved by the development, the larger the state.

By the way, when a standing wave is generated in the resist at the time of exposure, the standing wave on the reflecting surface usually becomes a node,
In the following, antinodes and nodes alternate at equal intervals, and the period of the standing wave L
Is L = λ / 2n [Å] (the exposure wavelength is λ [Å] and the refractive index of the resist is n). When a node of the standing wave comes on the resist surface, the resist surface is hardly dissolved, and after development, a bowl-shaped resist pattern 13a having a cross-sectional shape as shown in FIG. 1 is formed.

As described above, the SiO ₂ film 12 is formed on the substrate 11.
Is formed, and a resist is applied on the SiO ₂ film 12 by controlling the film thickness so that a node of a standing wave is generated on the resist surface in a subsequent exposure step, and the resist is entirely exposed and has a pattern size of 1 μm or less. By performing mask exposure using the mask and developing the resist, a bowl-shaped resist pattern 13a having a pattern size of 1 μm or less and excellent in controllability and reproducibility can be formed.

Furthermore, when a reactive ion etching the SiO ₂ film 12 using the resist pattern 13a in such a bowl-shaped subjected, since the opening of the resist pattern 13a is spread gently, ions SiO ₂ film 12
, And the reaction product of the ions and the SiO ₂ film 12 also easily comes out of the opening. For this reason, etching failure due to the microloading effect is prevented, and a decrease in the etch rate is suppressed. That is, even if the pattern size is reduced, uniform and reliable etching is performed, the precision of pattern formation is increased, and a bowl-shaped contact hole having a desired fine pattern can be formed.

In the contact hole, since the bottom of the side surface of the resist pattern 13a is linear, excellent line width controllability is obtained. In addition, even if overetching occurs, the linearity of the bottom of the hole side surface is maintained, and excellent line width controllability is exhibited.

Further, since the bowl-shaped resist pattern 13a is formed without adding an isotropic etching step by wet etching, the number of steps does not increase.

In addition, since the opening of the contact hole is gradually widened as shown in FIG. 2, even if the contact hole 15 has a pattern size of 1 μm or less, the substantial aspect ratio becomes small. ,
When the wiring material 16 is buried in the contact hole 15 in a later step, the wiring material 16 at the step portion also has a sufficient thickness, and the value of b / a increases. Therefore, the step coverage of the wiring is improved, and the poor conduction is prevented.

In the above-described method for forming a contact hole in a semiconductor device, when the exposure wavelength is a single wavelength,
Due to the effect of standing wave, λ / 4n perpendicular to the underlayer
When the light intensity changes at a period of (λ; wavelength, n: refractive index), a wavy pattern may appear on the side wall of the resist 13 (FIG. 3A). However, the wavy pattern is also smoothed by performing the PEB process after the entire surface exposure or the mask exposure (FIG. 3B), and the effect of the standing wave can be reduced. In addition, the inhibitor concentration distribution in the resist 13 after the entire surface exposure and the mask exposure becomes gentle, and the line width can be easily controlled.
Therefore, a bowl-shaped resist pattern 1 with a smooth surface
3a are formed, and the contact hole 15 after etching is formed.
Can be further improved.

In addition, before the mask exposure, the PEB
In the case where the processing is performed, light in the mask exposure is easily incident, so that the mask exposure amount can be estimated to be small, and the influence of the standing wave of the light during the mask exposure is also reduced. .

[0024]

Examples and Comparative Examples Examples and comparative examples of a method for forming a contact hole in a semiconductor device according to the present invention will be described below with reference to the drawings. FIGS. 4A to 4E are schematic cross-sectional views showing respective steps for explaining a method of forming a contact hole in a semiconductor device according to an example.

First, an SiO ₂ film 12 is formed on a substrate 11, and then a resist 13 such as PFX 15 (manufactured by Sumitomo Chemical Co., Ltd.) is formed on the SiO ₂ film 12 by using a standing wave generated in the resist 13. Spin coating is performed to a thickness of, for example, about 12000 ° so that the vicinity of the node is located on the surface of the resist 13 (FIG. 4A). Table 1 below shows the relationship between the resist film thickness at which a standing wave occurs and the state of the standing wave on the surface of the resist 13. By utilizing this fact, the thickness of the resist 13 is controlled so that the vicinity of the node of the standing wave is located on the surface of the resist 13. For example, when the refractive index of the resist 13 is 1.64 and the exposure wavelength is 4360 ° (g-line), the period of the standing wave is about 1330 °. Since the standing wave becomes a node on the surface of the SiO ₂ film 12, the film thickness is about (1330 k) Å, k is a natural number;
(See Table 1), the standing wave on the surface of the resist 13 becomes a node.

[0026]

[Table 1]

Thereafter, a pre-bake is performed to form a resist 13
The organic solvent contained therein is removed (FIG. 4A). Next, 115 mJ / cm ² is applied on the resist 13 with a stepper.
G-line (4360 °) is exposed on the entire surface (FIG. 4).
(B)). The exposure amount at this time is such that the resist 13 is not completely exposed, that is, an exposure amount that leaves a constant film thickness. In addition, g-line (4360 °) was used for exposure, but in addition to g-line, h-line (4050 °) and i-line (3650 °)
Å), KrF (2490 °), ArF (1930 °), and other single-wavelength exposure sources can be used.

Subsequently, mask exposure is performed by exposing with a stepper using a mask 14 having a pattern size of 1 μm or less (FIG. 4C). The exposure amount at this time is mask 1
It is 45 mJ / cm ² in such an amount that four dimensions can be obtained.

Next, development was carried out.
Performed for 20 seconds post-baking, the resist 13 is cured by skipping the water contained in the resist 13, SiO ₂
The adhesion to the film 12 is increased. Thus, a bowl-shaped resist pattern 13a corresponding to the mask 14 is formed (FIG. 4D). Furthermore, this bowl-shaped resist pattern 13
The contact hole 15 is formed by performing a reactive ion etching process on the SiO ₂ film 12 using “a” as a mask.
(E)), the unnecessary resist pattern 13a is removed (FIG. 4 (f)).

The above etching process is performed using Ar (350 sccc).
m) as a diluent gas, using a mixed gas of CF ₄ and CHF ₃ , and using the apparatus shown in FIG.
W, the distance between the electrodes: 1.0 cm, the sample temperature: −30 ° C., and the pressure: 500 mTorr.

In the figure, 21 indicates an upper electrode, 22 indicates a lower electrode, 23 indicates a high frequency power supply, 24 indicates a gas inlet, and 25 indicates a wafer.

Incidentally, O ₂ may be added as an etching gas to the above mixed gas.

In the above embodiment, Ar is used as the diluent gas, but He or the like may be used as the diluent gas.

FIG. 6 shows CF in the mixed gas according to the embodiment.
Etching was performed by changing the mixing ratio of ₄ and CHF _3, and the result of examining the relationship between the mixing ratio and the etching rate of SiO ₂ and resist and the relationship between the mixing ratio and the selectivity of SiO _{2 to} the resist were examined. FIG.

[0035]

[Table 2]

Table 2 shows that the contact hole 15 (FIG. 7A) according to the embodiment formed by using a gas mixture having a small selectivity in FIG. 6 during etching and a gas mixture having a large selectivity in FIG. The contact hole 15 (FIG. 7B) according to the example formed by the conventional method, the contact hole 35 (FIG. 9) according to the comparative example formed by the conventional photolithography and etching process, and the conventional wet etching and dry A contact hole 45 according to a comparative example formed by a method using etching together (see FIG. 1)
0) shows the results of examining the number of processes, the presence / absence of the influence of the microloading effect, the line width controllability, and the wiring step coverage.

As is clear from Table 2, the contact hole 35 according to the comparative example is affected by the microloading effect, the step coverage is considerably deteriorated, and the contact hole 45 according to the comparative example is also poor. , Affected by micro loading effect,
In addition, the step coverage is poor and the number of steps is large.
However, in the contact hole 15 according to the embodiment formed using the mixed gas having a small selectivity, the line width controllability is excellent, the number of steps is not increased, and the influence of the microloading effect is eliminated. The performance has also been greatly improved. Also, in the contact hole 15 according to the embodiment using the mixed gas having a high selectivity, the number of steps is not increased, the influence of the microloading effect is eliminated, and the line width controllability is excellent. It was able to confirm that it was excellent.

FIG. 8A is a schematic cross-sectional view showing a contact hole 15 according to the embodiment subjected to normal etching, and FIG. 8B is a sectional view according to the embodiment subjected to over-etching. FIG. 3 is a schematic sectional view showing a contact hole 15. As is clear from FIG. 8, it is confirmed that even in the case of over-etching, the contact hole 15 maintains the linearity of the bottom of the side surface of the hole and can exhibit excellent line width controllability. did it.

As described above, in the method of forming a contact hole in a semiconductor device according to the embodiment, the resist 13 is strongly exposed only at the surface portion by adjusting the exposure amount during the entire surface exposure, and as the depth increases, the resist 13 becomes deeper. It is in a state of light exposure. In the mask exposure, the opening is strongly exposed, but is also exposed in the depth direction of the resist 13, and the intensity becomes weaker according to the depth. That is, the inhibitor concentration after the entire surface exposure shows a concentration distribution that increases as the depth from the surface of the resist 13 increases, and the dissolution by development becomes more impossible as the inhibitor concentration increases.

At this time, a resist 13 is applied on the SiO ₂ film 12 by controlling the film thickness so that a node of a standing wave is formed on the resist surface in a later exposure step. Mask exposure is performed using a mask 14 having a pattern size of 1 μm or less. The resist 13 is exposed with a bowl-shaped intensity distribution by a combination of the entire surface exposure and the mask exposure, and the small resist pattern 13a having a size of 1 μm or less is formed into a bowl shape having good controllability and reproducibility. Can be.

Further, since the resist pattern 13a has a bowl shape, etching gas ions can easily enter the SiO ₂ film 12 in a subsequent etching step, thereby preventing defective etching due to the effect of the microloading effect. In addition, a decrease in the etch rate can be suppressed. For this reason, even if a pattern having a size of 1 μm or less is included, uniform etching becomes possible,
The precision of pattern formation can be improved, and a desired fine bowl-shaped contact hole 15 can be formed.

In the contact hole 15,
Since the bottom of the hole side surface is straight, line width controllability can be improved. Also, even if over-etching, the linearity of the bottom of the hole side surface can be maintained,
Excellent line width controllability is maintained.

Further, since the opening of the contact hole 15 is gradually widened, the substantial aspect ratio is reduced even if the contact hole 15 has a pattern size of 1 μm or less. For this reason, when the wiring material is buried in the contact hole 15 in a later step, a sufficient thickness can be given to the wiring material even at the step portion, the value of b / a increases, and the step coverage of the wiring increases. It becomes good and can prevent conduction failure.

The method for forming a contact hole in a semiconductor device according to another embodiment has basically the same steps as the method for forming a contact hole in the semiconductor device according to the embodiment shown in FIG. PEB after 4 (c))
The difference is that a treatment (heat treatment) is performed.

When the exposure wavelength is a single wavelength, the light intensity changes at a period of λ / 4n (λ: wavelength, n: refractive index) due to the effect of the standing wave, so that a wavy pattern is formed on the side wall of the resist pattern 13a. May appear. In the above-described another embodiment, PEB processing is performed after mask exposure in order to mitigate the influence of standing waves, and the resist 13 is developed so that the wavy density distribution of the inhibitor is gentle. As a result, a smooth resist pattern 13a can be formed. According to the process as shown in FIG. 4, the bowl-shaped resist pattern 13a can be formed without performing the PEB process, but the PEB process is more preferable in terms of shape control.

The method for forming a contact hole in a semiconductor device according to still another embodiment has basically the same steps as the method for forming a contact hole in the semiconductor device according to the embodiment shown in FIG. The difference is that a PEB treatment (heat treatment) is performed after (b)).

In the method of forming a contact hole in a semiconductor device according to the above-described still another embodiment, a mask exposure is performed by performing a PEB process after the entire surface exposure. By adjusting the exposure amount at the time of the whole surface exposure, only the surface portion of the resist 13 is strongly exposed and becomes weaker as the resist 13 becomes deeper.
The concentration distribution increases as the depth increases from the surface. As the inhibitor concentration increases, dissolution by development becomes impossible. By performing the PEB process in this state, the distribution of the inhibitor concentration in the resist 13 can be made gentle. Further, the transmittance of light in the resist 13 also changes, so that light in mask exposure becomes easy to enter, so that the amount of mask exposure can be underestimated, and further, the effect of standing waves of light during mask exposure is reduced. be able to.

[0048]

In the contact hole forming method for a semiconductor device according to the present invention as described in detail above, in the photolithography step in manufacturing a semiconductor device, a SiO ₂ film is formed on a substrate, the SiO ₂ A resist was applied on the film by controlling the film thickness so that a node of a standing wave was formed on the resist surface in a subsequent exposure step, and after exposing the entire surface of the resist, a mask having a pattern size of 1 μm or less was used. By developing after performing the mask exposure, a resist pattern having a small size can be formed into a bowl shape having good controllability and reproducibility. Thereby, the SiO 2 of ions in a later reactive ion etching step is formed.
₍₂₎ It is possible to facilitate intrusion into the film and diffusion of the reaction product, to prevent poor etching due to the effect of the microloading effect, and to suppress a decrease in the etch rate. Therefore, even if a pattern size of 1 μm or less is included, uniform etching can be performed, the accuracy of pattern formation can be improved, and a desired fine bowl-shaped contact hole can be formed.

In the contact hole, the line width controllability can be improved because the bottom of the hole side surface is straight. In addition, even if overetching occurs, the linearity of the bottom of the hole side surface can be maintained, and excellent line width controllability can be maintained.

Further, since the opening of the contact hole is gently widened, the substantial aspect ratio is reduced even if the contact hole has a pattern size of 1 μm or less. When a wiring material is embedded in the wiring, a sufficient thickness can be provided even at the stepped portion, the value of b / a can be increased, and the step coverage of the wiring is improved. Therefore, poor conduction can be prevented.

In the above-described method for forming a contact hole in a semiconductor device, when a PEB (Post Exposure Bake) process is performed after the entire surface exposure or the mask exposure,
The inhibitor concentration distribution in the resist after the entire surface exposure and the mask exposure can be made gentle, the line width change rate with respect to the exposure amount can be reduced, and the line width controllability can be improved. For this reason, it becomes easy to produce a finer contact hole.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a bowl-shaped resist pattern.

FIG. 2 is a schematic cross-sectional view showing a state where a wiring material is embedded in a bowl-shaped contact hole according to the present invention.

3A is a schematic cross-sectional view showing a resist pattern without PEB processing, and FIG. 3B is a schematic cross-sectional view showing a resist pattern with PEB processing.

FIGS. 4A to 4E are schematic sectional views showing an embodiment of a method for forming a contact hole in a semiconductor device according to the present invention in the order of steps.

FIG. 5 is a schematic cross-sectional view showing an etching apparatus used in an etching process in a method for forming a contact hole in a semiconductor device according to the present invention.

FIG. 6 shows CF ₄ and CHF in a mixed gas according to the embodiment.
₃ shows the result of examining the relationship between the mixture ratio of ₃ and the etching rate of SiO ₂ and resist, and the result of examining the relationship between the mixture ratio and the selectivity of SiO ₂ to resist.

FIG. 7A is a schematic cross-sectional view showing a contact hole according to an embodiment formed by using a mixed gas having a small selection ratio of SiO _{2 to} a resist, and FIG. 7B is a schematic cross-sectional view showing a large selection ratio. FIG. 4 is a schematic cross-sectional view showing a contact hole according to an embodiment formed using a mixed gas.

FIG. 8A is a schematic cross-sectional view showing a contact hole 15 according to an embodiment subjected to normal etching, and FIG. 8B is a contact hole 15 according to an embodiment overetched. FIG.

FIGS. 9A to 9E are schematic sectional views showing a conventional method for forming a contact hole in a semiconductor device in the order of steps.

FIGS. 10A to 10D are schematic cross-sectional views showing a conventional method for forming a contact hole in another semiconductor device in the order of steps.

FIG. 11 is a graph showing a relationship between a pattern size and an etch rate in a conventional method for forming a contact hole in a semiconductor device.

12A is a schematic cross-sectional view showing a resist pattern having a pattern size of 1 μm or less according to a conventional example, and FIG. 12B is a schematic view showing a contact hole having a pattern size of 1 μm or less according to a conventional example. FIG.

FIG. 13 is a schematic cross-sectional view showing a state where a wiring material is buried in a contact hole according to a conventional example.

FIG. 14 is a schematic cross-sectional view showing a state where a wiring material is embedded in a contact hole according to another conventional example.

[Explanation of symbols]

11 substrate 12 SiO ₂ film 13 resist 13a resist pattern 14 masks 15 contact hole

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21/44-21/445 H01L 29/40-29/43 H01L 29 / 47 H01L 29/872 H01L 21/302 H01L 21/306 H01L 21/3065 H01L 21/461

Claims (2)

(57) [Claims] An SiO ₂ film is formed on a substrate, and the SiO ₂ film is formed on the substrate.
₂ Apply the resist on the film by controlling the film thickness so that the nodes of the standing wave are generated on the resist surface in the subsequent exposure process, apply the entire surface exposure and mask exposure to the resist, and develop the resist. A method for forming a contact hole in a semiconductor device, wherein a reactive ion etching is performed on the SiO ₂ film after forming a pattern, wherein a mask having a pattern size of 1 μm or less is used for the mask exposure. Hole forming method. 2. PEB after overall exposure or mask exposure
2. The method according to claim 1, wherein a post-exposure bake process is performed.