JPH06295877A - Formation of contact hole in semiconductor device - Google Patents

Abstract

PURPOSE:To provide e a method for forming a contact hole on a semiconductor device in which defective etching due to microloading can be prevented while improving the step coverage of wiring without requiring any additional step even if the pattern size is smaller than a specific value and thereby a contact hole 15 having a desired pattern can be formed with high reproducibility and controllability. CONSTITUTION:An SiO2 film 12 is formed on a substrate 11 and a resist 13 is applied thereon while controlling the thickness such that the node of standing wave appears on the resist surface in the exposure step. The resist 13 is then subjected to total surface exposure and mask exposure and then it is developed to form a cup type resist pattern 13a. Subsequently, the SiO2 film 12 is subjected to reactive ion etching thus making a contact hole on the semiconductor substrate. A mask 14 having pattern size of 1mum or less is employed in the mask exposure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly to a method for forming a contact hole in a semiconductor device in which a contact hole is formed by etching a SiO ₂ film in a semiconductor integrated circuit manufacturing process.

[0002]

2. Description of the Related Art Conventionally, in the manufacture of semiconductor devices (semiconductor integrated circuits), photolithography in which a mask pattern is transferred to a resist in order to form a contact hole in a SiO ₂ film formed on the surface of a semiconductor substrate. S with the technique and the patterned resist as a mask
A process combined with an etching technique for processing the iO ₂ film is adopted. As a method of forming the contact hole, a method of combining wet etching and dry etching is also known.

First, a general photolithography and etching process for forming a contact hole is shown in FIG.
It will be described based on. First, S on the Si substrate 31
An iO ₂ film 32 is formed, a resist 33 made of a photosensitive polymer is then applied, and then prebaking is performed to remove the organic solvent contained in the resist 33 (FIG. 9).
(A)). Next, the pattern of the mask 34 is transferred onto the resist 33 by exposure (FIG. 9B), and then the resist 33 is developed to form a resist pattern 33a corresponding to the pattern of the mask 34. Next, post-baking is performed to remove moisture contained in the resist 33 to cure the resist 33 and enhance the adhesiveness with the SiO ₂ film 32 (FIG. 9C). Further, the resist pattern 33
The SiO ₂ film 32 is subjected to reactive ion etching treatment using a as a mask to form a contact hole 35 (FIG. 9D). Next, the unnecessary resist 33 is melted and removed (FIG. 9E). As described above, FIG.
A general photolithography and etching process is composed of five main processes as shown in FIGS.

Next, a method of combining wet etching and dry etching will be described with reference to FIG. In this method, first of all, S is formed on the Si substrate 41.
An iO ₂ film 42 is formed, and a resist 43 made of a photosensitive polymer is applied on the SiO ₂ film 42. After that, pre-baking is performed to remove the organic solvent contained in the resist 43, and a pattern (not shown) on the mask is transferred onto the resist 43 by exposure and then developed. Next, post-baking is performed to cure the resist 43 and enhance the adhesion to the base (FIG. 10A). Further, using the resist 43 as a mask, for example, a 10: 1 BHF solution (H
By wet etching using a mixed solution of F, HNO ₃ , and H ₂ O), the upper portion of the SiO ₂ film 42 is isotropically etched to chamfer (FIG. 10B). After this,
Anisotropic etching is performed by dry etching, and Si
A chamfered pattern is formed on the O ₂ film 42 (FIG. 10).
(C)). Next, the resist 43 that is no longer needed is melted and removed to obtain a bowl-shaped contact hole 45 (FIG. 10D).

[0005]

In recent years, with the miniaturization of wirings and the like in semiconductor devices, it is becoming more and more necessary to obtain a pattern of 1 μm or less, and along with this, the aspect ratio of the pattern is becoming higher. .

In the photolithography and etching process shown in FIG. 9, a rectangular resist pattern 3 is used.
3a is formed. Therefore, the resist pattern 33a
Has a space between wirings of 1 μm or less or a width to be etched (hereinafter referred to as a pattern size) such as a contact hole diameter, the following problems occur during etching. That is, when the pattern size is small as described above, the upper corners of the rectangular resist pattern 33a prevent the etching gas ions from flowing into the pattern, and the etching gas ions are less likely to enter the SiO ₂ film 32. Even if it can penetrate, the reaction products of the ions and the SiO ₂ film 32 are hard to come out from the opening. Therefore, the etching rate becomes slow.
FIG. 11 is a graph showing the relationship between the pattern size and the standardized etch rate, where the etch rate for an infinite pattern size is 1. From FIG. 11, it can be seen that the etch rate gradually decreases as the pattern size decreases with a small pattern size of 1 μm or less. Therefore, for example, a pattern of 2.0 μm size and small patterns of 0.8 μm and 0.6 μm exist in one resist pattern (FIG. 12).
(A)) When the etching process is stopped when the 2.0 μm size pattern is just etched, 0.8
Etching becomes insufficient with the patterns having a size of μm and 0.6 μm (FIG. 12B). Further, if the etching process is performed until the 0.6 μm size portion is sufficiently etched, the etching proceeds too much in the 2.0 μm size pattern portion. Therefore, there is a problem in that etching defects due to the so-called microloading effect described above occur, uniform etching cannot be performed, and a desired pattern size cannot be obtained.

If the aspect ratio of the contact hole 35 is large, the wiring material 36 is formed in the contact hole 35.
Embedded in (FIG. 13), the burying characteristic in the step portion deteriorates, the film thickness of the wiring material 36 in the step portion becomes thin, and the value of b / a becomes small. Therefore, there is a problem that the step coverage of the wiring is deteriorated and the probability of defective conduction increases.

On the other hand, even in the method in which both wet etching and dry etching are used, since the pattern of the resist 43 has a rectangular shape, when the dry etching is performed, S of etching gas ions is generated by the corners of the pattern.
Invasion of the iO ₂ film 42 and release of reaction products are inhibited,
There is a problem that etching failure occurs due to the microloading effect, uniform etching cannot be performed, and a desired pattern size cannot be obtained.

Further, according to this method, a bowl-shaped contact hole 45 is formed by adding an isotropic etching step by wet etching, and the upper portion of the bowl-shaped contact hole 45 is largely opened to form a step portion. Since the slope of is gentle, the practical aspect ratio becomes small. Therefore, as shown in FIG.
Although the burying characteristic when burying 6 is improved, the value of b / a is increased, and the step coverage of the wiring is improved, there is a problem that the number of steps for performing wet etching is increased.

Furthermore, the poor adhesion between the resist 43 and the SiO ₂ film 42, the resist 43 and an etching solution in a horizontal direction from the interface between the SiO ₂ film 42 is penetrated, transversely etching will spread. Therefore, there is a problem that reproducibility and controllability are deteriorated and also disadvantageous in fine processing.

The present invention has been invented in view of the above problems, and even if the pattern size is 1 μm or less, the step coverage of the wiring can be improved without increasing the number of steps, but the micro loading effect can be obtained. An object of the present invention is to provide a method for forming a contact hole in a semiconductor device, which can prevent a defective etching and can form a contact hole having a desired pattern with excellent reproducibility and controllability.

[0012]

In order to achieve the above object, a method of forming a contact hole of a semiconductor device according to the present invention comprises forming a SiO ₂ film on a substrate and exposing a resist on the SiO ₂ film later. In the process, the coating is performed by controlling the film thickness so that a node of a standing wave is generated on the resist surface, the resist is exposed to the whole surface and exposed by a mask and developed to form a bowl-shaped resist pattern, and then the SiO ₂ film is formed. A method for forming a contact hole in a semiconductor device, wherein reactive ion etching is performed on the mask, wherein a mask having a pattern size of 1 μm or less is used for the mask exposure.

Further, the above-mentioned method for forming a contact hole in a semiconductor device is characterized in that PEB (Post Exposure Bake) processing is performed after the whole surface exposure or mask exposure.

[0014]

Since the inhibitor (development inhibitor) in the resist is decomposed by exposing the resist, if the intensity of the overall exposure is adjusted, only the surface of the resist is strongly exposed and the inhibitor concentration becomes small. Developable state. Further, as the depth becomes deeper, the intensity of the exposed light becomes weaker, the inhibitor concentration becomes higher, and the developing becomes impossible. That is, it shows a concentration distribution in which the inhibitor concentration after the whole surface exposure increases as the depth from the surface of the resist increases.

When mask exposure is performed using a mask having a pattern size of 1 μm or less, the resist is irradiated with light only through the opening in the mask exposure, and the light intensity distribution in the opening is close to that at the surface. As a result, the state that can be dissolved by the development is greatly expanded.

By the way, when a standing wave is generated in the resist during exposure, the standing wave on the reflecting surface usually becomes a node,
The belly and the node are alternately present at equal intervals, and the standing wave period L
Is L = λ / 2n [Å] (where the exposure wavelength is λ [Å] and the refractive index of the resist is n). When a node of a standing wave appears on the resist surface, the resist surface is less likely to be dissolved, and after development, a resist pattern 13a having a bowl-shaped cross section as shown in FIG. 1 is formed.

As described above, the SiO ₂ film 12 is formed on the substrate 11.
Is formed, and a resist is applied on the SiO ₂ film 12 while controlling the film thickness so that nodes of standing waves are generated on the resist surface in the subsequent exposure step, and the entire surface of the resist is exposed and a pattern size of 1 μm or less is applied. By performing mask exposure using the above-described mask and developing, it is possible to form a bowl-shaped resist pattern 13a having a pattern size of 1 μm or less and excellent in controllability and reproducibility.

Further, when the SiO ₂ film 12 is subjected to the reactive ion etching treatment using such a bowl-shaped resist pattern 13a, the openings of the resist pattern 13a are gradually expanded, so that the ions are formed in the SiO ₂ film. 12
Even more easily, and the reaction product of the ions and the SiO ₂ film 12 also easily goes out through the opening. Therefore, the etching failure due to the microloading effect is prevented, and the decrease in the etching rate is suppressed. That is, even if the pattern size is reduced, uniform and reliable etching is performed, the accuracy of pattern formation is increased, and a bowl-shaped contact hole having a desired fine pattern can be formed.

Further, in the contact hole, since the side surface bottom portion of the resist pattern 13a is linear, excellent line width controllability is provided. Further, even if overetching is performed, the linearity of the bottom of the side surface of the hole is maintained, and excellent line width controllability is exhibited.

Furthermore, since the bowl-shaped resist pattern 13a is formed without adding an isotropic etching step by wet etching, the number of steps is not increased.

Moreover, since the opening of the contact hole is gradually widened as shown in FIG. 2, even if the contact hole 15 has a pattern size of 1 μm or less, the substantial aspect ratio becomes small. ,
When the wiring material 16 is embedded in the contact hole 15 in a later step, the wiring material 16 in the step portion also has a sufficient thickness, and the value of b / a becomes large. Therefore, the step coverage of the wiring is improved, and defective conduction is prevented.

In the method for forming a contact hole of a semiconductor device described above, when the exposure wavelength is a single wavelength,
Λ / 4n perpendicular to the underlying film due to the effect of standing waves
A wavy pattern may appear on the side wall of the resist 13 due to a change in the light intensity with a cycle of (λ; wavelength, n; refractive index) (FIG. 3A). However, the wavy pattern is also smoothed by performing PEB processing after the whole surface exposure or mask exposure (FIG. 3B), and it is possible to mitigate the influence of the standing wave. Further, the inhibitor concentration distribution in the resist 13 after the whole surface exposure and the mask exposure becomes gentle, and the line width can be easily controlled.
Therefore, a bowl-shaped resist pattern 1 with a smooth surface
3a is formed and the contact hole 15 after etching
It is possible to further improve the pattern controllability.

Moreover, the PEB is exposed before the mask exposure.
When the treatment is applied, the light in the mask exposure is likely to enter, so that the mask exposure amount can be estimated to be small, and the influence of the standing wave of the light in the mask exposure can be mitigated. .

[0024]

EXAMPLES AND COMPARATIVE EXAMPLES Examples and comparative examples of a method for forming a contact hole of a semiconductor device according to the present invention will be described below with reference to the drawings. 4A to 4E are schematic cross-sectional views showing each step for explaining the method of forming the contact hole of the semiconductor device according to the example.

First, an SiO ₂ film 12 is formed on a substrate 11, and then a resist 13 such as PFX15 (manufactured by Sumitomo Chemical Co., Ltd.) is formed on the SiO ₂ film 12 by a standing wave generated in the resist 13. Spin coating is performed with a film thickness of, for example, about 12000Å such that the nodes are located on the surface of the resist 13 (FIG. 4A). Table 1 below shows the relationship between the resist film thickness in which a standing wave is generated and the state of the standing wave on the surface of the resist 13. By utilizing this fact, the film thickness of the resist 13 is controlled so that the vicinity of the node of the standing wave is located on the surface of the resist 13. For example, when the refractive index of the resist 13 is 1.64 and the exposure wavelength is 4360Å (g line), the standing wave period is about 1330Å. Since standing waves become nodes on the surface of the SiO ₂ film, the film thickness is about (1330 k) Å, k is a natural number;
If (see Table 1), the standing wave on the surface of the resist 13 becomes a node.

[0026]

[Table 1]

After that, pre-baking is performed to form the resist 13
The organic solvent contained therein is removed (FIG. 4A). Next, 115 mJ / cm ² is applied on the resist 13 with a stepper.
Of g-line (4360Å) is exposed over the entire surface (Fig. 4).
(B)). The exposure amount at this time is such that the resist 13 is not entirely exposed, that is, the exposure amount is such that a constant film thickness remains. Although g-line (4360Å) was used for exposure, in addition to g-line, h-line (4050Å) and i-line (3650).
Å), KrF (2490 Å), ArF (1930 Å) and other single wavelength exposure sources can be used.

Subsequently, the mask 14 having a pattern size of 1 μm or less is used to perform mask exposure by exposure with a stepper (FIG. 4C). The exposure dose at this time is mask 1
The amount is 45 mJ / cm ^{2 so} that four dimensions can be obtained.

Next, development is carried out, and thereafter, 1 ° C. at 115 ° C.
Performed for 20 seconds post-baking, the resist 13 is cured by skipping the water contained in the resist 13, SiO ₂
The adhesion with the film 12 is enhanced. Thus, a bowl-shaped resist pattern 13a corresponding to the mask 14 is formed (FIG. 4D). Furthermore, this bowl-shaped resist pattern 13
Using SiO ₂ as a mask, the SiO ₂ film 12 is subjected to reactive ion etching to form a contact hole 15 (see FIG. 4).
(E)), the unnecessary resist pattern 13a is removed (FIG. 4 (f)).

The above etching treatment is performed by using Ar (350scc).
RF power: 850 using the apparatus shown in FIG. 5 using a mixed gas of CF ₄ and CHF ₃ with m) as a diluent gas.
W, distance between electrodes: 1.0 cm, sample temperature: −30 ° C., and pressure 500 mTorr.

In the figure, 21 is an upper electrode, 22 is a lower electrode, 23 is a high frequency power source, 24 is a gas inlet, and 25 is a wafer.

O ₂ may be added as an etching gas to the above mixed gas.

Further, although Ar is used as the dilution gas in the above-mentioned embodiment, He or the like can be used as the dilution gas.

FIG. 6 shows CF in the mixed gas according to the embodiment.
Etching was performed by changing the mixing ratio of ₄ and CHF _3, and the result of examining the relationship between the mixing ratio and the etching rate of SiO ₂ and resist and the relationship between the mixing ratio and the selection ratio of SiO _{2 to} the resist were investigated. The results are shown below.

[0035]

[Table 2]

Table 2 shows contact holes 15 (FIG. 7A) according to the embodiment formed by using a mixed gas having a small selection ratio in FIG. 6 during etching, and a mixed gas having a large selection ratio in FIG. The contact hole 15 according to the embodiment (FIG. 7B) formed by the conventional method, the contact hole 35 according to the comparative example (FIG. 9) formed by the conventional photolithography and etching process, and the conventional wet etching and dry etching. A contact hole 45 according to a comparative example formed by a method using etching together (see FIG.
In 0), the results of examining the number of steps, the presence or absence of the influence of the microloading effect, the line width controllability, and the step coverage of the wiring are shown.

As is clear from Table 2, the contact hole 35 according to the comparative example is affected by the microloading effect, the step coverage is considerably deteriorated, and the contact hole 45 according to the comparative example is also affected. , Due to the micro loading effect,
Moreover, the step coverage is poor, and the number of steps is large.
However, in the contact hole 15 according to the embodiment formed by using the mixed gas having a small selection ratio, the line width controllability is excellent, the number of steps is not increased, and the influence due to the microloading effect is eliminated, and the step coverage is achieved. It has also improved significantly. Further, also in the contact hole 15 according to the embodiment using the mixed gas having a large selection ratio, the number of steps is not increased, the influence due to the microloading effect is eliminated, and the line width controllability is excellent. I was able to confirm that it is superior.

Further, FIG. 8A is a schematic sectional view showing the contact hole 15 according to the embodiment subjected to the ordinary etching, and FIG. 8B is related to the embodiment subjected to overetching. FIG. 6 is a schematic cross-sectional view showing a contact hole 15. As is clear from FIG. 8, in the contact hole 15, it is possible to confirm that the linearity of the bottom of the hole side surface is maintained even when overetching, and excellent line width controllability can be exhibited. did it.

As described above, in the method for forming a contact hole of a semiconductor device according to the embodiment, the resist 13 is strongly exposed only to the surface portion and becomes deeper by adjusting the exposure amount during the whole surface exposure. It becomes weakly exposed. In the mask exposure, the opening is strongly exposed, but it is also exposed in the depth direction of the resist 13, and its intensity becomes weaker according to the depth. That is, the inhibitor concentration after the entire surface exposure has a concentration distribution that increases as the depth from the surface of the resist 13 increases. As the inhibitor concentration increases, dissolution by development becomes impossible.

At this time, a resist 13 is applied on the SiO ₂ film 12 while controlling the film thickness so that nodes of standing waves are generated on the resist surface in a subsequent exposure process, and after the entire surface is exposed, the resist 13 is applied from above the resist 13. Mask exposure is performed using a mask 14 having a pattern size of 1 μm or less. By combining the whole surface exposure and the mask exposure, the resist 13 is exposed with a bowl-shaped intensity distribution, and the small resist pattern 13a having a size of 1 μm or less is formed into a bowl shape with good controllability and reproducibility. You can

Further, since the resist pattern 13a has a bowl shape, etching gas ions easily penetrate into the SiO ₂ film 12 in the subsequent etching step, and etching defects due to the influence of the microloading effect are prevented. However, a decrease in the etch rate can be suppressed. Therefore, even if a pattern having a size of 1 μm or less is included, uniform etching can be performed,
The accuracy of pattern formation can be improved, and a desired fine bowl-shaped contact hole 15 can be formed.

Further, in the contact hole 15,
Since the hole side surface bottom portion is linear, the line width controllability can be improved. Also, even if overetching is performed, the linearity of the bottom of the side surface of the hole can be maintained,
Excellent line width controllability is maintained.

Further, since the opening of the contact hole 15 is gently expanded, the substantial aspect ratio is reduced even if the contact hole 15 has a pattern size of 1 μm or less. Therefore, when the wiring material is embedded in the contact hole 15 in a later step, the wiring material can have a sufficient thickness even in the step portion, the value of b / a becomes large, and the step coverage of the wiring is improved. It becomes good, and the conduction failure can be prevented.

A method of forming a contact hole of a semiconductor device according to another embodiment basically has the same steps as the method of forming a contact hole of a semiconductor device according to the embodiment shown in FIG. 4 (c)) followed by PEB
The difference is that a treatment (heat treatment) is performed.

When the exposure wavelength is a single wavelength, the light intensity changes at a cycle of λ / 4n (λ: wavelength, n: refractive index) under the influence of a standing wave, so that a wavy pattern is formed on the side wall of the resist pattern 13a. It may appear. In the above-described another embodiment, PEB treatment is performed after mask exposure to alleviate the effect of standing waves, and development is performed with a gentle wavy density distribution of the inhibitor in the resist 13. As a result, a smooth resist pattern 13a can be formed. According to the process as shown in FIG. 4, the bowl-shaped resist pattern 13a can be formed without performing the PEB treatment, but the PEB treatment is more preferable from the viewpoint of shape control.

A contact hole forming method for a semiconductor device according to still another embodiment basically has the same steps as the contact hole forming method for a semiconductor device according to the embodiment shown in FIG. The difference is that PEB treatment (heat treatment) is performed after (b)).

In the method of forming a contact hole of a semiconductor device according to another embodiment described above, mask exposure is performed by performing PEB processing after the entire surface exposure. By adjusting the exposure amount during the whole surface exposure, the resist 13 is strongly exposed only at the surface portion and weakly exposed as it becomes deeper. Therefore, the inhibitor concentration after the whole surface exposure is the resist 13
It shows a concentration distribution in which the concentration increases as it goes deeper from the surface, and the higher the inhibitor concentration, the more indissolvable it is by development. By performing PEB processing in this state, the inhibitor concentration distribution in the resist 13 can be made gentle. Further, the transmittance of light in the resist 13 also changes, and the light in the mask exposure is likely to enter, so that the mask exposure amount can be underestimated, and the influence of the standing wave of light during the mask exposure can be mitigated. be able to.

[0048]

In the contact hole forming method for a semiconductor device according to the present invention as described in detail above, in the photolithography step in manufacturing a semiconductor device, a SiO ₂ film is formed on a substrate, the SiO ₂ A resist was applied on the film while controlling the film thickness so that nodes of standing waves were generated on the resist surface in the subsequent exposure step, and after exposing the entire surface of the resist, a mask having a pattern size of 1 μm or less was used. By developing after performing mask exposure, a resist pattern having a small size can be formed into a bowl shape having good controllability and reproducibility. As a result, ions of the SiO 2 in the subsequent reactive ion etching step are
It is possible to facilitate the penetration into the _two films and the diffusion of reaction products, prevent the etching failure due to the influence of the microloading effect, and suppress the decrease in the etching rate. Therefore, even if a pattern size of 1 μm or less is included, uniform etching can be performed, the accuracy of pattern formation can be improved, and a desired fine bowl-shaped contact hole can be formed.

Further, in the contact hole, since the bottom of the side surface of the hole is straight, the line width controllability can be improved. Further, even if overetching is performed, the linearity of the bottom of the side surface of the hole can be maintained, and excellent line width controllability can be maintained.

Further, since the opening of the contact hole is gently expanded, the substantial aspect ratio is reduced even if the contact hole has a pattern size of 1 μm or less, and the contact hole is formed in a later step. When the wiring material is embedded in the wiring, a sufficient thickness can be provided even in the step portion, the value of b / a can be increased, and the step coverage of the wiring becomes good. Therefore, conduction failure can be prevented.

In the method of forming a contact hole for a semiconductor device described above, when PEB (Post Exposure Bake) processing is performed after the whole surface exposure or mask exposure,
The inhibitor concentration distribution in the resist after the whole surface exposure and the mask exposure can be made gentle, the rate of change in the line width with respect to the exposure amount can be reduced, and the line width controllability can be improved. Therefore, it becomes easier to fabricate a finer contact hole.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a bowl-shaped resist pattern.

FIG. 2 is a schematic cross-sectional view showing a state in which a wiring material is embedded in a bowl-shaped contact hole according to the present invention.

3A is a schematic cross-sectional view showing a resist pattern without PEB treatment, and FIG. 3B is a schematic cross-sectional view showing a resist pattern with PEB treatment.

4A to 4E are schematic cross-sectional views showing an embodiment of a method of forming a contact hole of a semiconductor device according to the present invention in the order of each step.

FIG. 5 is a schematic cross-sectional view showing an etching apparatus used in an etching treatment step in the method for forming a contact hole of a semiconductor device according to the present invention.

FIG. 6 shows CF ₄ and CHF in a mixed gas according to an embodiment.
₃ shows the results of examining the relationship between the mixing ratio with ₃ and the etching rate of SiO ₂ and the resist, and the results of examining the relationship between the mixing ratio and the selection ratio of SiO _{2 to} the resist.

7A is a schematic cross-sectional view showing a contact hole according to an example formed by using a mixed gas of SiO ₂ having a small selection ratio with respect to a resist, and FIG. 7B is a schematic cross-sectional view showing the contact hole having a large selection ratio. It is a schematic cross-sectional view showing a contact hole according to an example formed using a mixed gas.

8A is a schematic cross-sectional view showing a contact hole 15 according to an example in which normal etching is performed, and FIG. 8B is a contact hole 15 according to an example in which overetching is performed. It is a schematic cross-sectional view showing.

9A to 9E are schematic cross-sectional views showing a conventional method of forming a contact hole in a semiconductor device in the order of steps.

10A to 10D are schematic cross-sectional views showing a contact hole forming method for another conventional semiconductor device in the order of steps.

FIG. 11 is a graph showing the relationship between the pattern size and the etch rate in the conventional method of forming a contact hole in a semiconductor device.

12A is a schematic cross-sectional view showing a resist pattern having a pattern size of 1 μm or less according to a conventional example, and FIG. 12B shows a contact hole having a pattern size of 1 μm or less according to the conventional example. It is a typical sectional view.

FIG. 13 is a schematic cross-sectional view showing a state in which a wiring material is embedded in a contact hole according to a conventional example.

FIG. 14 is a schematic cross-sectional view showing a state in which a wiring material is embedded in a contact hole according to another conventional example.

[Explanation of symbols]

11 substrate 12 SiO ₂ film 13 resist 13a resist pattern 14 mask 15 contact hole

Claims (2)

[Claims] 1. A SiO ₂ film is formed on a substrate, and the SiO ₂ film is formed.
₍₂ ) A resist is applied on the film by controlling the film thickness so that nodes of standing waves are generated on the resist surface in the subsequent exposure process, and the resist is subjected to overall exposure and mask exposure to develop, and a bowl-shaped resist A method of forming a contact hole in a semiconductor device, wherein a reactive ion etching is performed on the SiO ₂ film after forming a pattern, wherein a mask having a pattern size of 1 μm or less is used for the mask exposure. Hole formation method. 2. PEB after whole surface exposure or mask exposure
The method for forming a contact hole in a semiconductor device according to claim 1, wherein a (Post Exposure Bake) process is performed.