JPS63117422A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a resist pattern high in an aspect ratio and a dry etching resistant property and excellent in verticality, by using multilayer resists and irradiating and developing a lower layer high-molecular film collectively with ions while using an upper resist as a mask. CONSTITUTION:A semiconductor substrate 10 is spin-coated with a PMMA resist 11, a spin-on glass SOG 12, and a novolak group resist 13 serially so that hot plate baking is performed. After the exposure for a resist pattern is performed by the use of a reduced projection exposure device, a resist pattern 13A is developed/formed by an organic alkaline developing liquid. While this pattern 13A is used as a mask, reactive ion etching is performed to form a SOG pattern 12A. An ion beam radiation device is used to radiate H<+> ion beams 14. When a wafer is developed by the developing liquids of MIBK and IPA, a resist pattern profile 11A high in an aspect ratio and excellent in verticality can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that involves ion implantation.

BACKGROUND OF THE INVENTION In recent years, the degree of integration of semiconductor integrated circuits has been increasing at a rate of doubling every two years, and the linkage technology that is the driving force behind this increase is becoming increasingly important. Using a resist pattern formed by this phosphorography technique as a mask, reactive ion etching, reactive ion beam etching, etc. are performed in order to accurately transfer the dry etching dimensions of a semiconductor substrate onto a semiconductor substrate. However, as miniaturization progresses further into the submicron or smaller region, the etching shape will become largely dependent on the cross-sectional shape of the resist. Therefore, there is an increasing demand for vertical resist patterns and higher aspect ratios. In addition, silicon trench etching etc.
When cracking the grooves, a resist with excellent dry etch resistance is required. In response to these demands, in order to increase the aspect ratio, reactive ion etching of the lower layer resist is performed using a multilayer resist and an inorganic film as a mask. Furthermore, a pattern with a high aspect ratio is obtained by exposing the entire surface of the lower resist using an inorganic film as a mask and developing it.

Problems to be Solved by the Invention However, when these methods are specifically applied to semiconductor processes, the throughput is extremely poor when etching the lower layer resist, and over-etching causes the resist to become slender and the cross section to be distorted. There was a problem with the verticality of the shape. Also, in the case of full exposure of the lower resist layer,
Since the cross-sectional shape depends on the development time, there is a problem that the cross-sectional shape becomes thin when the development time is long. Further, when etching a deep groove such as a silicon trench etching, there is a problem in that unless a resist with excellent dry etching resistance is used, the etched shape changes or the resist disappears.

Means to Solve the Problems Therefore, in order to solve the above problems, the present invention uses a multilayer resist, uses the upper resist as a mask, and develops the lower polymer film by ion irradiation at once, thereby creating a vertical, high aspect ratio film. This results in a resist pattern of . Moreover, at the same time, a resist pattern with high dry etch resistance can be obtained.

Function: According to the present invention, as described above, a vertical resist pattern with a high aspect ratio can be obtained with high throughput and with little dependence on development time. In addition, especially in the case of electron beam resists with high aspect ratios and difficult to obtain vertical resist patterns, by using the present invention, fine patterns formed on the upper layer resist can be vertically transferred to the lower layer electron beam resists with a high aspect ratio. . At this time, the upper resist layer is irradiated with ions and has improved dry etching resistance, so it functions effectively as a mask for dry etching of the semiconductor substrate. As a result, it is possible to cope with higher integration of semiconductor integrated circuit patterns.

Embodiment An embodiment of the present invention is shown in FIG. A PMM (polymethyl methacrylate) resist 11 with a thickness of 0.6 to 1 μm is coated on the semiconductor substrate 1o after cleaning with a spin coating at 0°C.
Perform open baking for 0 minutes. On top of that, spin-on glass 5OG (coated SiO□ film) 12 was applied at 0.1μ
After baking at 160'C for 30 minutes, a photoresist, i.e. novola, was applied as the top resist.
11tWl thick spin code L,
Hot plate baking at 100'C for 1 minute (Figure 1a). A desired resist pattern is exposed using a reduction projection exposure apparatus, and then developed with an organic alkaline developer to form a resist pattern 13. Using this resist pattern 13 as a mask, the intermediate layer 5OG 12 is etched by reactive ion etching to form an SOG pattern 12 (FIG. 1b).

Using an ion beam irradiation device, H+ ion beam 14
7×1015 pieces are irradiated at once at an accelerating voltage of 40 KeV. 15 is the H+ ion irradiation area (FIG. 1C). P
When the MM wafer is irradiated with 7 x 10" of H+Iyl-7/d, the molecular weight is reduced and becomes soluble in a developer consisting of a mixture of MIBK (methyl isobutyl ketone) and IP (isopropyl alcohol), so this wafer is MIBIC and I
When the resist pattern is developed with a developer containing P, a resist pattern profile 11 with a high aspect ratio and good verticality can be obtained (FIG. 1d).

In the above embodiment, a photoresist is used as the upper resist, but the upper resist pattern may of course be formed using electron beam cyst. Furthermore, in this example, SOG was used as the intermediate layer of the three-layer resist.
Other inorganic films such as 5in2°W may also be used. In addition, the lower resist layer was irradiated with H+ ions to break the polymer bonds and lower the molecular weight, making it soluble in the developer, but inorganic ions such as P and B other than C ions, or mulch, etc. The same thing can be done by irradiating with inert gas ions.

A second embodiment of the invention is shown in FIG. Low molecular weight PMM Muresyst 21 with low sensitivity is placed on the semiconductor substrate 10 after cleaning.
The sample was spin-coated to a thickness of 0.6 μm to 1 μm and open baked at 170′C for 20 minutes. Furthermore, a highly sensitive high molecular weight PMM Muresyst 22 is spin-coded to a thickness of 1 μm on top of this, and open baking is performed at 170″C for 20 minutes (Fig. 2). After exposing a desired circuit pattern to light, it is developed with a developer of MIBK and IP to form a resist pattern 22 (FIG. 2b).Then, H+ ions 14 are 7×10
2/d-batch irradiation is performed.

15 is the U+4 on irradiation area (Fig. 2 0), and the low molecular weight PMM murecist of the lower layer resist is 7×1o1
It becomes soluble in the developer at a dose of 3 particles/d, and a vertical resist pattern 21A with a high aspect ratio can be formed (FIG. 2d). On the other hand, the high molecular weight P of the upper resist layer
MM Muresyst exhibits insolubility in the developer at the same dose, and the etching rate for 0□ is slow, resulting in improved dry etch resistance. As described above, it is possible to form a vertical fine resist pattern of PMMA, which has poor dry etch resistance, with a high aspect ratio and high dry etch resistance, using an electron beam resist. Using this resist pattern as a mask, 6 μm of the semiconductor substrate 1o is
Perform 7 proboscises and 7 proboscises. The improved dry etch resistance of the resist improves the selectivity during trench etching and eliminates the need for resist. Furthermore, since the resist pattern is vertical and has a high aspect ratio, the trench can also have a vertical shape (FIG. 2e).

In the second example, high molecular weight PMMA was used for the upper resist layer, which is an electron beam resist with high sensitivity.

It may also be a photoresist. Further, although low molecular weight PMMA is used for the lower resist layer, an electron beam resist or photoresist having lower sensitivity than the upper layer resist may be used.

Effects of the Invention According to the present invention, a fine pattern with good verticality and a high aspect ratio can be formed by irradiating a resist with ions. Further, the dry etch resistance of the resist can also be improved, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view of a first embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a process sectional view of the second embodiment. 10... Semiconductor substrate, 11... PMM
Muresist, 12... Spin-on glass (SO
G), 13...Novolak resist, 14.
...H+ ion, 16...H+ ion irradiation area, 21...Low molecular weight PMMA resist,
22...High molecular weight PMMA resist. Name of agent: Patent attorney Toshio Nakao and 1 other person10
--Ichihan exclusive M2 tile + 3--ri Jζu, 2 screens, resist to---jp! Rice board Fig. 2 - “ce) tF, q”’22... - Akane II

Claims (4)

[Claims] (1) A step of applying a polymer film on a semiconductor substrate, forming an inorganic film on the polymer film, and applying a resist on the inorganic film, and forming a semiconductor circuit pattern by exposing and developing the resist. a step of etching the inorganic film by reactive ion etching using the resist pattern as a mask; and a step of irradiating the polymer film with inorganic ions or inert gas ions at once using the resist pattern as a mask, and then developing. A method for manufacturing a semiconductor device, comprising the steps of: (2) As inorganic ions or inert gas ions,
2. The method of manufacturing a semiconductor device according to claim 1, using H, P, B, or Ar ions. (3) a step of applying a lower layer resist on the semiconductor substrate;
applying an upper layer resist on the lower layer resist;
A semiconductor comprising the steps of: exposing and developing the upper resist to form a semiconductor circuit pattern; and using the upper resist pattern as a mask, irradiating the lower resist with inorganic ions or inert gas ions at once, and then developing. Method of manufacturing the device. (4) The method for manufacturing a semiconductor device according to claim 3, wherein a high-sensitivity resist is used as the upper layer resist and a low-sensitivity resist is used as the lower layer resist.