JPS6035821B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS6035821B2
JPS6035821B2 JP50072593A JP7259375A JPS6035821B2 JP S6035821 B2 JPS6035821 B2 JP S6035821B2 JP 50072593 A JP50072593 A JP 50072593A JP 7259375 A JP7259375 A JP 7259375A JP S6035821 B2 JPS6035821 B2 JP S6035821B2
Authority
JP
Japan
Prior art keywords
electron beam
wiring
layer
electrode
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50072593A
Other languages
Japanese (ja)
Other versions
JPS51148369A (en
Inventor
公雄 柳田
憲一 川島
保隆 伴
敬治 島
雄史 稲垣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP50072593A priority Critical patent/JPS6035821B2/en
Publication of JPS51148369A publication Critical patent/JPS51148369A/en
Publication of JPS6035821B2 publication Critical patent/JPS6035821B2/en
Expired legal-status Critical Current

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  • Electron Beam Exposure (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造に於ける写真触刻工程で電子
線照射技術を用いた場合、そこで触刻用に用いた電子線
レジストをそのまま絶縁物として利用する事により工程
の短縮を計り、又微細加工技術を利用する方法に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides that when electron beam irradiation technology is used in the photolithography process in the manufacture of semiconductor devices, the electron beam resist used for engraving can be used as is as an insulator. The present invention relates to a method of shortening the process and utilizing microfabrication technology.

半導体装置の製造に用いて来られたフオトレジストは、
耐薬品(無機系の酸)性にはすぐれているが、耐熱性、
耐湿性等で劣り、単に写真蝕刻工程に於てのみ使われ得
て、半導体装置の構成材料とはなり得ない。
Photoresists used in the manufacture of semiconductor devices are
It has excellent chemical resistance (inorganic acids), but it has poor heat resistance,
It has poor moisture resistance and can only be used in photo-etching processes, and cannot be used as a constituent material for semiconductor devices.

その為酸化シリコン等を絶縁物として用い、又電極窓の
微小化、配線間隔の微細化に伴い、蝕刻は高度の技術が
要求されたレジストも又一層困難な使用条件に耐えなけ
ればならない。本発明はこの欠点を改良し、工程短縮を
し且つ微細加工を可能ならしめる事を目的とする。
For this reason, silicon oxide or the like is used as an insulator, and with the miniaturization of electrode windows and miniaturization of interconnect spacing, resists that require advanced etching techniques must also withstand even more difficult usage conditions. The present invention aims to improve this drawback, shorten the process, and enable microfabrication.

この目的は、本発明によれば電子線レジストを写真蝕刻
工程に用いたあとそのまま絶縁物として残す事により達
成される。更に電子線で感光させる場合、光と異り、加
速電圧によっては、アルミニウム等の配線用金属膜を透
過してその下に敷かれた電子線レジストを感光させる事
も可能である。
This object is achieved according to the invention by leaving the electron beam resist as an insulator after it is used in a photolithographic process. Furthermore, when exposing with an electron beam, unlike light, depending on the accelerating voltage, it is possible to transmit the electron beam through a wiring metal film such as aluminum and expose the electron beam resist laid thereunder.

その実施例を図によって説明する。第1図は1が半導体
基板で、2はェミッター等電極形成を必要とする場所で
あり、第2図ではすでに一層目の電極配線が終ったあと
の電極の断面図を簡略化して示してある。
An example thereof will be explained with reference to the drawings. In Figure 1, 1 is the semiconductor substrate, 2 is the place where electrodes such as emitters need to be formed, and Figure 2 shows a simplified cross-sectional view of the electrode after the first layer of electrode wiring has already been completed. .

即ち3が配線断面である。第1図、第2図に示された場
合、或は更に第3層目の配線に於ける場合も同じ方式が
適用できるので、以後の工程は第1図を用いて説明する
。第1図に示された構造の上に、当該電子線レジスト4
を塗布し、電極形成に必要な箇所をレジストのみ蝕刻す
る。然る後、アルミニウム等電極層を蒸着等で作り、写
真蝕刻を行って配線パターンを形成する(第3図)。
That is, 3 is the wiring cross section. The same method can be applied to the cases shown in FIGS. 1 and 2, or even to the third layer of wiring, so the subsequent steps will be explained using FIG. 1. The electron beam resist 4 is placed on the structure shown in FIG.
Then, the resist is etched only in the areas necessary for electrode formation. Thereafter, an electrode layer such as aluminum is formed by vapor deposition or the like, and a wiring pattern is formed by photolithography (FIG. 3).

そのあと電極配線の形状を保つのに必要の場所のみ電子
線レジストが残る様に電極の上から電子線を照射し、第
4図で示された如く不要な部分6を取り除く。これによ
り電子線レジストが有する誘電率で定まる配線容量が大
中に縮少され素子動作の高速化に寄与する。
Thereafter, an electron beam is irradiated from above the electrode so that the electron beam resist remains only in the areas necessary to maintain the shape of the electrode wiring, and unnecessary portions 6 are removed as shown in FIG. This greatly reduces the wiring capacitance determined by the dielectric constant of the electron beam resist, contributing to faster device operation.

以上述べた如く、本発明の半導体装置の製造方法によれ
ば微細加工、工程の短縮、配線容量の減少による素子動
作の高速化等を達成する事ができる。
As described above, according to the method of manufacturing a semiconductor device of the present invention, it is possible to achieve fine processing, shortening of process steps, and high-speed device operation due to reduction in wiring capacitance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第4図は本発明の方法を示す図で、第1図は
所定の接合を形成した半導体基板の断面図、第2図はこ
の基板に一層目の配線を施したときの断面図、第3図は
層間絶縁用の電子線レジストを塗布し、電極窓あげを行
ない、配線パターンを形成したときの断面図、第4図は
電子線露光を行なって不要な電子線レジストを除去した
ときの基板の断面図である。 図中、1は半導体基板、2は電極を設けるべき領域、3
は一層目配線、4は電子線レジスト、5は上部配線、6
はしジスト除去部分である。 オ1図オ2図 才3図 矛ム図
1 to 4 are diagrams showing the method of the present invention, in which FIG. 1 is a cross-sectional view of a semiconductor substrate on which a predetermined bond has been formed, and FIG. 2 is a cross-sectional view when the first layer of wiring is applied to this substrate. Fig. 3 is a cross-sectional view after applying an electron beam resist for interlayer insulation, raising the electrode window, and forming a wiring pattern, and Fig. 4 is a cross-sectional view when electron beam resist is applied for interlayer insulation, and unnecessary electron beam resist is removed by electron beam exposure. FIG. In the figure, 1 is a semiconductor substrate, 2 is a region where an electrode is to be provided, and 3 is a semiconductor substrate.
is the first layer wiring, 4 is the electron beam resist, 5 is the upper wiring, 6
This is the part where the sting is removed. Figure 1, Figure 2, Figure 3, Figure 3.

Claims (1)

【特許請求の範囲】[Claims] 1 感電子線材料層を半導体基板上に形成した後、上記
感電子線材料層上に導体層を被着しパターニングした配
線層を形成し、次いで上記配線層の上から電子線を照射
して上記配線層下に上記感電子線材料層を部分的に残留
させる工程を含むことを特徴とする半導体装置の製造方
法。
1. After forming an electron beam-sensitive material layer on a semiconductor substrate, a conductor layer is deposited on the electron beam-sensitive material layer and a patterned wiring layer is formed, and then an electron beam is irradiated from above the wiring layer. A method for manufacturing a semiconductor device, comprising a step of partially leaving the electron beam sensitive material layer under the wiring layer.
JP50072593A 1975-06-14 1975-06-14 Manufacturing method of semiconductor device Expired JPS6035821B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50072593A JPS6035821B2 (en) 1975-06-14 1975-06-14 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50072593A JPS6035821B2 (en) 1975-06-14 1975-06-14 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS51148369A JPS51148369A (en) 1976-12-20
JPS6035821B2 true JPS6035821B2 (en) 1985-08-16

Family

ID=13493839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50072593A Expired JPS6035821B2 (en) 1975-06-14 1975-06-14 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6035821B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS644729U (en) * 1987-06-29 1989-01-12
JPH0412892Y2 (en) * 1986-07-31 1992-03-26
JPH0423937B2 (en) * 1986-01-20 1992-04-23 Gantan Beauty Kogyo Kk

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130192Y2 (en) * 1976-11-02 1986-09-04

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4934018A (en) * 1972-07-31 1974-03-29

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4934018A (en) * 1972-07-31 1974-03-29

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0423937B2 (en) * 1986-01-20 1992-04-23 Gantan Beauty Kogyo Kk
JPH0412892Y2 (en) * 1986-07-31 1992-03-26
JPS644729U (en) * 1987-06-29 1989-01-12

Also Published As

Publication number Publication date
JPS51148369A (en) 1976-12-20

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