JPS59177930A - Pattern formation of semiconductor device - Google Patents
Pattern formation of semiconductor deviceInfo
- Publication number
- JPS59177930A JPS59177930A JP5151683A JP5151683A JPS59177930A JP S59177930 A JPS59177930 A JP S59177930A JP 5151683 A JP5151683 A JP 5151683A JP 5151683 A JP5151683 A JP 5151683A JP S59177930 A JPS59177930 A JP S59177930A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- deposited layer
- irradiation
- polycrystalline silicon
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 230000007261 regionalization Effects 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 37
- 230000005855 radiation Effects 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 23
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 27
- 238000010894 electron beam technology Methods 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 238000002425 crystallisation Methods 0.000 abstract description 2
- 230000008025 crystallization Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 9
- 239000010409 thin film Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000002245 particle Substances 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000011856 silicon-based particle Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明はレジストを用いない半導体装置の・ぐターン形
成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for forming patterns in a semiconductor device without using a resist.
（従来技術）
一般に半導体装置の製造に当たシ、いわゆるマスキング
技術が用いられている。このマスキング技術にはレジス
トを用い、このレジストニックターンを形成しこのパタ
ーン成形されたレジストをマスクとして用いて下側に存
在する層例えば半導体層又は絶縁層に対しエツチング、
ドーぎングその他生導体装置の製造に必要な処理を所要
に応じて行っている。(Prior Art) Generally, a so-called masking technique is used in manufacturing semiconductor devices. This masking technique uses a resist, forms a resist nick turn, and uses the patterned resist as a mask to etch the underlying layer, such as a semiconductor layer or an insulating layer.
Doging and other processes necessary for manufacturing raw conductor devices are performed as required.
第１図Ａ−Ｄは従来の半導体装置の・ぐターン形成方法
の典型例を示す工程図で、特にシリコンケ゛−） ＭＯ
８半導体装置のダートのパターン形成（以ＴＶに・母タ
ーニングと称する）工程を示す。この従来のパターニン
グ方法では第１図Ａに示す如く半導体層ｌ上にダート酸
化膜２を形成し、このケ８−ト酸化膜２上に多結晶シリ
コンを堆積させて堆積層３を形成し、この堆積層゛３を
・やターニングしようとするものである。その場合、第
１図Ｂに示す如くこの堆積層３上にレジスト４を塗布す
る。FIGS. 1A to 1D are process diagrams showing a typical example of a conventional method for forming a pattern in a semiconductor device.
8 shows the step of forming a dirt pattern (hereinafter referred to as mother turning) of a semiconductor device. In this conventional patterning method, as shown in FIG. 1A, a dirt oxide film 2 is formed on a semiconductor layer 1, and polycrystalline silicon is deposited on this dirt oxide film 2 to form a deposited layer 3. The purpose is to slightly turn this deposited layer 3. In that case, a resist 4 is applied on the deposited layer 3 as shown in FIG. 1B.
其の後このレノスト１４に対しガラスマスクを通して放
射例えは紫外線を照射することによりこのレジスト４を
選択的に重合させる。其の後第１図Ｃに示す如く、この
レジスト・４を現像することにょｐこのレジストのパタ
ーン成形を行う。次に第１図りに示す如く、このパター
ン成形されたレジス１−４をマスクとして下側の多結晶
シリコンの堆積層３のエツチングを行うものである。Thereafter, the resist 4 is selectively polymerized by irradiating the resist 14 with radiation, such as ultraviolet light, through a glass mask. Thereafter, as shown in FIG. 1C, this resist 4 is developed to form a pattern. Next, as shown in the first diagram, the lower deposited polycrystalline silicon layer 3 is etched using the patterned resist 1-4 as a mask.
この従来の・ぐターニング方法では多結晶シリコンの堆
積層にレジストを塗布し、このレジスタをマスクとして
堆積層をエツチングするのであるから、この堆積層とレ
ジストとの密着性に起因してサイドエツチングが生ずる
。このサイドエツチングは、其の後に半導体層１にソー
ス及びドレイン領域を形成する際に、実効ケ゛−ト長に
バラツキを生ずる原因と々る。In this conventional turning method, a resist is applied to the deposited layer of polycrystalline silicon, and the deposited layer is etched using the resist as a mask. Therefore, side etching occurs due to the adhesion between the deposited layer and the resist. arise. This side etching is one of the causes of variations in the effective gate length when source and drain regions are subsequently formed in the semiconductor layer 1.
さらに、紫外線を用いてレジスタのパターニングを行う
工程で光の回折、多重反射効果等によシガラスマスク・
ぐターンとの寸法変換差が生じ、精密な・ぐターニング
が行え々いという欠点がある。Furthermore, in the process of patterning resistors using ultraviolet rays, light diffraction, multiple reflection effects, etc.
It has the disadvantage that there is a difference in dimensional conversion between the turning and the turning, making it difficult to perform accurate turning.
さらに、レジストを使用する方法はレジストが有機物で
あることから、其の後の工程に進む前にこれを十分に洗
浄する必要があシ、その分の処理工程が余分に必要とな
る欠点がある。Furthermore, since the resist is an organic substance, methods that use resist require thorough cleaning before proceeding to subsequent steps, which has the disadvantage of requiring additional processing steps. .
（発明の目的）
本発明の目的は上述した従来のパターニング方法の欠点
を除去するため、レジストを用いずに堆積層のエツチン
グを行って・ぐターン成形を行う半導体装置のパターン
形成方法を提供することにある。(Object of the Invention) In order to eliminate the drawbacks of the conventional patterning methods described above, an object of the present invention is to provide a pattern forming method for a semiconductor device in which a deposited layer is etched without using a resist and pattern formation is performed. There is a particular thing.
（発明の構成）
この目的の達成を図るため、本発明の半導体装置のパタ
ーン形成方法によれば、基層上の堆積層に対し放射を選
択的に照射し、この放射の照射を受けた堆積層部分と、
放射の照射を受けなかった堆積層部分とのエツチング速
度の差を利用してこの堆積層をエツチングしてパターン
成形することを特徴とする。(Structure of the Invention) In order to achieve this object, according to the pattern forming method for a semiconductor device of the present invention, a deposited layer on a base layer is selectively irradiated with radiation, and the deposited layer irradiated with the radiation is part and
The method is characterized in that the deposited layer is etched to form a pattern by utilizing the difference in etching rate between the deposited layer and the portion that has not been irradiated with radiation.
（実施例） 以下図面につき本発明の実施例を詳述する。(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.
第２図Ａ−Ｃは本発明のノやターン形成方法の一実施例
を説明するための工程図である。この工程図はシリコン
ケゞ−）ＭＯ８半導体装置のダート多結晶シリコンのパ
ターニング工程を一例として示す図で、１１はシリコン
ウェーハのような半導体層（又は半導体薄膜ともいう）
、１２はダート酸化膜、１３はケゞ−ト多結晶シリコン
層、１４はこの多結晶シリコン中の放射の照射を受けた
部分、１５はレーザビーム又は電子線等のいわゆる放射
、１６は放射の照射を受けなかった部分、１７はケ゛−
ト電極となる部分である。FIGS. 2A to 2C are process diagrams for explaining one embodiment of the method for forming grooves and turns of the present invention. This process diagram shows, as an example, the patterning process of dirt polycrystalline silicon for a MO8 semiconductor device, and 11 is a semiconductor layer (or also called a semiconductor thin film) such as a silicon wafer.
, 12 is a dirt oxide film, 13 is a gate polycrystalline silicon layer, 14 is a portion of this polycrystalline silicon that is irradiated with radiation, 15 is a so-called radiation such as a laser beam or an electron beam, and 16 is a radiation irradiation layer. The part that was not irradiated, 17, is a cage.
This is the part that becomes the top electrode.
先ず第２図Ａに示す如く、シリコンウェーハ・１１の活
性領域と々る領域の上側にダート酸化膜１２を形成し、
次いでこのダート酸化膜１２上にゲート多結晶シリコン
層１３を堆積させる。この実施例では、このダート多結
晶シリコン層１３をパターニングするのであるから、こ
のダート酸化膜１２が基層に対応し、ダート多結晶シリ
コン層１３がパターン成形されるべき堆積層と々る。First, as shown in FIG. 2A, a dirt oxide film 12 is formed on the upper side of the active region of the silicon wafer 11.
Next, a gate polycrystalline silicon layer 13 is deposited on this dirt oxide film 12. In this embodiment, since the dirt polycrystalline silicon layer 13 is patterned, the dirt oxide film 12 corresponds to the base layer, and the dirt polycrystalline silicon layer 13 corresponds to the deposited layer to be patterned.
次に第２図Ｂに示す様にこの堆積層１３に対し所定のパ
ターンに従ってレーザビーム又は電子線等の放射１５で
堆積層１３を選択的に照射する。Next, as shown in FIG. 2B, the deposited layer 13 is selectively irradiated with radiation 15 such as a laser beam or an electron beam according to a predetermined pattern.
この放射の照射を受けた堆積層である多結晶シリコン層
の部分１４は多結晶シリコンの粒子が増大し結晶化が進
み、これがため放射の照射を受けてい彦い他の残りの多
結晶シリコン層部分１６に比（５）
べてエツチング速度が極めて遅くなる。In the portion 14 of the polycrystalline silicon layer which is the deposited layer irradiated with this radiation, the particles of polycrystalline silicon increase and crystallization progresses, and therefore the remaining polycrystalline silicon layer is not irradiated with radiation. The etching speed is extremely slow compared to portion 16 (5).
第２図Ｃはこのよう々エツチング速度の差を利用して、
第２図Ｂに示す放射照射後の堆積層３に対しウェット又
はドライエツチング法によシエッチングを施して得られ
た状態を示す図である。この図からも明らか々様に、こ
のエツチング処理により照射を受けなかった堆積層部分
１６は完全に除去され、他方照射を受けた堆積層部分１
４は厚さの一部分にわたりエツチングされてダート電極
と々る部分１７が残される。Figure 2C uses this difference in etching speed to
3 is a diagram showing a state obtained by etching the deposited layer 3 shown in FIG. 2B after irradiation by a wet or dry etching method. FIG. As is clear from this figure, the deposited layer portion 16 that was not irradiated was completely removed by this etching process, while the deposited layer portion 16 that was irradiated was completely removed.
4 is etched over a portion of its thickness, leaving a portion 17 where the dart electrode extends.
このように、本発明の方法によれば、堆積層に対し選択
的に放射の照射を行って堆積層の結晶性に変化をもたら
し、然る後エツチングを行って所望の・ぐターニングを
得る。この場合放射としてレーザ光又は電子線を使用す
るのが好適である。レーザ光を使用する場合にはその照
射密度を約０．５〜ｌ０ＪＡＹｎ 程度とする。これ
を多結晶シリコン層である堆積層に照射すると、堆積直
後の多結晶シリコンの粒子の大きさが数十〜数百Ｘであ
ったものがレーザ光照射後には数μｍ〜数十μｍまで増
大（６）
する。その結果、次のエツチング工程に際し、例えばＣ
Ｆ４＋５係０２のドライエツチングを行うと、照射を受
けた多結晶シリコン部分のエツチングレイトは照射を受
けなかった多結晶シリコン部分に対し１０分の１〜１０
０分の工程度にまで減少する。従って、基層上に堆積さ
せる多結晶シリコン層の厚さを、最終的（Ｃ電極と々る
部分の厚さ及びエツチングに際する厚み減少分を考慮に
入れて、予め正確に設定しておけば、パターニングを正
確に制御することが出来る。放射として電子線を使用す
る場合でも、レーザ光と同程度のエネルギーの電子線を
堆積層に照射するととによシ、上述したと同等の結果を
得ることが出来る。Thus, according to the method of the present invention, the deposited layer is selectively irradiated with radiation to effect a change in the crystallinity of the deposited layer, and then etched to obtain the desired turning. In this case, it is preferred to use laser light or electron beams as radiation. When using laser light, the irradiation density is about 0.5 to 10 JAYn. When this is irradiated onto a deposited layer, which is a polycrystalline silicon layer, the size of the polycrystalline silicon particles immediately after deposition was several tens to hundreds of times larger, but after laser light irradiation, the size of the polycrystalline silicon particles increased to several micrometers to several tens of micrometers. (6) Do. As a result, during the next etching process, for example, C
When dry etching of F4+5 ratio 02 is performed, the etching rate of the irradiated polycrystalline silicon part is 1-10 times lower than that of the non-irradiated polycrystalline silicon part.
The process rate is reduced to 0 minutes. Therefore, if the thickness of the polycrystalline silicon layer to be deposited on the base layer is accurately set in advance, taking into account the final thickness of the part where the C electrode will reach and the thickness reduction during etching. , patterning can be precisely controlled. Even when using an electron beam as radiation, it is best to irradiate the deposited layer with an electron beam with an energy comparable to that of a laser beam, and the same results as described above can be obtained. I can do it.
上述した実施例では堆積層１３を多結晶シリコン層とし
たがこの層を非晶質シリコン層或いは金属薄膜とするこ
とも出来る。In the embodiments described above, the deposited layer 13 is a polycrystalline silicon layer, but this layer can also be an amorphous silicon layer or a metal thin film.
堆積層を非晶質シリコン層とし、放射として照射密度約
０．５〜１．０ Ｊ／ａｎ ２のレーザ光又はとのレー
ザ光と同程度のエネルギーの電子線を用いることによシ
、放射の照射を受けた非晶質シリコン層の粒子の大きさ
は前述と同様数μｍ〜数十μｍと疫る従ってこの場合に
も放射の照射を受けた部分のエツチング速度は放射の照
射を受けなかった部分のエツチング速度よりも遥かに遅
く々す、このエツチング速度の低減の割合は多結晶シリ
コン層の場合よシも犬と１蝋よってこのエツチング速度
の差を有効に利用してパターニングを行うことが出来る
。The deposited layer is an amorphous silicon layer, and the radiation is a laser beam with an irradiation density of about 0.5 to 1.0 J/an2 or an electron beam with energy comparable to that of the laser beam. The size of the particles in the amorphous silicon layer irradiated by the radiation ranges from several μm to several tens of μm, as described above.Therefore, in this case as well, the etching rate of the portion irradiated with the radiation is the same as that of the non-irradiated portion. The rate of reduction in etching speed is much slower than the etching speed of the etched parts, and the rate of reduction in etching speed is much lower than in the case of polycrystalline silicon layers. I can do it.
又、金属薄膜例えばアルミニウム薄膜を堆積層とする場
合には、アルミニウムの堆積直後の粒子の大きさは数千
Ｘ程度であったものが前述と同様なエネルギーのレーザ
光又は電子線の照射後には粒子の大きさは数十μｍに増
大し、従ってこの場合にも照射後のエツチング速度は照
射前のエツチング速度の数分の１〜数１０分の工程度に
減少し、・やターニングが容易となる。In addition, when a metal thin film such as an aluminum thin film is used as a deposited layer, the size of the particles immediately after aluminum deposition is approximately several thousand X, but after irradiation with a laser beam or electron beam of the same energy as described above, the particle size becomes smaller. The particle size increases to several tens of micrometers, and therefore, in this case as well, the etching speed after irradiation is reduced to a process time of a few to several tens of minutes of the etching speed before irradiation, and turning becomes easier. Become.
上述した実施例においてはダート酸化膜を基層として説
明したが、これに限定されるものでは彦く半導体装置の
製造に用いられるいわゆる絶縁層又は絶縁膜を基層とし
得ることはもとより、半導体基板等の半導体層にパター
ニング成形されるべき堆積層を設けた場合に（ｄこの半
導体層自体を基層とし得る。In the above-mentioned embodiments, the dirt oxide film was used as the base layer, but the base layer is not limited to this.In addition, the base layer can be a so-called insulating layer or insulating film used in the manufacture of semiconductor devices, and it can also be used as a base layer. When a semiconductor layer is provided with a deposited layer to be patterned (d), this semiconductor layer itself can be used as a base layer.
又、上述した実施例においては堆積層として多結晶シリ
コン層、非晶質シリコン層を用いたが、これに限定され
るものではなく、他の多結晶、非晶質半導体薄膜を用い
ることが出来ることは勿論である。又堆積層としての金
属薄膜は上述したアルミニウム以外の他の金属とし得る
こと明らかである。Furthermore, in the above embodiments, a polycrystalline silicon layer and an amorphous silicon layer were used as the deposited layer, but the present invention is not limited to this, and other polycrystalline or amorphous semiconductor thin films can be used. Of course. It is also clear that the metal thin film as deposited layer can be other metals than the aluminum mentioned above.
（発明の効果）
本発明によれば、多結晶又は非晶質の半導体薄膜或いは
金属薄膜等の堆積層にレーザ光又は電子線の放射を選択
的に照射し、この放射照射を受けた堆積層部分と受けな
かった堆積層部分とのエツチング速度の差を利用してパ
ターニングする方法であって、何らレジスト層を使用し
ないので、レジスト層の除去や洗浄等の工程が不必要と
なシ従って工程が簡略化し製造コストが低下するという
利点がある。(Effects of the Invention) According to the present invention, a deposited layer such as a polycrystalline or amorphous semiconductor thin film or a metal thin film is selectively irradiated with laser light or electron beam radiation, and the deposited layer irradiated with this radiation is This is a patterning method that utilizes the difference in etching speed between the etching layer and the unreceived deposited layer portion, and since no resist layer is used, processes such as removing and cleaning the resist layer are unnecessary. This has the advantage of simplifying the process and reducing manufacturing costs.
（９）
又、レジスト層を使用し々いため、マスク変換差が々く
なるか又はその予想も可能であり、サイドエツチング量
も正確に予測することが可能となり、その後の自己整合
技術によるソース−ドレインの従ってダート長を正確に
形成することが可能と々るという利点がある。(9) In addition, since the resist layer is used frequently, it is possible to predict whether or not the mask conversion difference will be large, and it is also possible to accurately predict the amount of side etching. There is an advantage that it is possible to accurately form the dart length of the drain.
尚、上述した実施例はシリコングー）ＭＯ８半導体装置
のケゝ−ト多結晶シリコンの・ぐターニング工程につき
本発明を説明したが、本発明はこの実施例にのみ限定さ
れるものではなく、他の種々の半導体装置の製造にも適
用出来ること明らかである。Although the above-mentioned embodiment describes the present invention with respect to the turning process of silicone polycrystalline silicon of an MO8 semiconductor device, the present invention is not limited only to this embodiment, and may be applied to other methods. It is clear that the present invention can also be applied to the manufacture of various semiconductor devices.
第１図は従来のシリコングー）ＭＯ８半導体装置のゲー
トの・母ターン形成方法を説明するだめの工程図、
第２図は本発明の半導体装置のパターン形成方法の一実
施例を説明するだめの工程図である。
１１・・・半導体層（又は半導体薄膜）、１２・・・ダ
ート酸化膜（又は基層）、１３・・・堆積層としての多
結晶シリコン層、１４・・・放射の照射を受けた部（１
０）
分、１５・・・放射（又はレーザビーム又は電子線）、
１６・・・放射の照射を受けんかった部分、１７・・・
ダート電極となる部分。
特許出願人 沖電気工業株式会社
（１１）
第２図
手続補正書（峠）
１ 事件の表示
昭和５８年 特 許 願第０５１５１６号２ 発明の名
称
半導体装置のパターン形成方法
３、補正をする者
事件との関係 特 許 出 願 人住 所（
〒１０５） 東京都港区虎ノ門１丁目７番１２号名称
（０２９） ５中電気工業株式会社代表者
取締役社長橋本南海男−１代理人
住 所（〒１０５） 東京都港区虎ノ門１丁目７香１
２号補正の内容 別紙のとおシ
６、補正の内容
（１）明細書第３頁第４行目と第１１行目に「レノスタ
」とあるのを「レジスト」と補正する。
「粒径」と補正する。
（３）同書第６頁第３行目に「堆積層３」とあるのを「
堆積層１３」と補正する。
（２）
１８３−Fig. 1 is a process diagram illustrating a method for forming a gate/main turn of a conventional silicon MO8 semiconductor device, and Fig. 2 is a process diagram illustrating an embodiment of a pattern forming method for a semiconductor device according to the present invention. It is a process diagram. 11... Semiconductor layer (or semiconductor thin film), 12... Dirt oxide film (or base layer), 13... Polycrystalline silicon layer as a deposited layer, 14... Portion irradiated with radiation (1
0) minutes, 15...Radiation (or laser beam or electron beam),
16... Part that was not irradiated with radiation, 17...
The part that becomes the dirt electrode. Patent Applicant Oki Electric Industry Co., Ltd. (11) Figure 2 Procedural Amendment (Toge) 1 Indication of the Case 1982 Patent Application No. 051516 2 Name of the Invention Method for Forming Patterns of Semiconductor Devices 3, Person Who Makes Amendment Case Relationship with Patent Application Person Address (
Address: 105) 1-7-12 Toranomon, Minato-ku, Tokyo Name (029) 5 Chuo Electric Industry Co., Ltd. Representative
Director and President Nankai Hashimoto-1 Agent address (105) 1-7 Ko, Toranomon, Minato-ku, Tokyo
Contents of Amendment No. 2 Attachment 6, Contents of Amendment (1) The word "Renostar" in lines 4 and 11 of page 3 of the specification is amended to read "Resist." Correct as “particle size”. (3) In the third line of page 6 of the same book, the phrase “deposited layer 3” was replaced with “
Deposited layer 13". (2) 183-
Claims (1)
、該堆積層に対し放射を選択的に照射し、。 該放射の照射を受けた堆積層部分と照射を受け々かった
堆積層部分とのエツチング速度の相違を利用して前記堆
積層をエツチングして・ぐターン成形することを特徴と
する半導体装置の・ぐターン形成方法。[Claims] A deposited layer to be formed into a base turn is formed on the surface of the base layer, and the deposited layer is selectively irradiated with radiation. A semiconductor device characterized in that the deposited layer is etched to form a pattern by utilizing a difference in etching rate between a deposited layer portion that has been irradiated with the radiation and a deposited layer portion that has not been irradiated.・Gutan formation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5151683A JPS59177930A (en) | 1983-03-29 | 1983-03-29 | Pattern formation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5151683A JPS59177930A (en) | 1983-03-29 | 1983-03-29 | Pattern formation of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59177930A true JPS59177930A (en) | 1984-10-08 |
Family
ID=12889167
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5151683A Pending JPS59177930A (en) | 1983-03-29 | 1983-03-29 | Pattern formation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59177930A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60109074A (en) * | 1983-11-18 | 1985-06-14 | Nec Corp | Magnetic head slider and its manufacture |
| WO2000065642A1 (en) * | 1999-04-26 | 2000-11-02 | Shin-Etsu Handotai Co., Ltd. | Production methods of compound semiconductor single crystal and compound semiconductor element |
-
1983
- 1983-03-29 JP JP5151683A patent/JPS59177930A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60109074A (en) * | 1983-11-18 | 1985-06-14 | Nec Corp | Magnetic head slider and its manufacture |
| WO2000065642A1 (en) * | 1999-04-26 | 2000-11-02 | Shin-Etsu Handotai Co., Ltd. | Production methods of compound semiconductor single crystal and compound semiconductor element |
| US6589447B1 (en) * | 1999-04-26 | 2003-07-08 | Shin-Etsu Handotai Co., Ltd. | Compound semiconductor single crystal and fabrication process for compound semiconductor device |
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