JP2723260B2 - Fine pattern forming method - Google Patents

Fine pattern forming method

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Publication number
JP2723260B2
JP2723260B2 JP21573988A JP21573988A JP2723260B2 JP 2723260 B2 JP2723260 B2 JP 2723260B2 JP 21573988 A JP21573988 A JP 21573988A JP 21573988 A JP21573988 A JP 21573988A JP 2723260 B2 JP2723260 B2 JP 2723260B2
Authority
JP
Japan
Prior art keywords
resist film
resist
opening
electron beam
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP21573988A
Other languages
Japanese (ja)
Other versions
JPH0263059A (en
Inventor
久夫 川崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP21573988A priority Critical patent/JP2723260B2/en
Publication of JPH0263059A publication Critical patent/JPH0263059A/en
Application granted granted Critical
Publication of JP2723260B2 publication Critical patent/JP2723260B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Electron Beam Exposure (AREA)

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は微細パターン形成方法に係り、特に集積回
路、GaAsを素材とするマイクロ波半導体素子の製造にお
ける微細パターンの形成方法に関する。
The present invention relates to a method of forming a fine pattern, and more particularly to a method of forming a fine pattern in the manufacture of an integrated circuit or a microwave semiconductor device using GaAs as a material. About.

(従来の技術) 近年、高速のスタティックRAMや乗算器等の集積回
路、あるいはGaAsを素材とするマイクロ波半導体素子の
特性は、微細加工技術の進歩を背景とし飛躍的に向上し
た。特に、高電子移動度トランジスタで代表される低雑
音マイクロ波半導体素子で、実用化されているゲート長
は0.3μm以下に達している。この様な微細パターンを
形成する方法として、電子ビーム露光法が広く採用され
ている。第2図(a)〜(c)は電子ビーム露光法を用
いて半導体基板上にレジストパターンを形成する方法を
具体的に示す図である。先ず、第2図(a)に示すよう
に半導体基板101上に電子線レジスト膜102を形成する。
次に第2図(b)に示すように、電子線レジスト膜102
に矢印で示す方向から電子ビーム103を照射する。この
電子線レジスト膜102としてポジ形のレジスト膜を用い
ると、第2図(c)に示すように、電子ビームに照射さ
れた部分が現像により除去され、半導体基板101上にレ
ジストパターン112が形成される。ところで、電子ビー
ム露光法を用いてレジストパターンを再現性良く安定に
形成するためには、露光条件及びレジスト膜の現像条件
を精密に制御するとともに、レジスト膜102に入射する
電子ビーム径を要求されたパターン寸法以下に絞る必要
がある。特に、0.3μm程度のレジストパターンを形成
する場合には、レジスト内あるいは半導体基板からの電
子散乱が無視出来なくなるため、レジスト膜に入射する
電子ビーム径を0.1μm以下に絞りこむことが望まし
い。一般に、レジスト膜に入射する電子ビーム径と電子
ビーム電流は比例関係にあり、電子ビーム電流と露光に
要する時間は同一感度のレジスト膜を用いた場合、逆比
例関係にある。従って電子ビーム径を絞りこむことは、
露光に要する時間が増大し、時間内の処理数の低下を招
く。
(Prior Art) In recent years, the characteristics of integrated circuits such as high-speed static RAMs and multipliers, and microwave semiconductor devices made of GaAs have been dramatically improved with the progress of fine processing technology. Particularly, in a low-noise microwave semiconductor device represented by a high electron mobility transistor, a gate length practically used has reached 0.3 μm or less. As a method for forming such a fine pattern, an electron beam exposure method is widely used. 2 (a) to 2 (c) are diagrams specifically showing a method of forming a resist pattern on a semiconductor substrate using an electron beam exposure method. First, an electron beam resist film 102 is formed on a semiconductor substrate 101 as shown in FIG.
Next, as shown in FIG. 2 (b), the electron beam resist film 102
Is irradiated with the electron beam 103 from the direction indicated by the arrow. When a positive resist film is used as the electron beam resist film 102, a portion irradiated with the electron beam is removed by development as shown in FIG. 2C, and a resist pattern 112 is formed on the semiconductor substrate 101. Is done. By the way, in order to form a resist pattern stably with good reproducibility using the electron beam exposure method, it is necessary to precisely control the exposure conditions and the development conditions of the resist film and to make the diameter of the electron beam incident on the resist film 102 necessary. It is necessary to narrow down to less than the pattern size. In particular, when a resist pattern of about 0.3 μm is formed, electron scattering from the resist or from the semiconductor substrate cannot be neglected. Therefore, it is desirable to narrow the diameter of the electron beam incident on the resist film to 0.1 μm or less. Generally, the diameter of an electron beam incident on a resist film and the electron beam current have a proportional relationship, and the electron beam current and the time required for exposure have an inverse proportional relationship when a resist film having the same sensitivity is used. Therefore, narrowing the electron beam diameter is
The time required for exposure increases, and the number of processes within the time decreases.

(発明が解決しようとする課題) 叙上の如く、従来の技術によると、露光時間が増大
し、時間当り処理数が低減するとともに、電子ビーム径
を0.1μm以下に設定するためには電子ビーム露光装置
の電子光学系の入念な整備と調整が必要なため、電子ビ
ーム露光装置の稼働率が大幅に低下する問題点もある。
(Problems to be Solved by the Invention) As described above, according to the conventional technology, the exposure time is increased, the number of processes per time is reduced, and the electron beam diameter is set to 0.1 μm or less. Since careful maintenance and adjustment of the electron optical system of the exposure apparatus is required, there is also a problem that the operation rate of the electron beam exposure apparatus is greatly reduced.

この発明は上記従来の問題点に鑑み、微細なレジスト
パターンを能率良く形成するレジストパターン形成方法
を提供することを目的とするものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a resist pattern forming method for efficiently forming a fine resist pattern in view of the above-mentioned conventional problems.

〔発明の構成〕[Configuration of the invention]

(課題を解決するための手段) 本発明にかかる微細パターン形成方法は、半導体基板
上に第1のレジスト膜を設けこれに露光処理および現像
処理を施して所定の開孔を有するパターンに形成する工
程と、前記第1のレジスト膜とその開孔の側面にこの第
1のレジスト膜と組成が異なりかつ第1のレジスト膜と
反応層を形成する第2のレジスト膜を積層して被着し両
レジスト膜の反応層を形成する工程と、前記第2のレジ
スト膜の未反応層を除去する工程とを具備し、前記第1
のレジスト膜の開孔よりも小さな開孔を形成するもので
ある。
(Means for Solving the Problems) According to the method for forming a fine pattern according to the present invention, a first resist film is provided on a semiconductor substrate and subjected to an exposure process and a development process to form a pattern having predetermined openings. Forming a second resist film having a composition different from that of the first resist film and forming a reaction layer with the first resist film on the side surface of the first resist film and the opening thereof; Forming a reaction layer of both resist films, and removing an unreacted layer of the second resist film;
An opening smaller than the opening of the resist film is formed.

(作 用) この発明は第1のレジスト膜の開孔よりも小さい開孔
が最終的に得られるので、第1のレジスト膜に設ける開
孔を所定の開孔寸法よりも広く設定できる。このため、
照射する電子ビーム径に対して十分な余裕度をもって形
成でき、しかも、第2のレジスト膜に対しては開孔を施
すことなく微細パターンが容易に、かつ再現性良く達成
できる。
(Operation) In the present invention, an opening smaller than the opening of the first resist film is finally obtained, so that the opening provided in the first resist film can be set wider than a predetermined opening size. For this reason,
The second resist film can be formed with sufficient margin with respect to the diameter of the electron beam to be irradiated, and a fine pattern can be easily achieved with good reproducibility without making a hole in the second resist film.

(実施例) 以下、本発明の一実施例を図面を参照して説明する。Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

まず第1図(a)に示すように、半導体基板101上に
第1のレジスト膜11として、例えばポジタイプの電子線
レジストPMMA(ポリメチルメタアクリレート)を1μm
厚に形成し、ついで前記第1のレジスト膜11に矢印で示
す方向から所定のパターンに従って電子ビーム13を照射
する。次に第1図(b)に示すように、第1のレジスト
膜11を例えばMIBK(メチルイソブチルケトン)とIPA
(イソプロピルアルコール)を容積比1:2に混合してな
る現像液を用いて現像し、例えば0.5μmの開孔11aを形
成する。電子ビーム露光法を用いた場合、開孔寸法0.5
μm程度のパターンは比較的大ビーム電流で形成できる
ため、描画に要する時間は短時間で済む。
First, as shown in FIG. 1A, as a first resist film 11 on a semiconductor substrate 101, for example, a positive type electron beam resist PMMA (polymethyl methacrylate) is 1 μm thick.
Then, the first resist film 11 is irradiated with an electron beam 13 according to a predetermined pattern from a direction indicated by an arrow. Next, as shown in FIG. 1B, the first resist film 11 is made of, for example, MIBK (methyl isobutyl ketone) and IPA.
(Ipsopropyl alcohol) is developed using a developing solution obtained by mixing the mixture in a volume ratio of 1: 2, and an opening 11a of, for example, 0.5 μm is formed. When the electron beam exposure method is used, the aperture size is 0.5
Since a pattern of about μm can be formed with a relatively large beam current, the time required for drawing is short.

レジスト膜12として例えばポジタイプのフォトレジス
トAZ1350(商品名、シプレイ社製)を0.5μm厚に塗布
し、例えば90℃10分間の熱処理を加え第1のレジスト膜
11と第2のレジスト膜12との境界に第1図(c)に示す
ような第2のレジスト膜12の剥離処理で剥離されない両
レジスト膜の反応層14を形成する。ここで第2のレジス
ト膜12を塗布した後の熱処理は、両レジスト膜の反応層
14を安定に形成することを目的として行なっているが、
第2のレジスト膜12を塗布しただけでも両レジスト膜の
反応層14を形成することが可能であるため、必ずしも必
要ではない。次に未反応の第2のレジスト膜12を剥離す
るために、例えば半導体基板上に紫外線を照射した後、
AZ現像液に浸漬し、第1図(d)に示すレジストパター
ン15を形成する。
As the resist film 12, for example, a positive type photoresist AZ1350 (trade name, manufactured by Shipley Co., Ltd.) is applied to a thickness of 0.5 μm, and heat-treated at, for example, 90 ° C. for 10 minutes to form a first resist film.
At the boundary between the second resist film 11 and the second resist film 12, a reaction layer 14 of the two resist films which is not stripped by the stripping process of the second resist film 12 as shown in FIG. 1C is formed. Here, the heat treatment after the application of the second resist film 12 is performed by a reaction layer of both resist films.
Although the aim is to form 14 stably,
It is not always necessary because the reaction layers 14 of both resist films can be formed only by applying the second resist film 12. Next, in order to remove the unreacted second resist film 12, for example, after irradiating an ultraviolet ray on the semiconductor substrate,
Immersion in an AZ developer forms a resist pattern 15 shown in FIG. 1 (d).

未反応の第2のレジスト膜12を剥離した後の半導体基
板(1)上のレジスト膜の厚さは、剥離されない反応層
14の存在により当初の第1のレジスト膜12の厚さよりも
0.1μm厚くなり、同時に開口部の周辺が0.1μmずつ狭
くなることが判っている。従って第1のレジスト膜の開
孔11aの寸法を上記実施例のように0.5μmと設定した場
合、第2のレジスト膜12を剥離した後の開孔23の寸法は
0.3μmとなる。
The thickness of the resist film on the semiconductor substrate (1) after the unreacted second resist film 12 is stripped is determined by the unreacted reaction layer
Due to the presence of 14, the thickness of the first resist film 12
It has been found that the thickness of the opening becomes smaller by 0.1 μm at the same time. Therefore, when the size of the opening 11a of the first resist film is set to 0.5 μm as in the above embodiment, the size of the opening 23 after the second resist film 12 is removed is
0.3 μm.

なお、上記実施例ではPMMAにAZ1350を用いた例につい
て説明したが、第2のレジスト膜を剥離した後の開孔の
寸法が若干異なるもののPMIPKにAZ1350を、また、PMMA
にHPR−1182(商品名、GAF社製)等のレジストの組合せ
であってもよい。また、第1および第2のレジスト膜1
1,12のパターン形成に用いる露光手段は、電子ビーム露
光に限らず、X線露光、あるいはこれらの組合せであっ
てもよい。さらに、半導体基板101上にSiO2、あるいはA
lの膜が形成されている場合にも適用可能である。
In the above embodiment, an example in which AZ1350 is used for PMMA has been described. However, although the dimensions of the openings after the second resist film is peeled off are slightly different, AZ1350 is used for PMIPK, and PMMA is also used for PMIPK.
Alternatively, a combination of resists such as HPR-1182 (trade name, manufactured by GAF) may be used. In addition, the first and second resist films 1
The exposure means used for forming the patterns 1 and 12 is not limited to electron beam exposure, but may be X-ray exposure or a combination thereof. Furthermore, SiO 2 or A
The present invention is also applicable to the case where the film l is formed.

〔発明の効果〕〔The invention's effect〕

以上述べたように本発明によれば、半導体基板上に第
1のレジスト膜を設けて所定の開孔を有するパターンに
形成したのち、前記第1のレジスト膜とその開孔の側面
にこの第1のレジスト膜と組成が異なりかつ第1のレジ
スト膜と反応層を形成する第2のレジスト膜を積層被着
し両レジスト膜の反応層を形成することにより、前記第
1のレジスト膜の開孔よりも小さな開孔を形成すること
ができる。
As described above, according to the present invention, after a first resist film is provided on a semiconductor substrate to form a pattern having a predetermined opening, the first resist film and the side surface of the opening are provided with the first resist film. A second resist film having a different composition from that of the first resist film and forming a reaction layer with the first resist film is laminated and formed to form a reaction layer between the two resist films, thereby opening the first resist film. An opening smaller than the hole can be formed.

したがって第1のレジスト膜の開孔を最終的に必要な
開孔寸法よりも広く設定することが可能となるため、照
射する電子ビーム径に対して十分な余裕度をもって形成
出来、しかも第2のレジスト膜を塗布した後剥離するだ
けで必要とする開孔が形成できるために、0.3μm程度
あるいはそれ以下の開孔寸法を有する微細パターンの形
成が容易に、しかも再現性良く達成できる顕著な効果が
ある。
Therefore, the opening of the first resist film can be set wider than the finally required opening size, so that the first resist film can be formed with a sufficient margin for the diameter of the electron beam to be irradiated, and the second resist film can be formed with a sufficient margin. Since the required holes can be formed simply by peeling after applying the resist film, a remarkable effect that a fine pattern having a hole size of about 0.3 μm or less can be easily achieved with good reproducibility. There is.

【図面の簡単な説明】 第1図(a)〜(d)は本発明にかかる一実施例の微細
パターン形成方法を工程順に示すいずれも断面図、第2
図(a)〜(c)は従来例の微細パターン形成方法を工
程順に示すいずれも断面図である。 11……第1のレジスト膜 12……第2のレジスト膜 13……電子ビーム 14……反応層 15……レジストパターン 101……半導体基板
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to 1 (d) are sectional views showing a method of forming a fine pattern according to one embodiment of the present invention in the order of steps, and FIGS.
1A to 1C are cross-sectional views showing a conventional fine pattern forming method in the order of steps. 11 First resist film 12 Second resist film 13 Electron beam 14 Reaction layer 15 Resist pattern 101 Semiconductor substrate

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板上に第1のレジスト膜を設けこ
れに露光処理および現像処理を施して所定の開孔を有す
るパターンに形成する工程と、前記第1のレジスト膜と
その開孔の側面にこの第1のレジスト膜と組成が異なり
かつ第1のレジスト膜と反応層を形成する第2のレジス
ト膜を積層して被着し両レジスト膜の反応層を形成する
工程と、前記第2のレジスト膜の未反応層を除去する工
程とを具備し、前記第1のレジスト膜の開孔よりも小さ
な開孔を形成する微細パターン形成方法。
A step of providing a first resist film on a semiconductor substrate, performing an exposure process and a development process on the first resist film to form a pattern having a predetermined opening, and forming the first resist film and the opening of the opening. Laminating and applying a second resist film having a composition different from that of the first resist film and forming a reaction layer with the first resist film on a side surface to form a reaction layer of both resist films; Removing the unreacted layer of the second resist film, and forming an opening smaller than the opening of the first resist film.
JP21573988A 1988-08-30 1988-08-30 Fine pattern forming method Expired - Fee Related JP2723260B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21573988A JP2723260B2 (en) 1988-08-30 1988-08-30 Fine pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21573988A JP2723260B2 (en) 1988-08-30 1988-08-30 Fine pattern forming method

Publications (2)

Publication Number Publication Date
JPH0263059A JPH0263059A (en) 1990-03-02
JP2723260B2 true JP2723260B2 (en) 1998-03-09

Family

ID=16677397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21573988A Expired - Fee Related JP2723260B2 (en) 1988-08-30 1988-08-30 Fine pattern forming method

Country Status (1)

Country Link
JP (1) JP2723260B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005116776A1 (en) 2004-05-26 2005-12-08 Jsr Corporation Resin composition for forming fine pattern and method for forming fine pattern
EP1942376A2 (en) 2001-07-05 2008-07-09 Tokyo Ohka Kogyo Co., Ltd. Method for reducing pattern dimension in a photoresist layer
WO2008105293A1 (en) 2007-02-26 2008-09-04 Jsr Corporation Resin composition for micropattern formation and method of micropattern formation

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2716547A1 (en) * 1994-02-24 1995-08-25 Fujitsu Ltd Method for forming a resist pattern and for manufacturing a semiconductor device.
JP6888493B2 (en) 2017-09-14 2021-06-16 三菱電機株式会社 Manufacturing method of semiconductor devices

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1942376A2 (en) 2001-07-05 2008-07-09 Tokyo Ohka Kogyo Co., Ltd. Method for reducing pattern dimension in a photoresist layer
WO2005116776A1 (en) 2004-05-26 2005-12-08 Jsr Corporation Resin composition for forming fine pattern and method for forming fine pattern
US8715901B2 (en) 2004-05-26 2014-05-06 Jsr Corporation Resin composition for forming fine pattern and method for forming fine pattern
WO2008105293A1 (en) 2007-02-26 2008-09-04 Jsr Corporation Resin composition for micropattern formation and method of micropattern formation

Also Published As

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JPH0263059A (en) 1990-03-02

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