JPS6137774B2 - - Google Patents

Info

Publication number
JPS6137774B2
JPS6137774B2 JP55101252A JP10125280A JPS6137774B2 JP S6137774 B2 JPS6137774 B2 JP S6137774B2 JP 55101252 A JP55101252 A JP 55101252A JP 10125280 A JP10125280 A JP 10125280A JP S6137774 B2 JPS6137774 B2 JP S6137774B2
Authority
JP
Japan
Prior art keywords
pattern
etching
cms
substrate
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55101252A
Other languages
Japanese (ja)
Other versions
JPS5727029A (en
Inventor
Tadamasa Ogawa
Minoru Kobayashi
Masatoshi Oda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10125280A priority Critical patent/JPS5727029A/en
Publication of JPS5727029A publication Critical patent/JPS5727029A/en
Publication of JPS6137774B2 publication Critical patent/JPS6137774B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Description

【発明の詳細な説明】 本発明は不均質なエツチング及びエツチング速
度の低下を防止し高品質のMoパターンを容易に
形成しうるMoパターンの形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a Mo pattern, which prevents non-uniform etching and a decrease in etching rate and easily forms a high quality Mo pattern.

紫外線、粒子線又はX線用レジストの1種であ
るクロルメチル化ポリスチレン(以下CMSと略
称する)を用いて形成したMoパターンは、半導
体集積回路等の製作におけるトランジスタの配線
あるいはトランジスタのゲート回路等に使用され
ている。しかし、その形成過程において、CMS
がMoと化学反応を起してMo基体上に変質層を形
成し、この層がエツチングのマスクとして作用
し、不均質なエツチング及びエツチング速度の低
下を生じるという問題がある。すなわち、Moは
それと接したCMSを変質させる作用を有する。
Moパターンの形成に当つては、CMS塗布後、レ
ジスト溶媒を蒸発させると共に、Moとの接着力
を強固にするため、プリベークと呼ばれる約100
℃の温度の熱処理が施されるが、この熱処理によ
りMoとCMSが反応してその境界に変質層が形成
され、この変質層のエツチング速度がMoのエツ
チング速度に比して著しく小さいため、変質層に
覆われた部分と覆われない部分のエツチングの深
さが異なり、不均一なエツチングが行なわれて良
好なMoパターンを形成することができなくな
る。
Mo patterns formed using chloromethylated polystyrene (hereinafter referred to as CMS), which is a type of resist for ultraviolet rays, particle beams, or X-rays, are used for transistor wiring or transistor gate circuits in the production of semiconductor integrated circuits, etc. It is used. However, in its formation process, CMS
There is a problem in that a chemical reaction occurs with Mo to form a degraded layer on the Mo substrate, and this layer acts as an etching mask, resulting in non-uniform etching and a reduction in the etching rate. That is, Mo has the effect of altering the CMS that comes into contact with it.
When forming a Mo pattern, after applying CMS, a pre-bake process of about 100% is required to evaporate the resist solvent and strengthen the adhesive force with Mo.
Heat treatment is performed at a temperature of °C, but as a result of this heat treatment, Mo and CMS react and an altered layer is formed at the boundary.The etching rate of this altered layer is significantly lower than that of Mo, so the alteration The etching depths of the covered and uncovered parts of the layer are different, resulting in non-uniform etching and making it impossible to form a good Mo pattern.

本発明は上記の観点に立つてなされたものであ
り、その目的は、不均質なエツチング及びエツチ
ング速度の低下を防止し高品質のMoパターンを
形成しうる方法を提供することである。
The present invention has been made based on the above-mentioned viewpoint, and its object is to provide a method capable of forming a high-quality Mo pattern while preventing non-uniform etching and reduction in etching speed.

本発明は上記の目的を達成するため、次の構成
をとるものである。すなわち、本発明のMoパタ
ーンの形成方法は、Mo基体上にクロルメチル化
ポリスチレンを塗布してレジスト膜を形成し、該
レジスト膜に遠紫外線、粒子線又はX線を照射し
て所定のパターンを描画し、現像処理を施して
Mo基体上に該レジスト膜のパターンを形成し、
次いで該パターンをマスクとしてMo基体をエツ
チングするMoパターンの形成方法において、ク
ロルメチル化ポリスチレンを塗布する前に予め
Mo基体の表面をMo酸化物で被覆することを特徴
とするものである。
In order to achieve the above object, the present invention has the following configuration. That is, the method for forming a Mo pattern of the present invention involves coating a Mo substrate with chloromethylated polystyrene to form a resist film, and irradiating the resist film with deep ultraviolet rays, particle beams, or X-rays to draw a predetermined pattern. and then undergo development processing.
forming a pattern of the resist film on the Mo substrate;
In the method for forming a Mo pattern in which the Mo substrate is then etched using the pattern as a mask, the
It is characterized in that the surface of the Mo substrate is coated with Mo oxide.

本発明においては、Siウエハ上に電子ビーム等
によりMoを付着して得たMo基体上に、CMSを塗
布する前に、熱処理等の適当な手段により、Mo
酸化物を形成し、その上にCMSを塗布する。こ
のようにして、MoとCMSの間にMo酸化物を介在
させることにより、MoとCMSの直接の接触を避
けることができる。Mo酸化物はCMSとの間に有
害な反応を起さず、又、極めて薄い膜を容易に形
成することができてエツチングの害にならないの
で、均質かつ迅速なエツチングを行ない高品質の
Moパターンを容易に形成することができる。
In the present invention, before coating CMS on a Mo substrate obtained by depositing Mo on a Si wafer using an electron beam or the like, Mo is applied by appropriate means such as heat treatment.
Form the oxide and apply CMS on top of it. In this way, direct contact between Mo and CMS can be avoided by interposing the Mo oxide between Mo and CMS. Mo oxide does not cause any harmful reaction with CMS, and it can easily form an extremely thin film that does not harm etching, allowing for uniform and rapid etching and high quality.
A Mo pattern can be easily formed.

本発明において、Mo酸化物の形成方法は特に
限定されず、熱処理による手段、高湿大気中に放
置する手段、硫酸等の薬品で処理する手段及び酸
素プラズマにさらす手段等を適宜適用することが
できる。この中でも熱処理による方法が簡便であ
り、その温度は150〜250℃とすることが適当であ
る。この温度範囲より低温では、Mo酸化物の膜
の形成が不十分なため本発明の効果を十分発揮す
ることができず、又、この温度範囲より高温で
は、Mo酸化物の膜が厚くなり過ぎて、Moの表面
が変色し、又、Moの実効厚さが減少し、更には
電気抵抗が増大して所定の特性の電気回路が形成
できなくなる。
In the present invention, the method for forming Mo oxide is not particularly limited, and methods such as heat treatment, leaving it in a high humidity atmosphere, treatment with chemicals such as sulfuric acid, exposure to oxygen plasma, etc. can be applied as appropriate. can. Among these methods, heat treatment is the simplest method, and the temperature is suitably 150 to 250°C. At temperatures lower than this temperature range, the effect of the present invention cannot be fully exhibited because the Mo oxide film is insufficiently formed, and at temperatures higher than this temperature range, the Mo oxide film becomes too thick. As a result, the surface of Mo becomes discolored, the effective thickness of Mo decreases, and electrical resistance increases, making it impossible to form an electrical circuit with predetermined characteristics.

本発明のMoパターンの形成方法は、上記のMo
酸化物形成工程を介入させる以外は、通常行なわ
れている方法にしたがつて容易に実施することが
できる。
The method for forming a Mo pattern of the present invention is based on the above-mentioned Mo pattern.
The process can be easily carried out according to commonly used methods, except for the intervention of the oxide forming step.

次に、本発明を実施例及び比較例により説明す
るが、本発明はこれらによりなんら限定されるも
のではない。
Next, the present invention will be explained with reference to Examples and Comparative Examples, but the present invention is not limited by these in any way.

実施例 Siウエハ上に、真空中、電子ビーム蒸着により
厚さ0.3μmにMoを付着させた後、これを大気中
に取出し、180℃で30分間熱処理を施した。次い
で、このウエハの表面にCMSを塗布し、厚さ0.5
μmのレジスト膜を形成した。このレジスト膜を
110℃で30分プリベークした後、加速電圧20KVの
電子ビームを照射量2×10-6C/cm2で照射し、
CMSに最少パターン寸法1μmのMOSトランジ
スタのゲート回路パターンを描画した。次いで、
これをアセトンとイソプロピルアルコールの混合
液で現像した後、イソプロピルアルコールでリン
スし、120℃で30分間ポストベークし、Mo上に、
電子ビーム照射を行なつた部分にのみ厚さ0.4μ
mのCMSが残存したSiウエハを得た。
Example After Mo was deposited on a Si wafer to a thickness of 0.3 μm by electron beam evaporation in vacuum, it was taken out into the atmosphere and heat-treated at 180° C. for 30 minutes. Next, CMS is applied to the surface of this wafer to a thickness of 0.5
A resist film of μm thickness was formed. This resist film
After prebaking at 110℃ for 30 minutes, it was irradiated with an electron beam with an acceleration voltage of 20KV at a dose of 2×10 -6 C/cm 2 .
A gate circuit pattern of a MOS transistor with a minimum pattern size of 1 μm was drawn on CMS. Then,
After developing this with a mixture of acetone and isopropyl alcohol, rinsing with isopropyl alcohol and post-baking at 120°C for 30 minutes,
Thickness 0.4μ only on the part where electron beam irradiation was performed
A Si wafer with residual CMS of m was obtained.

このウエハを、フレオンガスと酸素の混合気体
を用いてプラズマエツチングを行なつたところ、
Moエツチング速度は蒸着Moのそれと同じであ
り、しかもウエハ全面が一様にエツチングされ、
パターン寸法精度及びパターン形状共に良好な高
品質のMoのゲート回路パターンを形成すること
ができた。
When this wafer was subjected to plasma etching using a mixture of Freon gas and oxygen,
The Mo etching speed is the same as that of vapor-deposited Mo, and the entire wafer is etched uniformly.
A high-quality Mo gate circuit pattern with good pattern dimensional accuracy and pattern shape could be formed.

比較例 Moを付着させたSiウエハを大気中に取出し、
直ちに(熱処理を行なわずに)その上にCMSを
塗布した以外は、実施例1と同じ材料及び操作に
よりエツチングまでの工程を終了した。
Comparative example A Si wafer with Mo attached was taken out into the atmosphere.
The steps up to etching were completed using the same materials and operations as in Example 1, except that CMS was immediately applied thereon (without heat treatment).

その結果、CMSで被覆されていない部分のMo
エツチング速度は、蒸着Moのそれの1/3と小さ
く、かつ不均一なエツチングがなされ、良好な
Moのゲート回路パターンを形成することができ
なかつた。
As a result, the Mo
The etching speed was 1/3 that of vapor-deposited Mo, and the etching was uneven and good.
It was not possible to form a Mo gate circuit pattern.

以上説明したように、本発明によれば、不均質
なエツチング及びエツチング速度の低下を防止し
高品質のMoパターンをSiウエハ等の上に形成す
ることができる。
As described above, according to the present invention, a high quality Mo pattern can be formed on a Si wafer or the like while preventing non-uniform etching and reduction in etching speed.

Claims (1)

【特許請求の範囲】[Claims] 1 Mo基体上にクロルメチル化ポリスチレンを
塗布してレジスト膜を形成し、該レジスト膜に遠
紫外線、粒子線又はX線を照射して所定のパター
ンを描画し、現像処理を施してMo基体上に該レ
ジスト膜のパターンを形成し、次いで該パターン
をマスクとしてMo基体をエツチングするMoパタ
ーンの形成方法において、クロルメチル化ポリス
チレンを塗布する前に予めMo基体の表面をMo酸
化物で被覆することを特徴とするMoパターンの
形成方法。
1. A resist film is formed by coating chloromethylated polystyrene on a Mo substrate, and a predetermined pattern is drawn by irradiating the resist film with deep ultraviolet rays, particle beams, or X-rays. A method for forming a Mo pattern in which a resist film pattern is formed and then a Mo substrate is etched using the pattern as a mask, characterized in that the surface of the Mo substrate is coated with Mo oxide in advance before applying chloromethylated polystyrene. A method for forming a Mo pattern.
JP10125280A 1980-07-25 1980-07-25 Formation of mo pattern Granted JPS5727029A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10125280A JPS5727029A (en) 1980-07-25 1980-07-25 Formation of mo pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10125280A JPS5727029A (en) 1980-07-25 1980-07-25 Formation of mo pattern

Publications (2)

Publication Number Publication Date
JPS5727029A JPS5727029A (en) 1982-02-13
JPS6137774B2 true JPS6137774B2 (en) 1986-08-26

Family

ID=14295717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10125280A Granted JPS5727029A (en) 1980-07-25 1980-07-25 Formation of mo pattern

Country Status (1)

Country Link
JP (1) JPS5727029A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123373A (en) * 1983-12-06 1985-07-02 齋藤 武雄 Heating vessel by latent heat
JPS6299558U (en) * 1985-12-13 1987-06-25
ATE69780T1 (en) * 1986-07-02 1991-12-15 Brava Australia Pty Limited HEAT-INSULATED CARRYING BAG.
JP2537286Y2 (en) * 1991-08-21 1997-05-28 日野自動車工業株式会社 Mounting structure of resin parts
KR100858297B1 (en) * 2001-11-02 2008-09-11 삼성전자주식회사 Reflective-transmissive type liquid crystal display device and method of manufacturing the same

Also Published As

Publication number Publication date
JPS5727029A (en) 1982-02-13

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