DE2554450A1 - Integrated circuit prodn. with FET in silicon substrate - with polycrystalline silicon gate electrode and planar insulating oxide film - Google Patents

Abstract

Oxidising part of the substrate to form an insulating SiO2 film involves forming the insulating film in such a way that a planar surface is obtd. using the oxide grown in both directions. Pref. the insulating layer is formed directly on the substrate or by partial oxidn. of a polycrystalline Si film. The process utilises the fact that SiO2 forms in an O2 atmos. half by diffusion of O2 into the SiO2, already formed and by expansion in vol. A new surface results which is half the thickness of the insulating oxide film higher than the original surface. By removal of this oxide film and reoxidn. the surface can be made level with the original plane or even lower, so that sharp edges are avoided. This procedure can be used with both monocrystalline and polycrystalline Si. The claims cover the prodn. of the insulating film using suitable masks and also doping by diffusion or ion implantation.

Description

Process for manufacturing an integrated circuit

The invention relates to a method for producing an integrated Circuit in which there is at least one field effect transistor in a silicon semiconductor substrate introduced with a gate electrode made of polycrystalline silicon and where parts of the surface have a silicon dioxide layer as an insulation layer is formed by oxidation of the silicon semiconductor substrate.

An essential part of integrated circuits are the individual components of the circuit interconnecting conductor tracks. In the In most cases, contact-free crossovers of conductor tracks are required, see above that the circuit must have at least two wiring levels that oppose each other are separated by an insulation layer.

This means that on which the components of the integrated circuits containing semiconductor substrate in a sequence a first insulation layer, Conductor tracks of the first wiring level, a second insulation layer, conductor tracks the second wiring level and finally a third insulation layer is provided Need to become. Of course, there are also electrical connections between the electrodes of the individual components and the conductor tracks of the two wiring levels as well as between the two wiring levels. To do this, the individual layers of insulation, certain structures with windows respectively Openings through which these connections are made.

The structuring of the insulation layers now inevitably leads to Edges to which, as in contact holes, a conductor track does not adhere well May have cracks that lead to failure of the entire circuit.

For this reason, when designing integrated circuits, it is essential to that edge or contact hole problems are largely avoided. To the This problem was solved with insulation layers made of phosphor glass Certain adhesion promoters for photoresist have already been developed, which prevent the adhesion of a Improve the conductor track on the insulation layer.

However, such adhesion promoters do not work completely reliably. Attempts have also been made to use the insulation layers at suitable points to equip different layer thicknesses that "sharp" edges are avoided as much as possible will.

Such a procedure, however, is complex, since it is separate Resist and etch techniques are required.

About the undercuts that inevitably occur when the contact holes are etched avoidance has already been suggested (compare DT-OS 2 352 331) the external Edge area of the conductor track made of silicon as a whole in an insulator to convert. For this purpose, a thermal oxidation of the very small dimensions is required Edges required, which makes this process expensive.

So far, so-called intermediate oxide has been used for the insulation layers or "Elowglas" is used, which is a high phosphorus, low-melting, Hygroscopic glass is very sensitive to moisture absorption and in the electric field becomes aggressive and therefore in a short time, for example through cracks in the protective oxide at 50 0C and 85 ~ relative humidity to the complete destruction of the component can lead.

It is therefore the object of the invention to provide a method that the Manufacture of integrated circuits is allowed where there are edges and level differences the surfaces of each Layers should be avoided if possible; the procedure should be done by repeatedly applying the same steps as for For example, deposition, oxidation, implantation or diffusion can be carried out.

This object is achieved according to the invention in that the insulation layer is applied so that taking advantage of the oxidation of silicon in both Directions growing oxide creates a flat surface of the insulation layer.

The invention thus exploits the fact that silicon dioxide in an oxygen atmosphere half by diffusion of oxygen into the already formed silicon dioxide and forms by volume inflation. This creates a new surface that is half the thickness of that used as an insulation layer Oxide layer is higher than the original surface. By removing the oxide layer and re-oxidizing, the surface may or may not be leveled with the original plane be lowered below this level. Through targeted application of this process both On monocrystalline as well as on polycrystalline silicon components for integrated circuits are produced, in which the otherwise occurring at edges There are no disadvantages.

Further features and details of the invention emerge from the following description of exemplary embodiments on the basis of the figures. Show it: 1 to 10 show a first embodiment of the invention for producing a n-channel field effect transistor in silicon gate technology, with the pn transitions be produced by diffusion, and Figures 11 to 13 show a second Embodiment of the invention for producing an n-channel field effect transistor in silicon gate technology, where the pn junctions are produced by ion implantation will.

On a p-type silicon semiconductor substrate 1 is a Masking serving silicon nitride layer (Si3N4) 2 is formed. Then will the surface of the semiconductor body 1 is oxidized in a moist oxygen atmosphere (first oxidation). This forms on the exposed from the silicon nitride layer 2 Surface areas of the semiconductor substrate 1 with a silicon dioxide layer 3 the volume inflation discussed above. Then the silicon dioxide layer 3 etched with hydrofluoric acid. The field doping (zone 4 in FIG. 4) can be provided by a boron coating or made by ion implantation. After another oxidation in a moist oxygen atmosphere (second oxidation) occurs, which is shown in Fig. 4 shown arrangement with a silicon dioxide layer 6, which is a layer thickness of 1 / µm.

If necessary, the p + -conducting zone 4 can now also be made by diffusion of gallium are formed by the silicon dioxide layer 6. Then will the silicon nitride layer 2 is etched away with hot phosphoric acid. A third follows brief oxidation in a dry oxygen atmosphere, so that on the after the etching of the silicon nitride layer 2 exposed part of the surface of the semiconductor substrate 1 forms a silicon dioxide film 7 with a layer thickness of about 1,200 i. This Film 7 serves as a gate oxide (Fig. 5).

With a photoresist layer 8 (Fig. 6) is in the silicon dioxide film 7 a window 9 introduced. The window 9 preferably leads to the edge of a part 11 of the semiconductor substrate 1. After the photoresist layer 8 has been removed, the entire area a first polycrystalline silicon layer having a Layer thickness d1 deposited, which is structured by means of a photoresist layer 13 so that polycrystalline layers 12 remain. The left part of layer 12 in the 7 can also completely cover the window 9.

The right part of the layer 12 in FIG. 7 lies approximately in the middle the surface of the part 11 of the semiconductor substrate 1.

It is therefore important that the polycrystalline layer 12 be identical of the window 9 does not need to be adjusted. Then the exposed Parts of the silicon dioxide film 7 are etched away (gate oxide etching). Then there is a diffusion carried out, which leads to n-conductive zones 14, 16 (see FIG. 8). These zones 14, 16 can optionally also be produced by ion implantation (cf. the embodiment of FIGS. 11 to 13). After removing the photoresist layer 13 a second polycrystalline silicon layer 17 is deposited over the entire surface, which has a layer thickness d2 = d1. On this polycrystalline silicon layer 17, a structured silicon nitride layer 18 serving as a mask is applied. Subsequently, the parts of the silicon nitride layer 18 exposed are polycrystalline silicon layer 17 is oxidized. As a result of the volumetric flow, there is flatulence in this oxidation (compare above) because of the condition d1 = d2 and because of the approximate coverage of the layer 12 by the layer 18 (Fig. 8) a substantially flat surface, as indicated in FIG. 8 by a dashed line 19. The fact that when silicon is oxidized, volume inflation occurs.

In this way, the arrangement shown in FIG. 9 is produced with a polycrystalline silicon layer 21 (layers 12 and 17), a polycrystalline Silicon layer 22 (layers 12 and 17) and a silicon dioxide layer 23 (in 8 right half of layer 6 and the oxidized parts of the polycrystalline Silicon layer 17). On this arrangement becomes after the etching the silicon nitride layer 18 deposited a silicon dioxide layer 24 made of silane. The layer 24 can also by oxidation of a previously deposited polycrystalline Silicon layer are formed.

Another photoresist and etching technique is used to create the layer 23 a window 26 introduced. Polycrystalline silicon is then applied over the entire surface deposited, which is then structured by means of a further photoresist and etching technique so that only in window 26 and on parts of the surface of the silicon dioxide layer 23 a polycrystalline silicon conductor track 27 remains. Eventually the entire arrangement for shielding against moisture and environmental influences with a polyimide film 28 covered.

The arrangement shown in Fig. 10 has two wiring levels: The first wiring level consists of layers 21 and 22, the second wiring level from the conductor track 27.

An exemplary embodiment will now be described in greater detail with reference to FIGS. 11 to 13 explained, in which the diffusion of the zones 14, 16 by ion implantation through the silicon dioxide film (gate oxide) 7 is replaced.

In Figs. 11 to 13, corresponding parts with the The same reference numerals are provided as in FIGS. 1 to 10.

First, the semiconductor body 1 is treated as shown in FIG Fig. 1 to 6 is explained. After the photoresist layer 8 has been detached, the in the arrangement shown in Fig. 11, in which additionally through the window 9 a highly doped n + -conductive zone 31 is introduced by diffusion. Afterward a polycrystalline silicon layer 32 is deposited over the entire area. With help the photoresist and etching technology becomes one structured silicon nitride layer 33 produced, in the following ion implantation with the help of a by arrows 34 indicated phosphor ion beam, the photoresist layer 36 serves as an ion beam mask. The ion implantation creates the n-conductive zones 14, 16. With this type of doping remains the interface between the semiconductor substrate 1 and the silicon dioxide (Film 7) with the exception of the contact holes without any kind of etching.

After the photoresist layer 36 has been peeled off, oxidation takes place in the moist Oxygen atmosphere carried out. As a result, those from the silicon nitride layer are oxidized 33 exposed parts of the polycrystalline silicon layer 32 to silicon dioxide, so that the arrangement shown in FIG. 13 arises, in which the right part the silicon dioxide layer 6 and those provided thereon and the silicon dioxide film 7 Divide the polycrystalline silicon layer 32 into a silicon dioxide layer 37 are converted. Since the silicon nitride layer 33 has approximately the same layer thickness as the polycrystalline silicon dioxide layer 32 possesses, that by volume inflation silicon dioxide layer 37 formed has the same plane as the silicon nitride layer 33.

This structure is further treated as shown in Figs.

9 and 10 is shown.

Of course, the invention can also be used to produce a p-channel field effect transistor be used. The diffusion of the zones 14, 16 with gallium by a thin thermal silicon dioxide layer made in the semiconductor substrate 1.

The invention enables the production of integrated circuits, the difficulties that otherwise occur at edges are largely avoided. The procedure is repeated through Applying the same Steps: Deposition, oxidation, diffusion or implantation can be carried out easily. It is avoided that layers are etched which finally remain. this applies in particular to the gate oxide under the edge of that of polycrystalline silicon existing gate electrode. The semiconductor substrate is during the various Process sequences against moisture completed. Materials susceptible to corrosion, such as For example flow glass or metals are avoided. Evaporation processes for manufacture the metal contacts are not required.

12 claims 13 figures

Claims (12)

Method for producing an integrated circuit, with at least one field effect transistor in a silicon semiconductor substrate a gate electrode made of polycrystalline silicon is introduced and a silicon dioxide layer as an insulating layer on parts of the surface is formed by oxidation of the silicon semiconductor substrate, d a d u r c h g e k e n n -z e i c h n e t that the insulation layer is applied in such a way that using that which increases in both directions when silicon is oxidized Oxide creates a flat surface of the insulation layer. 2. The method according to claim 1, d a d u r c h g e k e n n -z e i c h n e t that the insulation layer is directly on the silicon semiconductor substrate is provided. 3. The method according to claim 1, d a d u r c h g e k e n n -z e i c h n e t that the insulation layer by partial oxidation of a polycrystalline Silicon layer is created. 4. The method according to claim 2, d a d u r c h g e k e n n -z e i c h n e t that a structured silicon nitride layer on the semiconductor substrate (1) (2) the surface portions exposed from the silicon nitride layer (2) are generated of the semiconductor substrate (1) are oxidized in a moist oxygen atmosphere, so that a silicon dioxide layer (3) arises that the silicon dioxide layer (3) in Hydrofluoric acid is etched off that on the exposed from the silicon nitride layer (2) Surface areas of the semiconductor substrate (1) again a silicon dioxide layer (6) is formed by oxidation in a moist oxygen atmosphere. 5. The method according to claim 4, d a d u r c h g e k e n n -z e i c h n e t that the silicon nitride layer (2) is etched off in hot phosphoric acid, that the exposed surface areas of the silicon nitride layer (2) Semiconductor substrate (1) are thermally oxidized, so that a thin silicon dioxide film (7) as gate oxide arises that in this silicon dioxide film (7) a window (9) is introduced that a polycrystalline silicon layer (12) is deposited over the entire area that is structured by means of a photoresist and etching technique that then a second polycrystalline Silioltun layer (17) with the same layer thickness (d2) how the first polycrystalline silicon layer (12) is deposited that this second polycrystalline silicon layer in certain areas with a silicon nitride layer (18) is covered, and that those exposed by the silicon nitride layer (18) Areas of the second polycrystalline silicon layer (17) are oxidized so that a flat surface is created. 6. The method according to claim 5, d a d u r G h g e k e n n -z e i c h n e t that the silicon nitride layer (18) is applied in a pattern that corresponds to the first polycrystalline silicon layer (12). 7. The method according to claim 6, d a d u r c h g e k e n n -z e i c h n e t that the first and second polycrystalline silicon layers (12; 17) respectively be applied with a layer thickness of about 0.4 / µm. 8. The method according to claim 1, d a d u r c h g e k e n n -z e i c h n e t that on the semiconductor substrate a Siliciunidioxidschicht (6, 7) with a Window (9) to the semiconductor substrate (1) is applied that on the silicon dioxide layer (6, 7) a polycrystalline silicon layer (32) is deposited that on the polycrystalline silicon dioxide layer (32) a structured Silicon nitride layer (33) with the same layer thickness as the polycrystalline silicon layer (32) is generated, and that the exposed from the silicon nitride layer (33) Areas of the polycrystalline silicon layer (32) are oxidized so that after the resulting silicon dioxide layer (37) is the same as the volume inflation Has plane like the silicon nitride layer (33). 9. The method according to any one of claims 1 to 8, d a d u r c h g e it is not possible to indicate that the doping of ZG-nen (14, 16) of a certain Leltbarkeit takes place in the semiconductor substrate (1) by diffusion. 10. The method according to any one of claims 1 to 8, d a d u r c h g e it is not possible to indicate that the doping of zones (14, 16) of a certain Conductivity in the semiconductor substrate (1) by ion implantation through a polycrystalline Silicon layer (32) takes place, and that a silicon nitride layer (33) as an ion beam mask is used. 11. The method according to claim 9, d a d u r c h g e k e n n -z e i c h n e t that the zones (14, 16) are doped with gallium by diffusion a thin layer of silicon dioxide occurs. 12. The method according to claim 10, d a d u r c h g e k e n n -z e i c h n e t that doping with phosphorus by implantation through a gate oxide serving thin silicon dioxide layer and a silicon nitride layer takes place.