JPS60150651A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To stop pinholes, created during processes wherein an insulating film is exposed to light with the intermediary of photomasks or resists, from penetrating the insulating film deep enough to reach a lower layer wiring by a method wherein the insulating film is allowed to remain partially unaffected after selective etching of a region planned for an aperture in the insulating film and etching is repeated after a second resist application. CONSTITUTION:A lower layer wiring 2 of Al and then an SiO2 insulating film 3 is formed to coat an Si substrate 1, and a photoresist 8 is laid by the application method. A photomask 10 is aligned, region 18 for an aperture is exposed to a light beam 13. Selective etching is performed to attack the insulating film 3, which comes to a halt before reaching the lower layer wiring 2. The resist 8 is removed, second resist 9 is applied, photomask 10a of the same pattern is aligned, exposure is allowed to the light beam 13, resist 9 is removed, and then selective etching is performed to affect the insulating film 3. Even when the etching process for the region 18 planned for an aperture proceeds through the insulating film to reach the lower layer wiring 2, the pinholes 11, 12, 19, 20 created in the previous manufacturing processes do not reach the lower layer wiring 2. There will be no short circuits between the lower layer wiring 2 and an upper layer wiring to be provided later.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a method for forming a pinhole-free insulating film in multilayer wiring of semiconductor integrated circuits. [Prior art and problems thereof] Generally, multilayer wiring of semiconductor integrated circuits When providing an electrode layer,
Pinholes that occur in the insulating film may cause short circuits between upper and lower wiring electrodes, or may cause inconveniences such as the underlying wiring being etched through the pinholes and causing disconnections.
In order to prevent these problems, a method of forming two layers of insulating films, for example, is conventionally known. That is, as shown in a cross section of a part of a semiconductor integrated circuit in FIG. 1, a first insulating film 3 made of silicon oxide and a second insulating film 3 made of silicon nitride are coated on a lower wiring 2 provided on a silicon substrate 1. After the film 4 is formed, windows are formed at predetermined locations by photo-etching, and the upper layer wiring 5 is deposited thereon.

In this method, pinholes caused by each insulating film quality occur at four locations in both the first insulating film 3 and the second insulating film 4, and the probability that these pinholes will match is extremely low. It is possible to almost completely prevent the upper layer wiring 5 and the lower layer wiring 2 from penetrating the insulating films 3 and 4 by means of a pinhole communicating with each other.

However, if there is dust in the photoresist used to carry out the above process, or if the light-shielding part of the photomask is partially incomplete and forms a hole-like shape that does not allow light to pass through, these pinholes may become two. Since this corresponds to the same location of the insulating films 3 and 4, the insulating films 3 and 4 are selectively etched, the resist is removed, and the upper layer wiring 5 is deposited.
As a result, as shown in FIG. 2, a pinhole 6 is formed that penetrates the upper layer wiring 5 and the lower layer front M42, and in this case, the effectiveness of using 2N4 as the insulating film is lost. There is a drawback that it is impossible to prevent contact or disconnection between the upper and lower wiring electrode layers due to the pinhole 6.

Furthermore, since the insulating film is made of two layers, the second insulating film 4 remains in an overhang state shown by 7 as shown in FIG. 3, and the upper layer wiring 5 is cut and connected at this sharp corner. There is also a risk that it will become defective.

In addition, as a simple and inexpensive method different from the above, the insulating film is
It is also known to use ii1 and double coat the resist. That is, as shown in FIG. 4, a first resist 8 and a second resist 9 are coated on top of the insulating film 3, and exposed using a photomask 10. If there is a pinhole 11 caused by dust or a pinhole 12 caused by the photomask 10, the pinhole will occur at the same location even if 2L of resist is applied, so the result will be the same as shown in Figure 2. Therefore, short circuit or disconnection between the upper layer wiring 5 and the lower layer wiring 2 cannot be prevented.

Furthermore, in this method, since the thickness of the applied resist becomes large, as shown in FIG. exposure, first resist 8
There is also the disadvantage that unreacted areas 14 of the resist remain because the light does not reach sufficiently below the resist. The pinholes produced in the resist in FIG. 5 are due to pinholes 11 in the resist and pinholes 12 caused by the photomask IO.

Next, when the insulating film 3 is selectively etched, it becomes as shown in FIG. 6, but the unreacted portion 14 of the resist shown in FIG.
The insulating film 3 at the location opposite to the etching is not etched, leaving a portion 15, and at the same time, pinholes 16 caused by the resist and pinholes 17 caused by the photomask are formed in the insulating film 3. Ru.

As described above, as a measure to prevent the occurrence of pinholes in the insulating film between electrode layers in multilayer wiring of semiconductor integrated circuits, the conventional method of providing a two-layer insulating film and the alternative insulating film are available. With methods such as one layer and two resist layers, if there is dust in the resist or defects in the light shielding part of the photomask, pinholes that are caused by these in the insulating film can be removed. I can't do it,
In the past, it was not possible to avoid short circuits between the upper layer wiring and the lower layer wiring, or the etching solution intruding into the lower layer wiring, causing disconnection.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method that eliminates the above-mentioned drawbacks and does not cause pinholes to occur in an insulating film provided between an upper layer wiring and a lower layer wiring in a multilayer wiring of a semiconductor integrated circuit.

[Key points of the invention]

In the present invention, a lower layer wiring and an insulating film are provided on a silicon substrate, and when selectively etching the insulating film in the window area using photoetching technology, the etching depth is set so as not to penetrate to the lower layer wiring, and the insulating film is completely etched. The insulating film is removed from the p1 window area by leaving the remaining area and applying resist again, and repeating the same etching operation for the window area, but the insulating film is removed from the p1 window area, which is caused by the photomask and resist. The pinhole-based photosensitive area is designed so that the insulating film does not penetrate to the lower layer wiring, and short circuits between the wirings do not occur even after the upper layer wiring is formed.

[Embodiments of the invention]

The present invention will be explained below based on examples.

7 to 12 show a cross section of a part of a semiconductor integrated circuit according to the procedure according to the method of the present invention, and parts common to those in FIGS. 1 to 6 are designated by the same reference numerals. .

First, as shown in FIG. 7, aluminum is deposited on a silicon substrate 1, a lower layer wiring 2 and an insulating film 3 of silicon dioxide are formed, and a first photoresist 8 is applied. It is assumed that pinholes 11 are present in the applied first resist 8 due to, for example, dust attached to the insulating film 3.

Next, as shown in FIG. 8, the photomask 10 is aligned, but if there is a pinhole 12 in the photomask 10 due to a hole in the light-shielding part, etc., if it is exposed to light 13 in the direction indicated by the arrow, In the bright region, the portion 18 of the first resist 8 facing the pinhole 12 of the photomask 10 is exposed to light.

Furthermore, when selectively etching the insulating film 3, as shown in FIG. 9, the etching depth of the insulating film 3 should be kept at a position where the etching depth does not reach the lower wiring 2, #1 is about the thickness of the insulating film #3. 0 Etched portion M18a of oxide film 3 in FIG.
, lla, 12al'i The window in FIG. 8 is part 18. B/Hole 11. It corresponds to pinhole 12. Note that in FIG. 9, the first resist 8 is removed.

In this state, as shown in FIG.
A resist 9 is applied. At this time, as shown in FIG. 7 where the first resist 8 is applied first, it is assumed that the second resist 9 applied for the second time also has pinholes 19 at different locations from the first resist 9.

Next, another photomask 10a having the same pattern as that used in FIG. 8 is put together as shown in FIG. When the light 13 is exposed in the same way as in Figure 8, where there is a pinhole 19 due to a hole in the photomask 10a, the second resist 90 portion facing the part 8 and the pinhole 20 of the photomask 10a is exposed. Be exposed to light.

Next, the Shimakoki resist 9 is removed and the insulating film 3 is selectively etched. At this time, as shown in FIG. 12, the window etched on top of the first etching is applied to the part 8, even when the etching depth reaches through the insulating film 3 to the lower layer #12. The shallow etching is not performed on the portions of the insulating film 30 corresponding to the pinholes, which are only subjected to the second etching. Note that FIG. 12 shows the state after removing the M2 resist. Therefore, even if the upper layer wiring is attached thereafter, there will be no short circuit with the lower layer wiring.

As described above, according to the method of the present invention, ii: Since the resist applied the i-th time is completely removed, the probability that the pinholes of the resist applied the first time will overlap with the pinholes of the resist applied the second time is very high. Moreover, if the photomask used for the first exposure and the photomask for the second exposure have the same pattern but are different, the probability that the pinholes formed by these two photomasks will overlap is also extremely small. .

A probabilistic consideration of the occurrence of pinholes in the present invention will be described below.

The number of resist pinholes generated in one chip of the substrate by one resist application, t - m, the area of one pinhole is acIA, and the number of pinholes existing in one step of one photomask is The number is n.

For example, even if a pinhole occurs in the interlayer insulating film in two-layer wiring, if the pinhole does not connect the wiring layers, the electrical characteristics of this integrated circuit are In some cases, there is no damage, so if there is a pinhole in one chip, the electrical performance will be poor. If f: cal, then one pinhole in one chip. If the probability that the chip has defective characteristics is It, then t=Ω, where Aca is the area of one chip. Therefore, if p is the probability that the electrical characteristics of the chip will be good after one resist application, exposure, and etching as usual, it is sufficient if all m and n pinholes are not in positions where the physical properties are poor. Therefore, p is expressed by the following formula.

p=(1-t)"(1-t)=(1-t)"+"
On the other hand, resist coating and exposure as in the present invention.

When etching is performed twice and different photomasks with the same pattern are used for the first and second exposures, Figure 13 shows the number of overlapping pinholes k created by the two resist coatings. This relationship is based on the assumption that the average size pinhole in resist coating is circle 21, and the center 0 of circle 22, which is assumed to be a pinhole in the second resist coating, is circle 2.
When the pinholes 1 and 23 are located within the area of the circle 23 having four times the area, one pinhole overlaps.

Therefore, for each pinhole in the second resist coating, there are a number of Kerrs. Similarly, pinholes are created by a photomask.

Therefore, the resist coating, exposure, and etching steps are performed twice, and the following equation is obtained since it is unnecessary to perform the resist coating, exposure, and etching processes twice to avoid another defective photomass characteristic of the same pattern.

In addition, in the present invention, when the process of resist application, exposure, and etching is performed twice and a photomask with a gap between exposures is used, the probability r that l chip will have good characteristics is as follows: This is because there are n pinholes created by the photomask.

Here, for example, the area of the chip A = 107μR = 10 The area of the pinhole in the resist a = 2μM The area of the pinhole in the photomask b = 1μ The area where the characteristics will be defective due to the presence of the pinhole c = 10
6 μm' = 1 2 Number of pinholes in resist m = 2 Number of pinholes in photomask 2 = 1 then p
=(1'-0,1)2+10.73=0.9+=0.
9999998 is obtained.

From the above equations, it can be seen that according to the method of the present invention, it is possible to prevent short circuits due to pinholes between upper layer wiring and lower layer wiring in multilayer wiring of a semiconductor integrated circuit with a probability as high as 99.99998.

It goes without saying that if the number of repetitions of the seven otolithography steps of resist coating, exposure, and etching is increased, the probability of pinholes overlapping will further decrease.

〔Effect of the invention〕

As explained above in the embodiments, according to the present invention, in order to prevent pinholes from occurring in the insulating film between the upper and lower wirings in the multilayer wiring of a semiconductor integrated circuit due to the photoresist or photomask used in the manufacturing process, After applying a resist to the insulating film formed on the lower wiring, the insulating film is selectively etched by exposure using a photomask with a predetermined pattern, and the etching depth is kept at approximately the middle of the thickness of the insulating film. After removing the resist, the above process is repeated once again, that is, a second resist is applied, exposed using another photomask with the same pattern, and the insulating film is selectively etched again. By increasing the etching depth to only reach the underlying wiring, pinholes caused by the photoresist or fort mask have less chance of aligning due to the second photolink roughy - the first etch is less likely to result in an insulating layer. Since it is designed to prevent the pinholes from penetrating the film, unless there is a very small probability that the pinholes overlap, there is a risk that the wiring will be short-circuited or disconnected due to full communication in the insulation film between the upper layer wiring and the lower layer wiring after the upper layer wiring is deposited. This makes it possible to obtain multilayer wiring with good reproducibility and stable electrical characteristics without causing problems.

Furthermore, the method of the present invention also solves the drawback of the prior art that overhang occurs when the insulating film is made of two layers.

[Brief explanation of drawings]

Figures 1 to 3 are top views of the imitation part showing a two-layer thin film structure in a semiconductor integrated circuit that uses conventional multilayer wiring;
5 to 6 are side views of the resist 2M (representing the application of a loose part), FIGS. Application, Figure 8 shows mask alignment, Figure 9 shows selective etching of the insulating film, Figure 10 shows second resist application, first
Figure 1 is the same mask alignment, Figure 12 is the same style, H
FIG. 13 is a side view of the main part showing the selective etching of the pinhole, and a schematic explanatory diagram showing the overlapped pinhole. 1...Silicon substrate, 2...Lower layer arrangement n, 3.4...Mineral film, 6.11.12.16.
17.19.20...Pinball, 8,9...
...Photoresist, 10,10a...
Photomask, 13... Direction of light, 18...
...Mado Akira is a club. ! 2 years old 6 fig.

Claims (1)

[Claims] 1) In a method for forming an insulating film provided between multilayer wiring electrodes of a semiconductor integrated circuit, a 7-photoresist is applied to an insulating film formed on a lower wiring layer adhered to a semiconductor substrate, and exposed using a photomask. The first step is the selective etching of the insulating film that does not reach the underlying wiring, and then the insulating layer is coated with photoresist on the [%] surface, and the same etching depth that is not used in the first step is performed. After aligning and exposing the patterned photomask, at least one second step of selectively etching the insulating film;
1. A method of manufacturing a semiconductor device, characterized in that the etching depth of a predetermined window portion is stopped when the etching depth reaches a lower layer wiring.