JPS5850026B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and its purpose is to improve the manufacturing yield of electrode wiring formation when integrated circuits become denser and larger and require fine pattern formation. It is.

As a method for forming fine electrode wiring for high-density integrated circuits, the applicant proposed in Japanese Patent Application Nos. 50-43969 and 50101336 a method using a two-layer mask pattern (two-layer photoresist) for electrode formation.

However, it has been discovered that this method also has problems that need to be improved.

Firstly, Japanese Patent Application No. 50-43969 uses an electrode wiring photomask twice and performs high-precision mask alignment to form fine electrode wiring. It has been found that if the thickness is not within 3 microns, disconnection or short-circuiting of the electrode wiring will occur, leading to a decrease in manufacturing yield, and this becomes more pronounced as the finer patterns become 3 microns or less.

Furthermore, to explain the method of the above-mentioned No. 50-43969 with reference to FIG. Then, an AI film 3 is deposited on the first photoresist pattern 2 and the exposed Si substrate 1.

Furthermore, a photoresist is coated on the AI film, and then high-precision mask alignment is performed using the photomask used when forming the first photoresist pattern 2, and a second photoresist is applied only on the exposed Si substrate 1. After forming the photoresist pattern 4 of c1, the second photoresist pattern 4 is formed.
Using as an etching mask, a part of the AI film 3 is etched until the surface of the first photoresist pattern 20 is exposed, and then the first and second photoresist patterns 2 are etched.
, 4 to obtain AII line pattern 5.e.

The problem at this time is the first photoresist pattern 2.
The second photoresist pattern 4 is applied with high accuracy (±0.5
This is something that must be done by aligning masks with a precision of microns (microns or higher).

This is because the mask alignment is 1 as shown in Figure 1.
If the etching occurs even by a micron, a part of the A1 film 3 on the Si substrate 1 will be exposed (C in FIG. 1) and etched.If the pattern becomes a fine pattern, even a small amount of side etching will cause the AI wiring pattern 5 to be etched in the first place. As shown in FIG. d, the probability of defects and disconnections increases, and the predetermined A1 wiring pattern 5 cannot be formed in the electrode wiring region 6.

In particular, this probability becomes extremely high when the wiring crosses a step formed on the Si substrate 1.

Further, in Japanese Patent Application No. 101336/1984, the second photoresist pattern is formed by plasma etching and no mask alignment process is required, so defects due to mask alignment do not occur, but the following problems arise.

To explain this with reference to FIG. 2, the Si substrate 11
The steps up to step a of forming the first photoresist pattern 12 thereon and depositing the Al film 13 thereon are the same as the previous method, so the explanation will be omitted.
b, and the surface of the second photoresist film 14 is coated with the first photoresist film b.
Etching is performed using an oxygen gas plasma method or a solvent until the AI film 13 on the first photoresist pattern 12 is exposed.
2 and the electrode wiring area 15 and when the distance between the electrode wiring areas 15 is wide (for example, the pattern size is 10 microns or more), the film thickness 16 of the second photoresist film 14 on the electrode wiring area 15 and the first photoresist pattern 12
The film thickness 17 of the upper second photoresist film 14 is approximately the same film thickness.

In other words, the wider the electrode wiring region 15 and the distance between the electrode wiring regions 15, the closer to the same thickness.

On the other hand, if the electrode wiring regions 15 and the spacing between them are small (for example, less than 10 microns), there is no problem that the film thickness difference may be several times larger.

Therefore, if the area is wide, the AI film 13 on the electrode wiring area 15
The electrode forming region 150A1 film is exposed with a portion of the second photoresist pattern 18 remaining only slightly near the boundary between the electrode wiring region 15 and the first photoresist pattern 12 5c.

In this state, when the AI film 13 is etched using the second photoresist pattern 18 as an etching mask, the A1 wiring pattern 19 is completely etched in the electrode wiring area 15 as shown in d.
cannot be left behind.

That is, the photoresist that must remain on the electrode formation region 15 is removed at the same time as the photoresist located on the electrode formation region 12 is removed, and the predetermined A1 film 19 does not remain on the entire electrode formation region 15.

This development becomes more pronounced as the pattern of the electrode formation region 15 becomes larger, and when the size becomes about 50 μm, this phenomenon cannot be eliminated no matter how the etching conditions are selected.

Therefore, when the remaining photoresist (12.18) is removed, an AI wiring pattern 19 which is much narrower than the designed value is formed as shown in e.

In the method shown in FIG. 1, the second resist pattern is formed using the mask used to form the first resist pattern, so if there is even a slight misalignment of the mask, the A1 wiring pattern becomes thin or breaks.

Although the method shown in FIG. 2 is effective for fine wiring pattern parts, it is inconvenient for wide wiring pattern parts.

The present invention improves mask alignment accuracy by removing almost the entire second protective film other than the electrode wiring area and at the same time leaving the second protective film (resist) pattern larger than the electrode wiring area. By etching the second protective film pattern over the entire surface of the second protective film pattern, the protective film pattern can be reliably formed in a self-aligned manner over the entire fine electrode wiring area and relatively large electrode area. This makes it possible to form.

The method of the present invention will be explained with reference to FIG.

First, the first photoresist film 23 is applied to areas other than the electrode wiring areas 22a and 22b on the 5i02 film 21' on the Si substrate 21.
After depositing an AI film 24 on the first photoresist film 23 as an etching protection film for AI and the electrode wiring regions 22a and 22b, a second photoresist film 25 is deposited as an etching protection film for AI. AI membrane 2
4, a second photoresist pattern 26 is formed uniformly from the C1 electrode wiring regions 22a and 22b by using a photomask (not shown) that is at least 1 micron wider than the normal mask and developing.d .

Here, the pattern dimensions of the photomask used when forming the second photoresist pattern 26 are as wide as 5 microns and 10 microns, as shown in L from the electrode wiring areas 22a and 22b, but good results can be obtained. obtain.

However, if L is less than 1 micron, it becomes extremely difficult in terms of uneven arrangement of photomasks and mask alignment accuracy, leading to a decrease in manufacturing yield.

In other words, the alignment unevenness is 1 micron for a 3-inch square photomask, and the mask alignment accuracy is the same (it is quite possible that there will be a deviation of about 1 micron).

By the way, the electrode wiring area 2 adjacent to the fine pattern part (for example, the interval between the electrode wiring areas 22a and 22b is 2 microns)
Second photoresist pattern 26 on 2a, 22b
It is recommended to design the photomask in a connected state as shown in Figure 3d.

In this way, if there is an overlap of 1 micron or more, the electrode wiring area
2a and 22b can be completely covered with a second photoresist pattern 26.

Next, the surface of the second photoresist pattern 26 is coated with an oxygen gas plasma method (for example, 150 W, 0.7 Torr 5
minutes) or in a solvent atmosphere (for example, in a xylene solution or vapor).
Remove by etching until completely exposed.

Here, in this embodiment, the electrode wiring regions 22a, 2
2b becomes wider, the second photoresist pattern 26 is formed only in the electrode wiring areas 22a, 22b and their vicinity, so at this time, the second photoresist pattern 26 on the first photoresist film 23 Since the thickness 27 is sufficiently thinner (for example, approximately) than the film thickness 28 of the second photoresist pattern 26 on the electrode wiring regions 22a and 22b, the second photoresist pattern 26 is etched and removed to a predetermined thickness. 3. In this way, the third photoresist film 23 is self-aligned only in the electrode wiring areas 22a and 22b according to the pattern of the first photoresist film 23, without requiring a highly accurate mask alignment process.
photoresist patterns 29 a and 29 b can be formed.

Next, a third photoresist pattern 29a.

Using etching mask 29b as an etching mask, the exposed portion of the AI film 24 is removed by etching with, for example, a phosphoric acid-based etching solution f.
, Finally, the first photoresist film 23 and the third photoresist patterns 29a and 29b are removed using, for example, a resist stripper (trade name: Jlooo), and the AI electrode wiring patterns 30a and 30b are removed as shown in g. Form.

In this way, in the method shown in Fig. 3, the second protective film (resist pattern 26) is left on the electrode wiring area wider than the electrode wiring area, so there is a margin in mask alignment accuracy for leaving the second protective film. This eliminates the possibility of abnormal etching or disconnection of the electrode wiring as shown in FIG.

Furthermore, in FIG. 3, since the second protective film other than the electrode wiring area is removed, the second protective film that is left widely is removed from the entire surface and the second protective film is applied only to the electrode area in a self-aligned manner. protective film pattern (third photoresist pattern 29a
, 29b), the electrode wiring area is 15 in Fig. 2.
Even when the resist pattern is relatively large as shown in FIG. 2C, the inconvenience of not leaving a resist pattern on the electrode wiring area 15 as shown in FIG.

That is, in the present invention, the second resist 14 in a portion having a film thickness of 17 as shown in FIG. 2, and the inconvenience of the case shown in FIG. 2 does not occur.

The above method can obtain similar results if the electrode material is not limited to AI, but is a metal or semiconductor that can be vacuum deposited.

The present invention can also be used in the same manner when an electrode wiring pattern is formed on the substrate 21 on which the 5i02 film 21' is not formed.

FIG. 4 shows the relative pattern formation yield for a 2 micron wiring pattern, assuming that the yield without surface steps according to the present invention is 1.

Here, the pattern formation yield is expressed as a total of disconnections of AI wiring and short circuits between wirings, and the pattern size for forming surface steps is also 2 microns.

Curve I shows the yield by the method of the present invention, and n and m show the yield by the methods of Japanese Patent Application Nos. 50-43496 and 101336, respectively.

In either method, the pattern formation yield decreases as the surface level difference increases, but it can be seen that the yield in the present invention is higher than in other methods.

As described above, the present invention can solve the problems previously proposed by the applicant.

In other words, the present invention does not require high mask alignment accuracy, and even if the electrode wiring area is minute, relatively large in size, and the distance between the electrode wiring areas is large, it is possible to reliably align only the electrode wiring area. The second protective film can be left on the entire surface in a self-aligned manner, making it possible to reliably form electrode wiring, greatly improving the manufacturing yield of high-density integrated circuits, and improving the manufacturing yield of this type of circuit. This will greatly contribute to the

[Brief explanation of the drawing]

Figures 1 a to e are process diagrams of wiring patterns using the method disclosed in Japanese Patent Application No. 1983-43969, and Figures 2 a to e are
A process diagram of a wiring pattern using the method of No. 101336,
3a to 3g are process diagrams for forming an electrode wiring pattern according to an embodiment of the present invention, and FIG. 4 is a curve diagram comparing the present invention and the prior application in terms of electrode pattern formation yield. 21... Si substrate, 22, 22'...
Electrode wiring area, 23...°...first photoresist film, 24...A1 vapor deposited film, 25...second photoresist film, 26... Second photoresist pattern, 29°29'...Third photoresist pattern, 30°30'...Al
Electrode wiring pattern.

Claims (1)

[Claims] 1. A step of selectively forming a first protective film in areas other than the electrode wiring area on the semiconductor substrate, a step of forming a conductor layer on the semiconductor substrate and the first protective film, and a step of forming a conductor layer on the conductor layer. After applying the second protective film, removing the second protective film other than the electrode wiring area and leaving the second protective film on the electrode wiring area wider than the electrode wiring area; etching the entire surface of the second protective film to remove the second protective film on the first protective film;
exposing the conductor layer and leaving the second protective film on the electrode wiring area in a self-aligned manner; a step of etching until the surface of the first protective film is exposed; and removing the first and second protective films to remove the conductor layer on the first protective film and selectively form the electrode wiring; A method for manufacturing a semiconductor device, comprising the steps of: