JPH05251383A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a sharply outlined pattern by building up polysilicon on a semiconductor substrate having an offset portion, forming silicide evenly thereon and patterning a polycide wiring. CONSTITUTION:Polysilicon 4 is clad across the - board on a semiconductor substrate 2 having an offset portion 1. A photoresist 9 is applied thereon where the surface of the resist 9 is flattened. Then, etch back is carried out so as to form one flattened plane 10 across the - board with the polysilicon 4 buried in a recess. After the etch back is over, silicide 5 is formed on the flattened surface 10 as a flat layer. After exposed and developed, a pattern portion 6a is adapted to remain and etched where it is used as a mask. This construction makes it possible to avoid the bleeding of light caused by halation produced by the reflection from the side walls and form a specified polycide wiring 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as a semiconductor integrated circuit including a circuit element having an insulated gate structure, such as a MOS-LSI, and various semiconductor devices.

[0002]

2. Description of the Related Art FIG. 5 is a plan view of a main portion thereof, and FIG. 6 is a cross-sectional view taken along the line AA of FIG. 5, for example, a semiconductor integrated circuit having a circuit element having an insulated gate structure, for example, In various semiconductor devices such as MOS-LSI, the conductive polysilicon 4 is used in the gate electrode of the insulated gate, the connection pattern for connecting circuit elements, and the like.
Further, in order to further reduce the electric resistance, a wiring structure is often formed by a polycide wiring 3 in which a metal silicide 5 such as silicide, for example, tungsten silicide, molybdenum silicide, titanium silicide is laminated.

Further, in an integrated circuit or the like, for example, a so-called field portion other than the so-called active region for forming the circuit element thereof, such as a passivation layer with a thick thermal oxide film or an insulating layer 7 for element isolation, so-called LOCOS.
In the case where the gap is formed, a step 1 is formed between the field portion and the active region.

As described above, when the above-mentioned polycide wiring 3 is formed on the semiconductor substrate 2 having the step 1 on the surface, the edge portion of the polycide wiring 3 is intended, for example, at the gate electrode. There is a problem that a so-called sharp pattern such as a straight line is not formed, and thinning or chipping occurs, so that a desired pattern cannot be obtained accurately.

The problem of such thinning and chipping of the pattern is, for example, that the width of the gate electrode by the polycide wiring, that is, the channel length L is reduced along with the shortening of the channel of the MOS circuit element in the MOS-LSI. It has a great influence on the characteristics.

The reduction in the pattern cut in the polycide wiring when the step 1 is present on the surface of the semiconductor substrate 2 is due to the application of photolithography in patterning the polycide wiring. That is, the light reflection due to the wall surface of the metal silicide layer of the upper layer such as tungsten silicide, molybdenum silicide, titanium silicide, etc., caused by the above-mentioned step difference is a portion to be avoided in the pattern exposure for the positive type photoresist as the etching mask. This is caused by causing unnecessary exposure and blurring the exposure pattern.

This will be described with reference to FIG.
In forming the polycide wiring, the polysilicon 4 and the silicide 5 are sequentially deposited on the entire surface of the semiconductor substrate 2 by CVD.
After being formed by a (chemical vapor deposition) method, sputtering, etc., a positive photoresist layer 6 on which a fine pattern is easily formed is applied thereon, and a pattern portion to be finally left as wiring for this. The portions other than 6a are exposed, and then developed, the exposed portions are removed, and the photoresist is patterned. Then, the silicide 5 and the polysilicon 4 are sequentially etched by using the patterned photoresist film 6 as a mask to pattern these to form the intended polycide wiring 3. In this case, If the step 1 exists on the surface of the semiconductor substrate 2 and the side wall surface 5a is formed on the silicide 5 having a high reflectance, the exposure light beam is reflected by the side wall surface 5a, which is originally
A so-called halation occurs in which the pattern portion 6a is exposed and the pattern portion 6a is also exposed. Therefore, when the photoresist film 6 is developed thereafter, a portion to be removed is generated at the edge portion of the pattern portion 6a, and thinning or chipping occurs. Therefore, when the silicide 5 and the polysilicon 4 are etched by using the pattern portion 6a as a mask, the wiring formed by this etching also becomes thin or chipped.

As described above, as a measure for solving the problem of halation on the photoresist layer due to the reflected light when using a metal silicide having a high reflectance in the polycide wiring, polysilicon or another material such as polysilicon is used on the silicide. A method of forming a photoresist film after forming an antireflection film and performing pattern exposure for the same is also adopted, but even in this case, the problem of the reflection is sufficiently avoided. Not not.

[0009]

DISCLOSURE OF THE INVENTION The present invention is a semiconductor device having a polycide wiring using the above-mentioned silicide having a high reflectance, and a semiconductor device having a step difference on the surface of the semiconductor substrate. By making it possible to pattern the polycide wiring, it is possible to surely obtain a semiconductor device having no variation in its characteristics and having the characteristics as designed.

[0010]

The present invention provides a method of manufacturing a semiconductor device in which a polycide wiring 3 is formed on the surface of a semiconductor substrate 2 having a step 1, as shown in FIG. 2C. As shown in the process diagram of one example of the manufacturing method,
A step of depositing the polysilicon 4 (FIG. 1A), a step of planarizing the polysilicon 4 (FIG. 1B), a step of depositing the silicide 5 on the semiconductor substrate 2 (FIG. 1C), and a step of depositing the silicide 5 on the silicide 5. A step of forming the photoresist film 6 (FIG. 2A), a step of selectively exposing and patterning the photoresist film 6 (FIG. 2B), and a step of etching the silicide 5 using the photoresist film 6 as a mask. (Fig. 2C).

Further, in the present invention, in the step of planarizing the polysilicon 4, after the planarizing film 9 is formed on the polysilicon 4 (FIG. 1A), the planarizing film 9 such as a photo film is formed. Take a step of etching back together with the resist film.

Further, according to the present invention, as shown in FIG. 3A, after the polysilicon 4 is flattened, a step of further depositing polysilicon 41 on the semiconductor substrate 2 before depositing the silicide 5 is taken. ..

[0013]

As described above, in the manufacturing method of the present invention,
As shown in FIG. 1C, since the adhered surface of the surface of the silicide 5 is flattened and the silicide 5 is flatly formed thereon, the pattern exposure of the photoresist film 6 formed thereon is performed. Since the reflection from the silicide 5 is effectively prevented from being scattered to the portion where pattern exposure is to be avoided, the photoresist film 6 after this exposure is subjected to a developing treatment and solubilized by this exposure. When the developed portion is removed by the developer or the solution and only the unexposed portion is left, the edge portion, that is, the boundary portion between the unexposed portion and the exposed portion is clearly formed. Therefore, the pattern portion 6a of the photoresist film 6 obtained by development is formed into a predetermined pattern that is well cut, that is, has no chipping or thinning.

Therefore, the silicide 5 etched using the photoresist film 6 as a mask and the polysilicon 4 thereunder also have a well-defined pattern without chipping or thinning, and the polycide wiring 3 having the desired pattern is formed. You can

Therefore, in the semiconductor device formed by this, for example, in an integrated circuit such as a MOS-LSI, it is possible to stably form an integrated circuit having desired characteristics.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the manufacturing method of the present invention will be described in detail with reference to FIGS.

In this example, the polycide wiring 3 is used to form the gate electrode of the MOS element and wiring such as internal wiring and bonding pads for leading the leads.

In this case, as shown in FIG. 1A, for example, an insulating layer 7 made of LOCOS, that is, a thick oxide film is formed in the field portion of the silicon semiconductor substrate 2, and a gate formed by thin thermal oxidation is formed in the active region surrounded by the LOCOS. The insulating film 8 is formed, and a step 1 is formed between the gate insulating film 8 and the insulating layer 7, that is, between the active region and the field portion.

In the present invention, the semiconductor substrate 2 having the step 1 is entirely covered by a well-known technique, for example, 20.
Polysilicon 4 is blanket deposited to a thickness of 0 nm by the CVD method or the like. In this case, since the surface of the polysilicon 4 has irregularities due to the presence of the step 1, a flattening film 9, for example, a photoresist 9 is applied on the surface of the polysilicon 4 and the surface of the resist 9 is covered. Flatten. Then, under the condition that the etching rate of the resist 9 and the polysilicon 4 is about 1: 1 from above the resist 9 whose surface is flattened, for example, RIE (reactive ion etching).
To perform planar etching, that is, etch back. In this case, the photoresist 9 is removed, and an etching back is performed to form the entire flat surface 10 with the polysilicon 4 embedded in the surface of the insulating layer 6 and in the recess surrounded by the insulating layer 6.

This RIE is, for example, CF ₄ or SF ₆
And other gases such as O ₂ are mixed in order to make the etching rate of the resist 9 and the polysilicon 4 1: 1.
E. Thereafter, as shown in FIG. 1C, a silicide 5, for example, a metal silicide such as tungsten silicide, molybdenum silicide, or titanium silicide is formed on the flat surface 10 by a known technique such as sputtering.

The silicide 5 thus formed is
Since the silicide 5 is formed on the flat surface 10, the silicide 5 is formed as a flat layer.

Then, as shown in FIG. 2A, the silicide 5 is formed.
A positive type photoresist film 6 is applied on top. The reason why the positive type photoresist film is used here is that the positive type photoresist film is generally capable of highly precise patterning as compared with the negative type photoresist film.

Then, as shown by an arrow in FIG. 2A, pattern exposure is performed through a photomask or the like except for the portion where the polycide wiring is to be finally formed. In this way, the pattern portion 6a of the photoresist film 6 which finally forms the polycide wiring is made an unexposed portion, and the other portion is exposed to be solubilized in the developing solution.

Thereafter, as shown in FIG. 2B, the photoresist film 6 is subjected to a developing treatment to remove the pattern portion 6a while leaving the other portion, and the pattern portion 6a is used as a mask to be covered with the pattern portion 6a. The silicide 5 and the polysilicon 4 in the non-existing portion are removed by etching.

Thereafter, as shown in FIG. 2C, the pattern portion 6a of the photoresist film 6 is removed. In this way, the polycide wiring 3, for example, the gate electrode, the internal wiring, and the bonding pad is formed by the laminated structure of the polysilicon 4 having the predetermined pattern and the silicide 5 formed thereon.

In the semiconductor device thus obtained, since the polysilicon 4 is surely left in the active region, that is, the portion having the thin gate insulating film 8, the metal such as tungsten or tungsten in the silicide 5 is surely left. Inconveniences such as molybdenum eroding the gate insulating film 8 and degrading the gate breakdown voltage are surely removed.

Further, in practice, the silicide 5 is directly SiO 2.
When the peeling film is applied to the insulating layer 7 made of _{2 and} there is a possibility that problems such as erosion may occur in the peeling film, it is desirable to interpose polysilicon between them.

In order to make polysilicon intervene between the insulating layer 7 and the silicide 5 in this way, for example, as shown in the process chart of FIG. 3, the steps of FIGS. 1A and 1B are performed. After forming the flat surface 10, the flat surface 10 is again formed with a thickness of, for example, 40 n as shown in FIG. 3A.
A polysilicon thin film 41 having a thickness of about m can be formed, and the polycide wiring 3 can be formed thereon as shown in FIG. 3B by taking steps shown in FIGS. 1C and 2A to 2C.

Alternatively, as shown in the process chart of FIG.
After applying the flattening film 9 with a photoresist as in FIG. 1A, in the formation of the flat surface 10 described in FIG. 1B, the depth of the surface of the insulating layer 6 is not exposed, that is, Etchback is performed to the position shown by the arrow in FIG. 4A, and 40 n is formed on the insulating layer 6 as shown in FIG. 4B.
With the thin polysilicon 4 of about m left,
Finally, similarly to the case shown in FIG. 3B, it is possible to form the polycide wiring 3 by interposing the polysilicon 4 on the insulating layer 7.

In the above example, the circuit element is M
This is a case where the present invention is applied to obtain a semiconductor integrated circuit device such as a MOS-LSI having an OS structure. In addition, the present invention is applied to a case where polycide wiring is formed on the semiconductor substrate 2 having steps on various surfaces. The invention can be applied.

[0031]

As described above, according to the present invention, in the photoresist film 6 used as an etching mask for forming the polycide wiring 3, a silicide having a high reflectance in exposing the photoresist film is used. 5,
By avoiding bleeding of light due to halation caused by reflection from the side wall surface 5a caused by the step 1, the gate electrode, that is, the polycide wiring 3 having a predetermined channel length is surely formed even in the formation of the short channel MOS element. Therefore, it is possible to reliably obtain the semiconductor device having the desired characteristics.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram (1) of an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a manufacturing process diagram (2) of the example of the method for manufacturing the semiconductor device according to the present invention.

FIG. 3 is a manufacturing process diagram of another example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a manufacturing process diagram of still another example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a schematic enlarged plan view of an example of a semiconductor device to which the present invention is applied.

6 is a cross-sectional view taken along the line AA of FIG.

FIG. 7 is an explanatory diagram of an exposure state for a photoresist.

[Explanation of symbols]

 1 step 2 semiconductor substrate 4 polysilicon 5 silicide 6 photoresist film 7 insulating layer

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device in which polycide wiring is formed on a surface of a semiconductor substrate having a step, a step of depositing polysilicon on the semiconductor substrate, and a step of planarizing the polysilicon. A step of depositing silicide on the semiconductor substrate; a step of forming a photoresist film on the silicide; a step of selectively exposing and patterning the photoresist film; and a step of forming the silicide using the photoresist film as a mask. And a step of etching the semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in planarizing the polysilicon, a planarizing film is formed on the polysilicon and then the planarizing film is etched back. Method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein after the polysilicon is planarized, the polysilicon is deposited on the semiconductor substrate before the silicide is deposited.