JPS59165426A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59165426A JPS59165426A JP3966383A JP3966383A JPS59165426A JP S59165426 A JPS59165426 A JP S59165426A JP 3966383 A JP3966383 A JP 3966383A JP 3966383 A JP3966383 A JP 3966383A JP S59165426 A JPS59165426 A JP S59165426A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- resist pattern
- hole
- insulating film
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 229910000859 α-Fe Inorganic materials 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 32
- 238000010586 diagram Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 241000219995 Wisteria Species 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 102000006533 chordin Human genes 0.000 description 1
- 108010008846 chordin Proteins 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかり、特にチップ実
装あるいは高密度配線のために多層配線構造を必要とす
るサーマルヘッド、長尺画像読み取り素子用基板、およ
びハイブリッド回路基板などの製造に際して、層間絶縁
膜にスルーホールを形成するための方法に関ｊ−る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and is particularly applicable to a thermal head, a long image reading element substrate, and a hybrid circuit board that require a multilayer wiring structure for chip mounting or high-density wiring. This invention relates to a method for forming through-holes in an interlayer insulating film during the production of an interlayer insulating film.
長尺基板上に形成される多層配線層は、基板そのものの
もつ表面粗さに加えて、基板面積が大でありかつ基板の
寸法に方向性かあるため、均一な層を形成するのは困難
である。特に、この配線層の中で、隣接する２つの配線
層を絶縁するための眉間絶縁−膜は、膜中のどンホール
などに起因する短絡を完全に防ぐため罠できるだけ膜厚
を厚くするのが望ましい。It is difficult to form a uniform layer for multilayer wiring layers formed on long substrates due to the surface roughness of the substrate itself, the large area of the substrate, and the directional nature of the dimensions of the substrate. It is. In particular, in this wiring layer, it is desirable to make the thickness of the insulating film between the eyebrows, which is used to insulate two adjacent wiring layers, as thick as possible in order to completely prevent short circuits caused by holes in the film. .
ところで、眉間絶縁膜には、隣接する２つの配線層を絶
縁すると共忙、所定の箇所で、前記配線層を電気的に接
続する為の導体の通路となるという２つの目的があり、
後者の目的の為に、スルーホールと称するコンタクト窓
が所定の箇所に設けられなければならない。By the way, the glabella insulating film has two purposes: to insulate two adjacent wiring layers, and to serve as a path for a conductor to electrically connect the wiring layers at a predetermined location.
For the latter purpose, contact windows, called through-holes, must be provided at predetermined locations.
従来、このスルーホールの形成は次のようにして行なわ
れていた。すなわち、第１図に示すように所定の配線パ
ターン２が形成された基板１上に、まず、基板表面全体
にわたって絶縁膜３を形成する。次に、レジスト塗布、
そして露光、現像工程を経て、スルーホールを形成ｊべ
き部分以外の基板表面を第２図に示すようにレジスト４
で被覆して、この絶縁膜をエツチングする。そして最後
にレジスト４を除去し、第３図に示すようにスルーホー
ル５が形成されるわけである。Conventionally, this through hole was formed as follows. That is, as shown in FIG. 1, on a substrate 1 on which a predetermined wiring pattern 2 is formed, an insulating film 3 is first formed over the entire surface of the substrate. Next, resist coating,
After exposure and development steps, the surface of the substrate other than the area where the through hole is to be formed is coated with resist 4 as shown in FIG.
This insulating film is then etched. Finally, the resist 4 is removed, and a through hole 5 is formed as shown in FIG.
ところで前述の如く、絶縁という目的の為に絶縁膜を厚
く形成するのが望ましいわけであるが、反面これはスル
ーホールすなわち、配線層間の接続を行なうために層間
を貫通すべく、絶縁膜中に形成されるコンタクト＝すな
わちスルーホールの穿設に、以下に示すような不都合を
生じる。By the way, as mentioned above, it is desirable to form a thick insulating film for the purpose of insulation, but on the other hand, it is desirable to form a thick insulating film for the purpose of insulation, but on the other hand, it is necessary to form through holes in the insulating film to penetrate between the layers in order to connect between wiring layers. The following inconveniences arise in forming contacts, that is, in drilling through holes.
まず、絶縁膜が厚くなればなるほど、スルーホール形成
のためのエツチング時間は長くなるため、レジストにキ
ズあるいはピンホール等があると、そこからレジスト下
の絶縁膜にエツチングが進行し、スルーホール以外の箇
所に下地の琴線層まで貫通する孔が形成されてしまうこ
とがある。さらには、エツチング時間が長いことに起因
して、サイドエッチが増大し、スルーホールの寸法精度
か安定性に欠けるため、コンタクト抵抗が一定しない。First of all, the thicker the insulating film, the longer the etching time to form through holes, so if there are scratches or pinholes in the resist, etching will progress to the insulating film under the resist, leaving holes other than through holes. Holes that penetrate to the underlying chordin layer may be formed at these locations. Furthermore, due to the long etching time, side etching increases, and the through holes lack dimensional accuracy or stability, resulting in inconsistent contact resistance.
加えて、エツチング時間が長いことに起因してエツチン
グ時間にばらつきが生じ、エツチング終了の検出か困難
である。エツチングの停止が早過ぎると、スルーホール
が貫通し得ないため、オーバーエツチング気味にしなけ
ればならず、従って微小寸法のスルーホールの形成は不
可能である。また、たとえば、絶縁膜として酸化シリコ
ン膜（Ｓｉ０２人下地金属（配線層）としてアルミニウ
ム膜（Ａｌ）を用いてなる８１０．−ｉ構造の多層配線
層の形成に際し、フッ酸（Ｉ（Ｆ ）系のエツチング液
を使用してこの絶縁膜のエツチングを行なった場合、エ
ツチングの終了検出が遅れてオーバーエツチングとなる
と、下地のアルミニウム層にまでエツチングが及んでし
まうという不都合が生じる。In addition, due to the long etching time, variations occur in the etching time, making it difficult to detect the end of etching. If the etching is stopped too early, the through-hole cannot penetrate, so the etching must be slightly over-etched, and it is therefore impossible to form a through-hole with minute dimensions. For example, when forming a multilayer wiring layer with an 810.-i structure using a silicon oxide film (Si02) as an insulating film and an aluminum film (Al) as a base metal (wiring layer), hydrofluoric acid (I(F))-based When this insulating film is etched using an etching solution of 100 mL, if over-etching occurs due to a delay in detecting the end of etching, the inconvenience arises that the underlying aluminum layer is etched.
さらには、厚い絶縁膜中にスルーホールが形成されるた
め、その上に形成される第２の配線層の段差が急峻とな
、す、断線が生じ易いという不都合があった。Furthermore, since the through hole is formed in the thick insulating film, the step of the second wiring layer formed thereon is steep, and wire breakage is likely to occur.
本発明はこれらの実情に鑑みてなされたもので、絶縁体
層へのスルーホールの形成を容易かつ確実釦行うことが
できるようにした半導体装置の製造方法を提供すること
な目的とする。The present invention has been made in view of these circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that allows through-holes to be formed in an insulating layer easily and reliably.
すなわち本発明は所定の領域の形成された基板上に絶縁
層を形成した後、該絶縁層にフォトエツチングを施すこ
とにより、不要部の絶縁層を除去して前記基板の露出部
を形成する工程を含む半導体装置の製造方法において、
前記絶縁層の形成に先立ち、前記藤出部形成部に所定の
厚さのレジスト層を形成することを特徴とする。That is, the present invention includes a step of forming an insulating layer on a substrate on which a predetermined region is formed, and then removing unnecessary portions of the insulating layer by photo-etching the insulating layer to form exposed portions of the substrate. In a method of manufacturing a semiconductor device including:
The method is characterized in that, prior to forming the insulating layer, a resist layer having a predetermined thickness is formed on the wisteria part forming portion.
以下、本発明を多層配線基板の製造方法に適用した一実
施例を図面を参照しつつ説明する。Hereinafter, an embodiment in which the present invention is applied to a method for manufacturing a multilayer wiring board will be described with reference to the drawings.
第４図に示す如く、所定の領域の形成されたフェライト
基板ｌ上に第１の配線層２を形成する。As shown in FIG. 4, a first wiring layer 2 is formed on a ferrite substrate l on which a predetermined region is formed.
次に、この基板上に耐熱性を有するネガ形のレジスト４
′を塗布し、スルーホールとなる部分だけにレジストを
残すべく形成されたフォトマスクを用いて露光、現像を
行ない、第５図に示すごとく第１のレジストパターンを
膜厚２μｍとなるように形成する。Next, a heat-resistant negative resist 4 is placed on this substrate.
' is applied, exposed and developed using a photomask formed to leave resist only in the areas that will become through holes, and a first resist pattern is formed with a film thickness of 2 μm as shown in Figure 5. do.
更にこのレジストの上から第６図に示すように、プラズ
マＣＶＤ法を用いて酸化シリコン膜３を膜厚４μｍの厚
さで形成する。Furthermore, as shown in FIG. 6, a silicon oxide film 3 having a thickness of 4 μm is formed on this resist using the plasma CVD method.
そして更に、この上にレジスト６を塗布し、前記レジス
ト３に対応するように、スルーホールエツチングのため
のレジストパターンを形成し、第１のレジストパターン
が露出するまでエツチングを行なう。このエツチング後
の状態を第７図に示す。Further, a resist 6 is applied thereon, a resist pattern for through-hole etching is formed so as to correspond to the resist 3, and etching is performed until the first resist pattern is exposed. The state after this etching is shown in FIG.
最後に所定のレジスト剥離液によってレジストを除去す
る。Finally, the resist is removed using a predetermined resist stripping solution.
このようにして形成されたスルーホールの断面形状は第
７図から明らかなｊうに階段状をなしており、段差か緩
やかである。従って、第８図に示すごとく、この上に第
２の配線層７を形成した場合、第２の配線層７はスルー
ホールに対し、膜の密着性が極めて良好となり、断線を
生じることもない。The cross-sectional shape of the through-hole thus formed has a step-like shape as seen in FIG. 7, and the steps are gradual. Therefore, as shown in FIG. 8, when the second wiring layer 7 is formed on this layer, the second wiring layer 7 has extremely good film adhesion to the through hole, and there is no possibility of disconnection. .
また、本発明の方法によれば、絶縁膜のエッチング時間
が短縮されるため、サイドエッチも減少し、寸法精度の
良好なスルーホールの形成が可能となる。すなわち、ス
ルーホールの開孔寸法（下地金属との接続面積）は第１
のレジストパターンによって決まるから、エツチングに
起因する寸法変化に比べ充分小さく、できる。従ってコ
ンタクト抵抗を一定とすることが可能である。さらには
、エツチング時間の短縮によりレジストのピンホールに
起因する絶縁不良の発生も大幅に低減される。Further, according to the method of the present invention, since the etching time for the insulating film is shortened, side etching is also reduced, and through holes with good dimensional accuracy can be formed. In other words, the opening size of the through hole (connection area with the underlying metal) is the first
This is determined by the resist pattern, so the dimensional change is sufficiently small compared to the dimensional change caused by etching. Therefore, it is possible to keep the contact resistance constant. Furthermore, by shortening the etching time, the occurrence of insulation defects caused by pinholes in the resist is also significantly reduced.
本発明実施例の方法においては、第１のレジストパター
ンはその上に形成される絶縁膜の約ｉの厚さとなるよ５
に形成されたが、膜厚は絶縁膜よりも薄いという条件の
もとで適宜選択可能である。In the method of the embodiment of the present invention, the first resist pattern has a thickness of approximately i of the insulating film formed thereon.
However, the film thickness can be selected as appropriate under the condition that it is thinner than the insulating film.
また、レジストについても、耐熱性の良いレジストであ
れば使用可能である。Further, as for the resist, any resist with good heat resistance can be used.
さらには、絶縁膜の形成については、レジストが熱的劣
化をおこさないような方法であればよく、実施例の他ス
パッタリング、グロー放電法などにより、酸化シリコン
膜を形成することも可能である。また、スピンナーを用
い【液状で塗布できる絶縁膜であるスビンオンガ２スの
使用も、平坦性の面で有利である。Furthermore, the insulating film may be formed by any method that does not cause thermal deterioration of the resist, and it is also possible to form a silicon oxide film by sputtering, glow discharge method, etc. in addition to the method described in the embodiment. Further, the use of Subin-on-Gas 2, which is an insulating film that can be applied in liquid form using a spinner, is also advantageous in terms of flatness.
加えて、第２のレジストパターンのスルーホールの孔径
ｌは、第１のレジストパターンのスルーホール孔径寸法
ｍに比べて太き（することが必要である。In addition, the diameter l of the through-hole in the second resist pattern needs to be larger than the diameter m of the through-hole in the first resist pattern.
ところでレジストパターンの形成は通常、フォトマスク
を介して紫外光８をレジスト膜に照射してマスクパター
ンを焼き付けることによってなされる。フォトマスクと
基板とをできるだけ密着させることによってパターニン
グ精度を上げることは可能であるが、マスク９と基板ｌ
の間には、少なくともレジストの厚さ分だけの間隙が残
りこの間隙に起因する紫外光の回折、散乱などにより、
マスク下への光の回り込みを避けることができない。従
って照射部分１０の断面は第９図にハツチングで示すご
とく逆台形状を呈することになる。By the way, a resist pattern is usually formed by irradiating the resist film with ultraviolet light 8 through a photomask and baking the mask pattern. Although it is possible to improve patterning accuracy by bringing the photomask and substrate into close contact as much as possible,
In between, a gap equal to at least the thickness of the resist remains, and due to the diffraction and scattering of ultraviolet light caused by this gap,
It is impossible to avoid light getting under the mask. Therefore, the cross section of the irradiated portion 10 has an inverted trapezoidal shape as shown by hatching in FIG.
ネガ形のレジストを使用した場合は、光照射部が残留部
となりレジストパターンを描くわけであるか、この場合
第１０図に示すとと（、レジストパターン１１の断面は
逆台形状となる。When a negative resist is used, the light irradiation part becomes a residual part and a resist pattern is drawn. In this case, as shown in FIG. 10, the cross section of the resist pattern 11 becomes an inverted trapezoid.
他方、ポジ形のレジストを使用した場合は、遮光部が残
留部となり、第１１図に示すとと（レジストパターン１
２の断面は台形状となる。On the other hand, when a positive resist is used, the light-shielding part becomes a residual part, as shown in Fig. 11 (resist pattern 1).
The cross section of No. 2 is trapezoidal.
本発明の第１の実施例の多層配線基板の製造方法におい
て第１のレジストパターンを形成するにあたり、前記ネ
ガ形のレジストを使用した場合は第１０図に示すごとく
逆台形状となるが、これをポジ形のレジストを用いて通
常の方法で露光、現像を行った場合、第１のレジストパ
ターンは第１１図に示すごとく台形状となる６従ってス
ルーホールの下方は断面が台形状を呈することになり、
この上に第２の配線層７′を形成する場合、この台形の
底角にあたる部分１３への配線層の形成がなされに（く
なり、断線が生じることがある。When forming the first resist pattern in the method for manufacturing a multilayer wiring board according to the first embodiment of the present invention, when the negative resist pattern is used, it becomes an inverted trapezoidal shape as shown in FIG. When exposed and developed using a positive resist in the usual manner, the first resist pattern becomes trapezoidal as shown in FIG. 116.Therefore, the section below the through hole exhibits a trapezoidal shape. become,
When the second wiring layer 7' is formed on this, the wiring layer is not formed on the portion 13 corresponding to the base corner of this trapezoid, and a disconnection may occur.
従ってポジ形のレジストを第１のレジストパターンに使
用する場合は、感度の異なるレジストを多層状に形成し
たり、電子ビームによる露光法を導入したりして、第１
のレジストパターンが第１０図の如く逆台形状となるよ
うに調整するのが望ましい。Therefore, when using a positive resist for the first resist pattern, it is necessary to form a multilayered resist with different sensitivities or to introduce an exposure method using an electron beam.
It is desirable to adjust the resist pattern so that it has an inverted trapezoidal shape as shown in FIG.
以上説明してきたように、本発明の方法によれば、絶縁
層に確実にかつ容易にスルーホールを形成し得ると共に
、これを層間絶縁膜を介して２つの配線層が対峙する多
層配線基板の製造方法罠適用すれば２つの配線層の絶縁
が確実となるとともに、両層のコンタクトを特徴とする
特定の領域に対してはコンタクト抵抗が一定の値となる
ような半導体装置を得ることができる。As explained above, according to the method of the present invention, it is possible to reliably and easily form a through hole in an insulating layer, and also to form a through hole in a multilayer wiring board in which two wiring layers face each other via an interlayer insulating film. By applying the manufacturing method trap, it is possible to obtain a semiconductor device in which insulation between two wiring layers is ensured, and the contact resistance is a constant value for a specific region characterized by contacts in both layers. .
第１図乃至第３図は、従来の方法に基づくスルーホール
の形成方法を示す工程の説明図、第４図乃至第８図は、
本発明の一実施例である多層配線基板の製造工程を示す
断面概要図、第９図はフォトマスクと被照射部の関係を
示す説明図、第１０図はネガ形のレジストを使用した場
合のレジストパターンの断面図、第１１図はポジ形のレ
ジストを使用した場合の同断面図、第１２図は、第１１
図に示された形状の第１のレジストノくターンを使用し
て形成されたスルーホールに第２の配線層を形成した場
合の状態説明図である。
１・・・基板、２−・・第１の配線層、３・・・層間絶
縁膜、４，４’・・・第１のレジストパターン、５・・
・スルーホール、６・・・第２のレジストパターン、７
．７′・・・第２の配線層、８・・・紫外光、９・・・
フォトマスク、１０−・・光照射部分、１１．１２・・
・レジストパターン、１３・・・部分。
第９図
第１Ｏ図
１
第１１図
２
第１２図1 to 3 are explanatory diagrams of steps showing a through-hole forming method based on a conventional method, and FIGS. 4 to 8 are
A cross-sectional schematic diagram showing the manufacturing process of a multilayer wiring board according to an embodiment of the present invention, FIG. 9 is an explanatory diagram showing the relationship between the photomask and the irradiated area, and FIG. A cross-sectional view of the resist pattern, FIG. 11 is the same cross-sectional view when a positive resist is used, and FIG. 12 is a cross-sectional view of the resist pattern.
FIG. 3 is an explanatory diagram of a state in which a second wiring layer is formed in a through hole formed using a first resist pattern having the shape shown in the figure. DESCRIPTION OF SYMBOLS 1... Substrate, 2-... First wiring layer, 3... Interlayer insulating film, 4, 4'... First resist pattern, 5...
-Through hole, 6...Second resist pattern, 7
．． 7'... Second wiring layer, 8... Ultraviolet light, 9...
Photomask, 10-...Light irradiation part, 11.12...
-Resist pattern, 13... portion. Figure 9 Figure 1O Figure 1 Figure 11 2 Figure 12
Claims (1)
該絶縁層にフォトエツチングを施すことにより、不要部
の絶縁層を除去して前記基板の露出部を形成する工程を
含む半導体装置の製造方法において、前記絶縁層の形成
に先立ち、前記露出部形成部に所定の厚さのレジスト層
を形成することを特徴とする半導体装置の製造方法。After forming an insulating layer on the formed substrate in a predetermined area,
A method for manufacturing a semiconductor device including a step of removing an unnecessary portion of the insulating layer to form an exposed portion of the substrate by photoetching the insulating layer, prior to forming the insulating layer, forming the exposed portion. 1. A method of manufacturing a semiconductor device, comprising forming a resist layer of a predetermined thickness on a portion of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3966383A JPS59165426A (en) | 1983-03-10 | 1983-03-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3966383A JPS59165426A (en) | 1983-03-10 | 1983-03-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59165426A true JPS59165426A (en) | 1984-09-18 |
Family
ID=12559319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3966383A Pending JPS59165426A (en) | 1983-03-10 | 1983-03-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59165426A (en) |
-
1983
- 1983-03-10 JP JP3966383A patent/JPS59165426A/en active Pending
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