JPH06188317A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate lowering of a step coverage and a disconnection or the like generation of and to achieve a high-reliability connection by a method wherein a first interlayer insulating film is formed, a residual resist film is removed, a conductive film is posited selectively on the lower-layer interconnection in one exposed part and a connection part to an upper-layer interconnection is formed so as to protrude. CONSTITUTION:A residual resist film which corresponds to the width of a through hole required to connect a lower-layer interconnection 3 to an upper- layer interconnection is left, and an interlayer insulating film 16 is deposited, by a photo-assisted CVD operation, on the whole surface including the residual resist film. Then, the residual resist film is stripped, one part of the lower-layer interconnection 3 is exposed, a conductive film 17 such as aluminum or the like is designated selectively in an exposed part, and a connection part to the upper-layer interconnection 7 is formed so as to protrude. Then, the film thickness of the interlayer insulating film 16 is increased on the interlayer insulating film 16 by a photo-assisted CVD operation, the film is etched back, one part of the conductive film 17 is exposed, and the upper-layer interconnection 7 is formed on it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art A conventional method for manufacturing a multi-layer wiring portion of a semiconductor device will be described. As shown in FIG. 13 (a), an insulating film 2 such as SiO ₂ is formed on a semiconductor substrate (hereinafter referred to as Si substrate) 1.
Then, the first layer (lower layer) wiring 3 is formed on the insulating film 2, the interlayer insulating film 4 is formed as shown in FIG. 13 (b), the resist film 5 is applied, and the through film is formed. After exposure and development using a hole mask, the interlayer insulating film 4 is etched as shown in FIG. 13 (c), and the lower wiring 3 and the second layer (upper layer)
A through hole opening portion 6 for connecting to the wiring portion is formed.
After that, an upper layer wiring is formed on the entire surface by a sputtering method or the like, and an upper layer wiring 7 is formed through an etching process as shown in FIG. 13 (d).

[0003]

However, in the above-described conventional method for manufacturing a multilayer wiring portion of a semiconductor device, there is a problem that a deviation occurs at the time of alignment between the lower layer wiring 3 and the through hole portion 6 and the interlayer insulation. Due to the thickening of the film 4 and the like, the step difference of the through-hole portion 6 expands, the step coverage of the upper layer wiring 7 deteriorates, and there is a drawback that the connection between the lower layer wiring 3 and the upper layer wiring 7 becomes difficult.

By the way, as means for eliminating the above-mentioned misalignment, for example, a resist film formed on a semiconductor substrate by using an exposure line mask in which an exposure line absorber is made convex or concave as disclosed in JP-A-2-103921. Is exposed to light and then developed to form the resist film in a pattern corresponding to a desired pattern, a conductive material film is formed on the resist film, and then the resist film is removed. Although proposed, in this case, there is a problem that it is necessary to accurately process the uneven portion on the exposure line mask.

As a means for improving the above-mentioned step coverage, for example, in Japanese Unexamined Patent Publication No. 4-29357, a lower layer wiring is formed on a substrate and then this lower layer wiring portion is formed into a convex shape so that it can be connected to the upper layer wiring. However, this conventional example is intended to reduce the step difference and improve the coverage on the premise of the existence of the through-hole opening portion. At best, you can expect only 50-60% coverage.

An object of the present invention is to provide a semiconductor manufacturing method and a pattern forming mask which solve the above problems of the prior art.

[0007]

The present invention provides a method for manufacturing a semiconductor device having a multilayer wiring structure, in which an upper wiring is formed on a lower wiring having an insulating film formed on a semiconductor substrate with an interlayer insulating film interposed therebetween. A step of forming a conductive film on the insulating film on the substrate, and an i-line resist film and g on the conductive film.
Line resist film, a step of irradiating i-line and g-line through a pattern forming mask to develop into a predetermined resist pattern, and etching the conductive film using the resist pattern as a mask to form a lower layer. A step of forming a wiring, a step of leaving a resist film corresponding to a width necessary for forming a connection portion with an upper wiring when removing the resist film, and a step of forming an interlayer insulating film on the entire surface including the remaining resist film And a step of removing the residual resist film to expose a part of the lower layer wiring, a step of selectively depositing a conductive film on the exposed lower layer wiring, and a whole surface after the conductive film is deposited. After forming an interlayer insulating film on it, etch back,
A method of manufacturing a semiconductor device, comprising: exposing a part of the conductive film; and forming an upper layer wiring connected to the conductive film on the interlayer insulating film.

In addition, after the step of removing the residual resist film, a step of depositing a conductive film on the exposed portion of the lower layer wiring and the interlayer insulating film and a step of etching the conductive film to form an upper layer wiring The process may be performed.

[0009]

[Operation] According to the present invention, an i-line resist film and a g-line resist film are applied on a conductive film formed on a semiconductor substrate via an insulating film, and an i-line resist is applied via a pattern forming mask. A width required for forming a through hole when the resist film is removed by irradiating the g-line and developing to a predetermined resist pattern, and etching the conductive film by using the resist pattern as a mask to form a lower wiring. The resist film corresponding to the above is left, the first interlayer insulating film is sequentially formed, and the remaining resist film is removed, and then the conductive film is selectively deposited on a part of the exposed lower layer wiring to form the upper layer wiring. The connecting portion with is formed to project.

The protrusion forming portion corresponds to a buried layer for filling the inside of the contact hole opened in the conventional interlayer insulating film formed on the lower layer wiring. Unlike the conventional method of filling a contact hole, the conductive film of the protruding formation portion is formed by selectively depositing it on the lower layer wiring, so that the film thickness can be arbitrarily determined. Therefore, even if the aspect ratio becomes high, there will be no deterioration of step coverage or disconnection,
You can make a reliable connection. Moreover, since the film thickness of the interlayer insulating film can be increased according to the film thickness of the conductive film of the protrusion forming portion, the inter-wiring capacitance can be reduced.

Further, since the conductive film of the protrusion forming portion can be formed in a self-aligned manner without performing a photo process for forming itself, there is no mechanical alignment (alignment) deviation and high precision. Can be formed.
Then, after that, an interlayer insulating film is formed on the entire surface and is etched back to expose the conductive film of the protruding formation portion, and then the upper layer wiring contacting the exposed conductive film on the interlayer insulating film. By forming the above, it is possible to obtain an upper layer wiring that is connected to the lower layer wiring via the conductive film of the protrusion forming portion.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1A and 1B are views showing an embodiment of a pattern forming mask used in the present invention, in which FIG. 1A is a sectional view, FIG. 1B is a sectional view taken along line XX, and FIG. FIG. As shown in these figures, the pattern forming mask 10 of the present invention is configured so that the first filter material 11 disposed in the area A and not passing the i-line and the g-line and the area A of the first filter material 11 are provided. The second filter material 12 that cuts the i-line and passes only the g-line in the region B of the lower wiring pattern except
And the area A of the first filter material 11 and the second filter material 12
And a third filter material 13 that allows the i-line and the g-line to pass through the area C except the area B.

FIG. 2 shows a connection wiring pattern forming method according to the present invention using the pattern forming mask 10 described above.
The outline of the process will be described below with reference to FIGS. First, as shown in FIG. 2, a conductive film 3a such as an aluminum pattern corresponding to the lower layer wiring 3 is formed on the insulating film 2 on the Si substrate 1 to a predetermined thickness of about 0.5 μm, and then the i-line resist is formed. A film 14 is applied, and a g-line resist film 15 is further applied thereon.
Apply.

Next, as shown in FIG. 3, the pattern forming mask 10 is used to irradiate i-line and g-line from a xenon-mercury lamp light source (not shown), and the i-line resist films 14 and g are irradiated. The line resist film 15 is exposed and developed.
Then, as shown in FIGS. 4 (a) and 4 (b), neither the i-line nor the g-line is allowed to pass in the region A of the pattern forming mask 10 corresponding to the first filter material 11 such as Cr. Therefore, the i-line resist film 14 and the g-line resist film 15 retain their state without being developed.
In the region B of the filter material 12, the g-line resist film 15 is developed, and the i-line and the g-line are passed in the region C of the third filter material 13 such as quartz. Both the line resist film 14 and the g-line resist film 15 are developed. Therefore, the exposed conductive film 3a is etched to form the lower wiring 3 as shown in FIGS. 5 (a) and 5 (b).
To form.

Further, by peeling off the i-line resist film 14 and the g-line resist film 15 and stopping the peeling on the way, as shown in FIG. 6, it is necessary for connection with the upper layer wiring of the lower layer wiring 3. The residual resist film 14a corresponding to the width of the through hole is left. Then, as shown in FIG. 7, an interlayer insulating film 16 is deposited by photo CVD on the entire surface including the residual resist film 14a.

Then, the residual resist film 14a is peeled off to expose a part of the lower layer wiring 3, and then a conductive film 17 such as aluminum is selectively deposited on the exposed part as shown in FIG. A connection portion with the upper layer wiring 7 is formed so as to project. Then, as shown in FIG. 9, after further increasing the film thickness of the interlayer insulating film 16 on the entire surface by photo-CVD on the interlayer insulating film 16 and etching back to expose a part of the conductive film 17, An upper layer wiring 7 is formed thereon as shown in FIG.

In the above embodiment, when the interlayer insulating film 16 may be thin, the residual resist film 14a shown in FIG.
After the step of depositing the interlayer insulating film 16 on the entire surface including the above, the remaining resist portion 14a is peeled off, and the following two steps are performed, whereby the step can be shortened. That is, as shown in FIG. 11, after the conductive film 7a is deposited to a predetermined thickness on the lower wiring 3 and the interlayer insulating film 16 exposed by the peeling of the residual resist film 14a, the conductive film 7a is etched. Thus, the upper wiring 7 is formed as shown in FIG.

The conductive films 3a and 7 used here are used.
Besides aluminium, a conductive material such as an aluminum alloy, a refractory metal, or a silicide is suitable as the material for a and 17. Further, in the above-mentioned embodiment, the i-line resist film 14 and the g-line resist film 15 are sequentially coated on the conductive film 3a, but the present invention is not limited to this, and the order may be reversed. The i-line resist film 14 may be applied after the line resist film 15 is applied first. At this time, the second filter material 12 of the pattern forming mask 10 used needs to be configured to pass only the i-line and cut the g-line.

Further, the irradiation of the i-line and the g-line in the above-mentioned embodiment may be carried out simultaneously or alternately, or may be simply X-ray irradiation.

[0020]

As described above, according to the present invention,
I is formed on a conductive film formed on a semiconductor substrate via an insulating film.
Line resist film and g-line resist film are applied, i-line and g-line are irradiated through a pattern forming mask, and a predetermined resist pattern is developed, and the conductive film is etched using this resist pattern as a mask. Then, after forming the lower layer wiring, the resist film corresponding to the width required for forming the through hole is left when the resist film is removed,
After first forming the interlayer insulating film and removing the residual resist film, the conductive film is selectively deposited on the exposed part of the lower layer wiring to form the protruding connection part with the upper layer wiring. Therefore, even if the aspect ratio becomes high, step coverage and disconnection do not occur, making it possible to perform highly reliable connections, reduce the capacitance between wires, and achieve highly accurate alignment. It has an excellent effect.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a mask for pattern formation used in the present invention, (b) a sectional view taken along the line XX, (c).
It is a YY arrow plane view.

FIG. 2 is a partial cross-sectional view showing a part of a connection wiring pattern forming step according to an embodiment of the present invention.

FIG. 3 is a partial cross-sectional view showing a part of a connection wiring pattern forming step according to an embodiment of the present invention.

FIG. 4A is a partial sectional view and FIG. 4B is a partial plan view showing a part of a connection wiring pattern forming step according to an embodiment of the present invention.

FIG. 5A is a partial cross-sectional view and FIG. 5B is a partial plan view showing a part of a connection wiring pattern forming step according to an embodiment of the present invention.

FIG. 6 is a partial cross-sectional view showing a part of the connection wiring pattern forming step according to the embodiment of the present invention.

FIG. 7 is a partial cross-sectional view showing a part of the connection wiring pattern forming step according to the embodiment of the present invention.

FIG. 8 is a partial cross-sectional view showing a part of the connection wiring pattern forming step according to the embodiment of the present invention.

FIG. 9 is a partial cross-sectional view showing a part of the connection wiring pattern forming step according to the embodiment of the present invention.

FIG. 10 is a partial cross-sectional view showing a part of the connection wiring pattern forming step according to the embodiment of the present invention.

FIG. 11 is a partial cross-sectional view showing a part of the connection wiring pattern forming step according to the embodiment of the present invention.

FIG. 12 is a process drawing partially showing another embodiment of the present invention.

FIG. 13 is a process chart showing a method of manufacturing a conventional multilayer wiring portion of a semiconductor device.

[Explanation of symbols]

 1 Si substrate (semiconductor substrate) 2 Insulating film 3 Lower layer wiring 3a Conductive film 4 Interlayer insulating film 7 Upper layer wiring 7a Conductive film 10 Pattern forming mask 11 First filter material 12 Second filter material 13 Third filter material 14 i-line resist film 14a Residual resist film 15 g-line resist film 16 Interlayer insulating film 17 Conductive film

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device having a multi-layer wiring structure in which an upper wiring is formed on a lower wiring having an insulating film formed on a semiconductor substrate via an interlayer insulating film, wherein a conductive film is formed on the insulating film on the semiconductor substrate. Of a conductive film, applying an i-line resist film and a g-line resist film on the conductive film, and irradiating i-line and g-line through a pattern forming mask to form a predetermined resist pattern. A step of developing, a step of etching the conductive film using the resist pattern as a mask to form a lower layer wiring, and a step of forming a resist film corresponding to a width necessary for forming a connection portion with an upper layer wiring when removing the resist film. A step of leaving it, a step of forming an interlayer insulating film on the entire surface including the residual resist film, a step of removing the residual resist film to expose a part of the lower layer wiring, and the exposed lower layer A step of selectively depositing a conductive film on the wiring; a step of forming an interlayer insulating film over the entire surface after the conductive film is deposited and then etching back to expose a part of the conductive film; And a step of forming an upper layer wiring connected to the conductive film on the interlayer insulating film. 2. A step after the step of removing the residual resist film, a step of depositing a conductive film on the exposed portion of the lower layer wiring and the interlayer insulating film, and an etching of the conductive film to form an upper layer wiring. The method for manufacturing a semiconductor device according to claim 1, wherein the step is a step of performing.