JPH06188319A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To omit a process in which a through hole is formed, to eliminate the misalignment of a lower-layer interconnection with a through-hole part and to obtain a multilayer interconnection whose step coverage is good by a method wherein a conductive film to be used as the lower-layer interconnection is etched and a connection part of the lower-layer interconnection with an upper-layer interconnection is formed. CONSTITUTION:A conductive film 13a which has been formed on a semiconductor substrate 1 via an insulating film 2 is coated with an i-line resist film 14 and a g-line resist film 15, the resist films are irradiated with an i-line and a g-line via a mask 10 for pattern formation, the conductive film 3a is etched by making use of a prescribed resist pattern as a mask, a lower-layer interconnection 3 is formed, and the resist films are then removed. At this time, the resist films corresponding to a width required to form a connection part 3b to an upper-layer interconnection 7 are left, the lower-layer interconnection 3 is etched, the connection part 3b is formed, an interlayer insulating film 4 is deposited, and the upper-layer interconnection 7 is formed on the film 4. Consequently, since a process to form a through hole is not required, no misalignment is caused.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure.

[0002]

When BACKGROUND ART method for manufacturing a multilayer wiring portion of a conventional semiconductor device will be described, as shown in FIG. 10 (a), the semiconductor substrate (or less, Si as substrate) 1 an insulating film 2 of SiO ₂ or the like formed Then, the first layer (lower layer) wiring 3 is formed on the insulating film 2.
Is formed, an interlayer insulating film 4 is formed as shown in FIG. 10 (b), a resist film 5 is applied, and exposure / development is performed using a through-hole mask. Then, as shown in FIG. 10 (c). The interlayer insulating film 3 is etched in such a manner that the lower layer wiring 3 and the second layer (upper layer)
A through hole opening portion 6 for connecting to the wiring portion is formed.
After that, an upper wiring layer is formed on the entire surface by a sputtering method or the like, and an upper wiring 7 is formed through an etching process as shown in FIG. 10 (d).

[0003]

However, in the above-described conventional method for manufacturing a multilayer wiring portion of a semiconductor device, there is a problem that a deviation occurs at the time of alignment between the lower layer wiring 3 and the through hole portion 6 and the interlayer insulation. Due to the thickening of the film 4 and the like, the step difference of the through-hole portion 6 expands, the step coverage of the upper layer wiring 7 deteriorates, and there is a drawback that the connection between the lower layer wiring 3 and the upper layer wiring 7 becomes difficult.

By the way, as means for eliminating the above-mentioned misalignment, for example, a resist film formed on a semiconductor substrate by using an exposure line mask in which an exposure line absorber is made convex or concave as disclosed in JP-A-2-103921. Is exposed to light and then developed to form the resist film in a pattern corresponding to a desired pattern, a conductive material film is formed on the resist film, and then the resist film is removed. Although proposed, in this case, there is a problem that it is necessary to accurately process the uneven portion on the exposure line mask.

As a means for improving the above-mentioned step coverage, for example, in Japanese Unexamined Patent Publication No. 4-29357, a lower layer wiring is formed on a substrate and then this lower layer wiring portion is formed into a convex shape so that it can be connected to the upper layer wiring. However, this conventional example is intended to reduce the step difference and improve the coverage on the premise of the existence of the through-hole opening portion. At best, you can expect only 50-60% coverage.

It is an object of the present invention to provide a semiconductor manufacturing method that solves the above-mentioned problems of the prior art.

[0007]

The present invention provides a method for manufacturing a semiconductor device having a multi-layer wiring structure, in which an upper wiring is formed on a lower wiring formed on a semiconductor substrate via an insulating film and an interlayer insulating film is formed on the lower wiring. A step of forming a conductive film on the insulating film on the semiconductor substrate, a step of applying an i-line resist film and a g-line resist film on the conductive film, and an i-line via a pattern forming mask. a step of irradiating with a g-line to develop into a predetermined resist pattern, a step of etching the conductive film using the resist pattern as a mask to form a lower layer wiring, and a connection part with an upper layer wiring when removing the resist film A step of leaving a resist film corresponding to the width required for formation, a step of etching the lower layer wiring by using the residual resist film as a mask to form a connection part, and a step of removing the residual resist film. Forming an interlayer insulating film after a manufacturing method of a semiconductor device, comprising forming an upper wiring connected to the lower wiring on the interlayer insulating film.

[0008]

[Operation] According to the present invention, an i-line resist film and a g-line resist film are applied on a conductive film formed on a semiconductor substrate via an insulating film, and an i-line resist is applied via a pattern forming mask. Irradiated with g-line and developed to a predetermined resist pattern, and the conductive film is etched using the resist pattern as a mask to form a lower layer wiring, which is necessary to form a connection portion with an upper layer wiring when the resist film is removed. A resist film corresponding to a certain width is left, the lower layer wiring is etched to form a connection portion, an interlayer insulating film is deposited, and then an upper layer wiring to be connected to the lower layer wiring is formed on the interlayer insulating film. Thus, since the step of forming the through hole is not required, the misalignment does not occur, and the wiring connection with the step coverage of 100% can be realized.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1A and 1B are views showing an embodiment of a pattern forming mask used in the present invention, in which FIG. 1A is a sectional view, FIG. 1B is a sectional view taken along line XX, and FIG. FIG. As shown in the figure, the pattern forming mask 10 of the present invention includes a first filter material 11 arranged in a region A that does not allow passage of both the i-line and the g-line, and the first filter material 11.
A second filter material 12 that cuts the i line and allows only the g line to pass through in the region B of the lower layer wiring pattern except the region A of 11;
A region A of the first filter material 11 and a region C of the second filter material 12 excluding the region B are composed of a third filter material 13 that passes both the i-line and the g-line.

FIG. 2 shows a connection wiring pattern forming method according to the present invention using the pattern forming mask 10 described above.
The outline of the process will be described below with reference to FIGS. First, as shown in FIG. 2, a conductive film 3a such as an aluminum pattern corresponding to the lower layer wiring 3 formed on the Si substrate 1 via the insulating film 2 is formed to a predetermined thickness of about 2 μm, and then the i-line is formed. A resist film 14 is applied, and a g-line resist film 15 is further applied thereon. Here, as the conductive film 3a, in addition to the aluminum pattern, a conductive material such as an aluminum alloy, a refractory metal, or silicide is suitable.

Next, as shown in FIG. 3, the pattern forming mask 10 is used to irradiate i-line and g-line from, for example, a xenon-mercury lamp light source (not shown) to obtain i-line resist films 14 and g. The line resist film 15 is exposed and developed.
Then, as shown in FIGS. 4 (a) and 4 (b), neither the i-line nor the g-line is allowed to pass in the region A of the pattern forming mask 10 corresponding to the first filter material 11 such as Cr. Therefore, the i-line resist film 14 and the g-line resist film 15 retain their state without being developed.
In the region B of the filter material 12, the g-line resist film 15 is developed, and the i-line and the g-line are passed in the region C of the third filter material 13 such as quartz. Both the line resist film 14 and the g-line resist film 15 are developed. Therefore, the exposed conductive film 3a is etched to form the lower wiring 3 as shown in FIGS. 5 (a) and 5 (b).
To form.

Next, by peeling off the i-line resist film 14 and the g-line resist film 15 and stopping the peeling on the way, as shown in FIG. 6, it is necessary for connection with the upper layer wiring of the lower layer wiring 3. Remaining resist portion 14a corresponding to the width
Leave. Further, using the remaining resist portion 14a as a mask, the lower layer wiring 3 is additionally etched to form a connecting portion 3b as shown in FIG. After that, as shown in FIG. 8, the residual resist portion 14a is peeled off, and then an interlayer insulating film 4 such as P-SiO ₂ is deposited. Then, on the interlayer insulating film 4, as shown in FIG. Form 7.

In the above embodiment, the conductive film 3a is used.
Although it has been described that the i-line resist film 14 and the g-line resist film 15 are sequentially applied on the above, the present invention is not limited to this, and the order is reversed and the g-line resist film 15 is first applied. The i-line resist film 14 may be applied. The second filter material 12 of the pattern forming mask 10 used at this time needs to be configured to pass only the i line and cut the g line.

Irradiation of i-line and g-line in the above embodiment may be performed simultaneously or alternately, or may be simply X-ray irradiation.

[0015]

As described above, according to the present invention,
By etching the conductive film used for the lower layer wiring to form the connection between the lower layer wiring and the upper layer wiring, the step of forming the through hole opening can be omitted and the lower layer wiring and the through wiring can be omitted. It is possible to eliminate misalignment with the hole and to realize a multi-layered wiring with good step coverage, which greatly contributes to improvement of reliability of the multi-layered wiring.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a mask for pattern formation used in the present invention, (b) a sectional view taken along the line XX, (c).
It is a YY arrow plane view.

FIG. 2 is a partial cross-sectional view showing a part of a connection wiring pattern forming step according to an embodiment of the present invention.

FIG. 3 is a partial cross-sectional view showing a part of a connection wiring pattern forming step according to an embodiment of the present invention.

FIG. 4A is a partial sectional view and FIG. 4B is a partial plan view showing a part of a connection wiring pattern forming step according to an embodiment of the present invention.

FIG. 5A is a partial cross-sectional view and FIG. 5B is a partial plan view showing a part of a connection wiring pattern forming step according to an embodiment of the present invention.

FIG. 6 is a partial cross-sectional view showing a part of the connection wiring pattern forming step according to the embodiment of the present invention.

FIG. 7 is a partial cross-sectional view showing a part of the connection wiring pattern forming step according to the embodiment of the present invention.

FIG. 8 is a partial cross-sectional view showing a part of the connection wiring pattern forming step according to the embodiment of the present invention.

FIG. 9 is a partial cross-sectional view showing a part of the connection wiring pattern forming step according to the embodiment of the present invention.

FIG. 10 is a process chart showing a method of manufacturing a conventional multilayer wiring portion of a semiconductor device.

[Explanation of symbols]

 1 Si substrate (semiconductor substrate) 2 Insulating film 3 Lower layer wiring 3a Conductive film 3b Connection part 4 Interlayer insulating film 7 Upper layer wiring 10 Mask for pattern formation 11 First filter material 12 Second filter material 13 Third filter material 14 i-line resist film 14a Remaining resist part 15 g-line resist film

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device having a multilayer wiring structure, wherein an upper wiring is formed on a lower wiring formed on a semiconductor substrate via an insulating film, and an upper wiring is formed on the lower wiring. A step of forming a conductive film on the top,
A step of applying an i-line resist film and a g-line resist film on the conductive film, a step of irradiating an i-line and a g-line through a pattern forming mask to develop into a predetermined resist pattern, and the resist pattern A step of etching the conductive film using the as a mask to form a lower layer wiring, a step of leaving a resist film corresponding to a width necessary for forming a connection portion with the upper layer wiring when removing the resist film, and the remaining resist A step of etching the lower layer wiring by using the film as a mask to form a connection portion; a step of removing the residual resist film and then forming an interlayer insulating film; and connecting the lower layer wiring on the interlayer insulating film. And a step of forming an upper layer wiring, the method for manufacturing a semiconductor device.