KR100351445B1 - Method For Forming The Contact Hole Using The Organic Material - Google Patents
Method For Forming The Contact Hole Using The Organic Material Download PDFInfo
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- KR100351445B1 KR100351445B1 KR1019990059519A KR19990059519A KR100351445B1 KR 100351445 B1 KR100351445 B1 KR 100351445B1 KR 1019990059519 A KR1019990059519 A KR 1019990059519A KR 19990059519 A KR19990059519 A KR 19990059519A KR 100351445 B1 KR100351445 B1 KR 100351445B1
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- insulating layer
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- interlayer insulating
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000011368 organic material Substances 0.000 title claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 30
- 239000010410 layer Substances 0.000 claims description 77
- 239000011229 interlayer Substances 0.000 claims description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000010030 laminating Methods 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000006866 deterioration Effects 0.000 abstract description 4
- 230000002950 deficient Effects 0.000 abstract description 3
- 238000004140 cleaning Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
본 발명은, 유기물질을 이용한 콘택홀 형성방법에 관한 것으로서, 특히, 상,하부금속배선층을 연결시키는 금속플러그를 콘택홀 내부에 매립하여 형성할 때, 콘택홀의 불량식각을 방지하기 위하여 절연층을 두 번에 걸쳐서 적층하여 콘택홀을 이중에 걸쳐서 식각 형성하므로 콘택홀의 식각불량으로 인한 소자의 전기적인 특성 저하를 방지하도록 하는 매우 유용하고 효과적인 발명에 관한 것이다.The present invention relates to a method for forming a contact hole using an organic material. In particular, when forming a metal plug connecting the upper and lower metal wiring layers inside a contact hole, an insulating layer is formed to prevent defective etching of the contact hole. The present invention relates to a very useful and effective invention that prevents deterioration of electrical characteristics of a device due to poor etching of a contact hole since the contact hole is etched through a double layer by stacking two times.
Description
본 발명은 금속배선라인을 형성하는 방법에 관한 것으로서, 특히, 상,하부금속배선층을 연결시키는 금속플러그를 콘택홀 내부에 매립하여 형성할 때, 콘택홀의 불량식각을 방지하기 위하여 절연층을 두 번에 걸쳐서 적층하여 콘택홀을 이중에 걸쳐서 식각 형성하므로 콘택홀의 식각불량으로 인한 소자의 전기적인 특성 저하를 방지하도록 하는 유기물질을 이용한 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for forming a metal wiring line, in particular, when forming a metal plug to connect the upper and lower metal wiring layer in the contact hole, the insulating layer twice to prevent the poor etching of the contact hole. The present invention relates to a method of forming a contact hole using an organic material, which is formed by stacking over and etching a contact hole over a double layer, thereby preventing deterioration of electrical characteristics of the device due to poor etching of the contact hole.
일반적으로, 금속배선라인 상에 콘택홀을 형성할 때, 화학기계적연마법(CMP; Chemical Mechanical Polishing)을 사용하여 층간절연막을 평탄화시키지만 3000Å이하에서 굴곡이 발생하여 비균일상태(Non-Uniformity)가 이루어지므로 콘택홀을 형성할 때, 한 웨이퍼당 두께가 8500 ∼ 11,500Å이다. 여기서, 11500Å의 두께를 기준으로 식각을 진행할 때는 8500Å이하의 깊이는 과도식각으로 인한 메탈성분이 포함된 폴리머(Polymer)의 증가를 유발한다.In general, when the contact hole is formed on the metal wiring line, the interlayer insulating film is planarized using chemical mechanical polishing (CMP), but the bending occurs below 3000 GPa, resulting in non-uniformity. Since the contact holes are formed, the thickness of each wafer is 8500 to 11,500 kPa. Here, when the etching is performed based on the thickness of 11500Å, the depth below 8500Å causes an increase in the polymer (Polymer) containing the metal component due to the excessive etching.
이와 같이, 세정공정시, 불완전한 제거가 되면, 비아 콘택홀의 막힘현상을 유발하거나 비아저항의 증가를 유발하는 요인으로 작용하였다.As such, incomplete cleaning during the cleaning process may cause clogging of the via contact holes or cause an increase in via resistance.
따라서, 웨이퍼의 두께가 11500Å이상의 경우에는 부족한 식각부분이 발생하여 소자의 특성 및 수율이 0%가 된다.Therefore, when the thickness of the wafer is 11500 GPa or more, insufficient etching occurs, resulting in 0% of device characteristics and yield.
이 경우는 산화막(Oxide)에 대한 아크 티타늄나이트라이드막(ARC TiN)의 식각비가 10 : 1 이상일 경우에는 TiN막이 300Å만 식각되므로 문제가 발생하지 않지만 그 이상의 경우에는 과도식각 외에 비아 콘택홀을 형성함에 따른 다른 변수와 복합적으로 작용하여 콘택홀의 막힘 현상으로 연결되어지고, 결국에는 소자의 전기적인 불량을 유발하는 문제점을 지닌다.In this case, if the etch ratio of the arc titanium nitride film (ARC TiN) to the oxide is 10: 1 or more, only 300 Ti is etched, which does not cause a problem. However, in this case, a via contact hole is formed in addition to the transient etching. In combination with other variables, the contact hole is connected to the blockage of the contact hole, eventually causing a problem of electrical failure of the device.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 상,하부금속배선층을 연결시키는 금속플러그를 콘택홀 내부에 매립하여 형성할 때, 콘택홀의 불량식각을 방지하기 위하여 절연층을 두 번에 걸쳐서 적층하여 콘택홀을 이중에 걸쳐서 식각 형성하므로 콘택홀의 식각불량으로 인한 소자의 전기적인 특성 저하를 방지하는 것이 목적이다.The present invention has been made in view of this point, and when forming a metal plug connecting the upper and lower metal wiring layer in the contact hole, the insulating layer is laminated twice in order to prevent defective etching of the contact hole. Since the contact holes are etched through the double layer, an object of the present invention is to prevent deterioration of electrical characteristics of the device due to poor etching of the contact holes.
도 1(a) 내지 도 1(h)는 본 발명의 일실시예에 따른 유기물질을 이용한 콘택홀 형성방법을 순차적으로 보인 도면이고,1 (a) to 1 (h) is a view sequentially showing a method for forming a contact hole using an organic material according to an embodiment of the present invention,
도 2(a) 내지 도 2(g)은 본 발명의 다른 실시예에 따른 유기물질을 이용한 콘택홀 형성방법을 순차적으로 보인 도면이다.2 (a) to 2 (g) are views sequentially showing a method for forming a contact hole using an organic material according to another embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10,110 : 반도체기판 15,115 : 제1층간절연층10,110 semiconductor substrate 15,115 first interlayer insulating layer
20,120 : 하부금속라인 25,125 : 제2층간절연층20,120: Lower metal line 25,125: Second interlayer insulating layer
30,130 : 제1감광막 35,135 : 콘택패턴30,130: first photosensitive film 35,135: contact pattern
40,140 : 콘택홀 50 : 유기계절연층40,140: contact hole 50: organic insulating layer
55,155 : 제3절연층 60 : 제2감광막55,155: third insulating layer 60: second photosensitive film
70 : 콘택홀 75,175 : 상부금속라인70: contact hole 75,175: upper metal line
150 : 금속층 153 : 금속플러그150: metal layer 153: metal plug
이러한 목적은 반도체기판 상에 적층된 제1층간절연층에 하부금속라인을 형성한 후, 제2층간절연층을 적층하는 단계와; 상기 제2층간절연층 상에 제1감광막을 적층하여 콘택패턴을 형성한 후, 식각으로 하부금속라인에 연결되는 제1콘택홀을 형성하는 단계와; 상기 콘택홀내에 유기계 절연층을 매립한 후, 식각으로 제1콘택홀 내에 만 절연층을 잔류시키는 단계와; 상기 결과물 상에 제3절연층을 적층한 후, 제3층간절연막을 식각하여 상기 제1콘택홀에 매립된 절연층으로 연결되는 제2콘택홀을 형성하는 단계와; 상기 제1콘택홀 내에 잔류된 절연층을 제거한 후, 제1,제2콘택홀내에 상부금속라인을 적층하는 단계를 포함하여 이루어진 유기물질을 이용한 콘택홀 형성방법의 일실시예를 제공함으로써 달성된다.This object is achieved by forming a lower metal line on the first interlayer insulating layer stacked on the semiconductor substrate, and then laminating a second interlayer insulating layer; Forming a contact pattern by stacking a first photoresist layer on the second interlayer insulating layer, and forming a first contact hole connected to the lower metal line by etching; Filling the organic insulating layer in the contact hole, and leaving the insulating layer only in the first contact hole by etching; Stacking a third insulating layer on the resultant, and etching a third interlayer insulating layer to form a second contact hole connected to an insulating layer embedded in the first contact hole; It is achieved by providing an embodiment of a method for forming a contact hole using an organic material comprising removing the insulating layer remaining in the first contact hole, and then laminating an upper metal line in the first and second contact holes. .
그리고, 상기 제2층간절연층은, 화학기계적연마공정으로 평탄화하여 2500 ∼ 3500Å정도로 잔류하는 것이 바람직 하다.The second interlayer insulating layer is preferably flattened by a chemical mechanical polishing process and left at about 2500 to 3500 kPa.
그리고, 상기 유기계절연층은, 플라즈마(Plasma)공정을 이용하여 60 ∼80mT, 1000 ∼ 1200Watt, 90 ∼ 110sccm N2, 200 ∼ 400sccm H2의 조건으로 식각하도록 한다.The organic insulating layer is etched under conditions of 60 to 80 mT, 1000 to 1200 Watts, 90 to 110 sccm N 2 , and 200 to 400 sccm H 2 using a plasma process.
상기 유기계절연층은, 마이크로웨이브(Micro-Wave)를 이용한 감광막 제거장치를 이용하여, 1000 ∼ 1200Watt, 1400 ∼ 1600mTorr, 1500 ∼ 2000sccm H2N2, 500 ∼ 1000sccm O2의 조건으로 식각하도록 한다.The organic insulating layer may be etched under conditions of 1000 to 1200 Watts, 1400 to 1600 mTorr, 1500 to 2000 sccm H 2 N 2 , and 500 to 1000 sccm O 2 using a photoresist removal device using microwaves.
본 발명 목적은, 반도체기판 상에 적층된 제1층간절연층에 하부금속라인을 형성한 후, 제2층간절연층을 적층하는 단계와; 상기 제2층간절연층 상에 제1감광막을 적층하여 콘택패턴을 형성한 후, 식각으로 하부금속라인에 연결되는 제1콘택홀을 형성하는 단계와; 상기 콘택홀 내에 금속층을 매립한 후, 마스킹식각으로 제2층간절연층 상부로 돌출되는 금속플러그를 형성하는 단계와; 상기 결과물 상에 제3절연층을 적층한 후 식각으로 금속플러그의 높이로 맞추는 단계와; 상기 결과물 상에 상부금속라인을 적층하는 단계를 포함하여 이루어진 유기물질을 이용한 콘택홀 형성방법을 제공함으로써 달성된다.An object of the present invention is to form a lower metal line in a first interlayer insulating layer stacked on a semiconductor substrate, and then stacking a second interlayer insulating layer; Forming a contact pattern by stacking a first photoresist layer on the second interlayer insulating layer, and forming a first contact hole connected to the lower metal line by etching; Filling a metal layer in the contact hole, and then forming a metal plug protruding over the second interlayer insulating layer by masking etching; Stacking a third insulating layer on the resultant and adjusting the height of the metal plug by etching; It is achieved by providing a method for forming a contact hole using an organic material comprising the step of laminating an upper metal line on the resultant.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 1(a) 내지 도 1(h)은 본 발명의 일 실시예에 따른 유기물질을 이용한 콘택홀 형성방법을 순차적으로 보인 도면이다.1 (a) to 1 (h) are views sequentially showing a method for forming a contact hole using an organic material according to an embodiment of the present invention.
도 1(a)에 도시된 바와 같이, 반도체기판(10) 상에 적층된 제1층간절연층 (15)에 하부금속라인(20)을 형성한 후, 제2층간절연층(25)을 적층하도록 한다.As shown in FIG. 1A, after forming the lower metal line 20 on the first interlayer insulating layer 15 stacked on the semiconductor substrate 10, the second interlayer insulating layer 25 is laminated. Do it.
이 때, 상기 제2층간절연층(25)은, 화학기계적연마공정(CMP; Chemical Polishing Polishing)으로 평탄화하여 2500 ∼ 3500Å정도의 두께로 잔류하는 것이 바람직 하다.At this time, it is preferable that the second interlayer insulating layer 25 is flattened by a chemical mechanical polishing process (CMP) to remain at a thickness of about 2500 to 3500 kPa.
그리고, 상기 제2층간절연층(25) 상에 제1감광막(30)을 적층하여 콘택패턴 (35)을 형성하도록 한다.The first photosensitive film 30 is stacked on the second interlayer insulating layer 25 to form the contact pattern 35.
도 1(b)에 도시된 바와 같이, 마스킹식각공정으로 상기 하부금속라인(20)에 연결되는 제1콘택홀(40)을 형성하도록 한다.As shown in FIG. 1 (b), the first contact hole 40 connected to the lower metal line 20 is formed by a masking etching process.
도 1(c) 및 도1(d)에 도시된 바와 같이, 상기 콘택홀(40)내에 유기계 절연층 (50)을 매립한 후, 식각으로 제1콘택홀 (40) 내에 만 절연층(50)을 잔류시키도록 한다.As shown in FIGS. 1 (c) and 1 (d), after filling the organic insulating layer 50 in the contact hole 40, only the insulating layer 50 is formed in the first contact hole 40 by etching. ) To remain.
상기 유기계절연층(50)은, 플라즈마 공정을 이용하여 60 ∼80mT, 1000 ∼ 1200Watt, 90 ∼ 110sccm N2가스를 90 ∼ 110sccm의 유량으로 공급하고, H2가스를 200 ∼ 400sccm 의 유량을 공급하는 조건으로 식각하는 것이 바람직 하다.The organic insulating layer 50 supplies 60 to 80 mT, 1000 to 1200 Watts, and 90 to 110 sccm N 2 gas at a flow rate of 90 to 110 sccm, and supplies a H 2 gas at a flow rate of 200 to 400 sccm using a plasma process. It is preferable to etch under conditions.
또는, 상기 유기계절연층(50)은, 마이크로웨이브를 이용한 감광막 제거장치 (PR Stepper)를 이용하여, 1000 ∼ 1200Watt, 1400 ∼ 1600mTorr, H2N2가스를 1500∼ 2000 sccm 의 유량으로 공급하고, O2가스를 500 ∼ 1000sccm 의 유량을 공급하는 조건으로 식각하도록 한다.Alternatively, the organic insulating layer 50 supplies 1000 to 1200 Watts, 1400 to 1600 mTorr, and H 2 N 2 gas at a flow rate of 1500 to 2000 sccm using a photoresist removal device (PR Stepper) using microwaves. The O 2 gas is etched under the condition of supplying a flow rate of 500 to 1000 sccm.
도 1(e) 및 도(f)에 도시된 바와 같이, 상기 결과물 상에 2500 ∼ 3500Å의 두께로 제3절연층(55)을 적층한 후, 제3층간절연막(55)을 식각하여 상기 제1콘택홀 (40)에 매립된 절연층(50)으로 연결되는 제2콘택홀(70)을 형성하도록 한다.As shown in FIGS. 1 (e) and (f), after the third insulating layer 55 is laminated on the resultant with a thickness of 2500 to 3500 GPa, the third interlayer insulating layer 55 is etched to form the third insulating layer 55. FIG. The second contact hole 70 connected to the insulating layer 50 embedded in the first contact hole 40 is formed.
그리고, 도 1(g)에 도시된 바와 같이, 상기 제1콘택홀(70) 내에 잔류된 절연층(50)을 제거한 후, 제1,제2콘택홀(70)내에 상부금속라인(75)을 적층하도록 한다.As shown in FIG. 1G, after removing the insulating layer 50 remaining in the first contact hole 70, the upper metal line 75 in the first and second contact holes 70 is removed. To be stacked.
도 2(a) 내지 도 2(g)은 본 발명의 다른 실시예에 따른 유기물질을 이용한 콘택홀 형성방법을 순차적으로 보인 도면이다.2 (a) to 2 (g) are views sequentially showing a method for forming a contact hole using an organic material according to another embodiment of the present invention.
도 2(a)에 도시된 바와 같이, 반도체기판(110) 상에 적층된 제1층간절연층 (115)에 하부금속라인(120)을 형성한 후, 제2층간절연층(125)을 적층한다. 그리고, 상기 제2층간절연층(125) 상에 제1감광막(130)을 적층하여 콘택패턴(135)을 형성한다.As shown in FIG. 2A, after forming the lower metal line 120 on the first interlayer insulating layer 115 stacked on the semiconductor substrate 110, the second interlayer insulating layer 125 is laminated. do. The first photoresist layer 130 is stacked on the second interlayer insulating layer 125 to form a contact pattern 135.
도 2(b)에 도시된 바와 같이, 상기 제1감광막(130)의 콘택패턴(135)을 통하여 제2층간절연층(125)을 식각으로 하부금속라인(120)에 연결되는 콘택홀(140)을 형성하도록 한다.As shown in FIG. 2B, the contact hole 140 is connected to the lower metal line 120 by etching the second interlayer insulating layer 125 through the contact pattern 135 of the first photoresist layer 130. ) To form.
도 2(c)에 도시된 바와같이, 상기 콘택홀(140)내에 금속층(150)을 매립하도록 한다.As shown in FIG. 2C, the metal layer 150 is buried in the contact hole 140.
그리고, 도 2(d)에 도시된 바와 같이, 상기 금속층(150)을 마스킹식각으로제2층간절연층(125)의 상부로 돌출되는 금속플러그(153)를 형성 한다.As shown in FIG. 2 (d), a metal plug 153 protruding to the upper portion of the second interlayer insulating layer 125 is formed by masking the metal layer 150.
그리고, 도 2(e) 및 도2(f)에 도시된 바와 같이, 상기 결과물 상에 제3절연층(153)을 적층한 후 식각으로 금속플러그(153)의 높이로 맞추도록 한다.As shown in FIGS. 2E and 2F, after stacking the third insulating layer 153 on the resultant, the height of the metal plug 153 is adjusted by etching.
도 2(g)에 도시된 바와 같이, 상기 결과물 상에 상부금속라인(175)을 적층하도록 한다.As shown in FIG. 2 (g), the upper metal line 175 is stacked on the resultant.
상기한 바와 같이, 본 발명에 따른 유기물질을 이용한 콘택홀 형성방법을 이용하게 되면, 상,하부금속배선층을 연결시키는 금속플러그를 콘택홀 내부에 매립하여 형성할 때, 콘택홀의 불량식각을 방지하기 위하여 절연층을 두 번에 걸쳐서 적층하여 콘택홀을 이중에 걸쳐서 식각 형성하므로 콘택홀의 식각불량으로 인한 이물질이 콘택홀에 잔류됨으로 인한 소자의 전기적인 특성 저하를 방지하도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the contact hole forming method using the organic material according to the present invention is used, when the metal plugs connecting the upper and lower metal wiring layers are buried in the contact holes to prevent defective etching of the contact holes. In order to etch the insulating layer through two times to form a contact hole through the double is a very useful and effective invention to prevent the deterioration of the electrical characteristics of the device due to the foreign matter remaining in the contact hole due to the etch defect of the contact hole.
Claims (6)
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| KR1019990059519A KR100351445B1 (en) | 1999-12-20 | 1999-12-20 | Method For Forming The Contact Hole Using The Organic Material |
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| JPH06188317A (en) * | 1992-12-21 | 1994-07-08 | Kawasaki Steel Corp | Manufacture of semiconductor device |
| JPH06295906A (en) * | 1993-04-08 | 1994-10-21 | Toshiba Corp | Manufacture of semiconductor device |
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| JPH06188317A (en) * | 1992-12-21 | 1994-07-08 | Kawasaki Steel Corp | Manufacture of semiconductor device |
| JPH06295906A (en) * | 1993-04-08 | 1994-10-21 | Toshiba Corp | Manufacture of semiconductor device |
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