JP2000133711A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize multilayer wiring which has high reliability. SOLUTION: This device 100 contains a first wiring layer 20, an interlayer insulating layer 30 formed on the first wiring layer 20, a second wiring layer 60 formed on the interlayer insulating layer 30, a plurality of through-holes 40 for connecting the first wiring layer 20 and the second wiring layer 60, and contact layers 50 formed in the plurality of through-holes 40. At least one of the through-hole 40 is so constituted that at least one part of the first wiring layer 20 is eliminated, and the bottom surface is a continuous surface constituted of a surface 30a of the interlayer insulating layer and a surface 20a of the first wiring layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a multilayer wiring layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the demand for miniaturization and high integration of semiconductor devices, multilayer wiring has been attempted. For example, the following technology is known as a technology for achieving multilayer wiring.

A technique for realizing multilayer wiring will be described with reference to FIGS.

First, a description will be given with reference to FIG. A first interlayer insulating layer 212 is formed over a semiconductor substrate 210 on which a semiconductor element and the like are formed. First interlayer insulating layer 212
On, for example, a conductive layer (eg, aluminum alloy)
222 and an antireflection film (for example, titanium nitride) 224
Are sequentially formed. Next, the conductive layer 222 and the antireflection film 224 are formed by photolithography and dry etching.
Are patterned to form a lower wiring layer 220. On the lower wiring layer 220 and the first interlayer insulating layer 212,
A second interlayer insulating layer 230 is formed.

As shown in FIG. 8, the second interlayer insulating layer 23
On resist 0, a resist layer R2 having a predetermined pattern is formed by photolithography. Resist layer R2
Has an opening above a region where a through hole is to be formed. Using the resist layer R2 as a mask, the second
Is dry-etched to form a through-hole 240 reaching the lower wiring layer 220. The through hole 240 has a role of connecting the lower wiring layer 220 and an upper wiring layer 260 described later.

[0009] As shown in FIG. 9, a conductive material is filled in the through-hole 240 to form a contact layer 250. On the second interlayer insulating layer 230 and the contact layer 250, a conductive layer 262 and an antireflection film 264 are sequentially formed. The conductive layer 262 and the antireflection film 264 are patterned by photolithography and dry etching to form the upper wiring layer 260. As described above, multilayer wiring can be achieved.

In recent years, attention has been paid to a technique in which the pattern width of the wiring layer is made as narrow as the width of the through hole 240 for further miniaturization and multilayering. But,
As the pattern width of the wiring layer becomes narrower, the misalignment of the pattern of the resist layer R2 adversely affects the reliability of the wiring layer. That is,
When the second interlayer insulating layer 230 is etched to form the through hole 240 in a state where the pattern of the resist layer R2 is misaligned, the first wiring layer is over-etched as shown in FIG. A trench 232 occurs near the sidewall of 220. The presence of the trench 232 causes the following problem when filling the through hole 240 with the conductive material forming the contact layer 250. That is, since it is difficult to fill the trench 232 with a conductive material, a void 270 due to the trench 232 is generated as shown in FIG. This void 270
This significantly deteriorates the reliability of the wiring layer.

As a technique for preventing the void 270 from being generated even when the pattern of the resist layer R2 is misaligned, for example, there is a technique disclosed in Japanese Patent Application Laid-Open No. 9-298239.

Hereinafter, this technique will be briefly described.

According to this technique, when dry etching is performed on the interlayer insulating film to form a connection hole (through hole), a reaction product of an etching gas and an antireflection film is re-adhered to the bottom of the connection hole. Thus, the occurrence of trenches is prevented. That is, by causing the reaction product of the etching gas and the anti-reflection film to adhere again to the bottom of the connection hole, even if the pattern of the resist layer is misaligned, excessive progress of the etching can be suppressed. for that reason,
The formation of the trench can be prevented, and as a result, no void occurs in the connection hole.

However, this technique requires a step of removing a generated reaction product after forming a connection hole.
Also, removal of the reaction products is difficult.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a highly reliable wiring layer and a method for manufacturing the same.

[0013]

According to the present invention, there is provided a semiconductor device comprising:
A first wiring layer, an interlayer insulating layer formed on the first wiring layer, a second wiring layer formed on the interlayer insulating layer, the first wiring layer, A plurality of through holes for connecting the second wiring layer and a contact layer formed in the plurality of through holes, wherein at least one through hole is at least a part of the first wiring layer Is removed, and the bottom surface is a continuous surface formed by the surface of the interlayer insulating layer and the surface of the first wiring layer.

In the semiconductor device of the present invention, in at least one through hole, the surface of the conductive layer and the surface of the interlayer insulating layer form a continuous surface. Therefore, when the conductive material forming the contact layer is embedded in the through hole forming the continuous surface, the conductive material can be embedded well in the through hole. As a result, the semiconductor device of the present invention
High reliability of wiring layer.

Examples of the form of the continuous surface include a plane, a curved surface and a form having a curved surface.

The first wiring layer can be made of at least one of a silicon layer and a metal layer.

The semiconductor device of the present invention can be manufactured, for example, by the following method of manufacturing a semiconductor device.
That is, the method of manufacturing a semiconductor device according to the present invention includes the steps (A)
Forming a wiring layer, (B) forming an interlayer insulating layer on the first wiring layer, and (C) reaching the first wiring layer at a predetermined position of the interlayer insulating layer. Forming a plurality of through holes; and (D) forming a contact layer in the plurality of through holes and a second wiring layer on the interlayer insulating layer. At least one through hole to be formed is formed by removing at least a part of the first wiring layer, and has a bottom surface formed by a surface of the interlayer insulating layer and a surface of the first wiring layer. It is a continuous surface.

As described above, since the surface of the interlayer insulating layer and the surface of the first wiring layer form a continuous surface on the bottom surface of at least one through hole, the conductive layer is formed in the through hole. The constituent conductive material can be satisfactorily embedded. As a result, the semiconductor device obtained by the manufacturing method of the present invention has high reliability of the wiring layer.

The at least one through hole can be formed, for example, by one of the following two methods.

(1) First, the at least one through hole is formed by simultaneously etching a part of the first wiring layer and a part of the interlayer insulating layer. As an etching method of the etching, for example, reactive ion etching (RIE), inductively coupled plasma etching (inductively-co
coupled plasma etching, ECR plasma etching (electron cyclottr)
on response plasma etchin
g). As an etchant for the etching, for example, a mixed gas containing a CF-based gas can be used. Examples of the CF-based gas include CF ₄ , CHF ₃ , C ₂ F ₆ , C ₄ F ₈ , and C ₅ F ₈ . In the etching, the selectivity of the first wiring layer to the interlayer insulating layer (the etching rate of the first wiring layer / the etching rate of the interlayer insulating layer) is 0.5
When it is in the range of from 2.0 to 2.0, a better continuous surface can be formed.

(2) Secondly, the at least one through hole is formed by etching a part of the interlayer insulating layer and further etching a part of the first wiring layer. Examples of the etching method for etching a part of the first wiring layer include inductively coupled plasma etching, downflow plasma etching, and reactive ion etching. The first
As an etchant for etching part of the wiring layer,
A mixed gas containing a chlorine-based gas can be used.

In the above continuous surface, the surface of the interlayer insulating layer and the surface of the first wiring layer are formed on the bottom surface of the through hole.
Even in the case where unevenness having a microscopic step is formed, it includes a surface that can sufficiently fill the through hole with the conductive material.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) (Structure of Device) Semiconductor device 1 according to the present embodiment
00 will be described. FIG. 1 is a sectional view schematically showing a semiconductor device 100 according to the present embodiment.

On the surface of the substrate 10 of the semiconductor device 100,
Semiconductor elements such as MOSFETs, wiring layers, and element isolation regions (not shown) are formed. On the substrate 10,
A first interlayer insulating layer 12 is formed. On the first interlayer insulating layer 12, a first wiring layer 20 is formed.
The first wiring layer 20 includes a conductive layer 22 and an antireflection film 24 formed on the conductive layer 22, and is patterned in a predetermined pattern. In the first interlayer insulating layer 12, a contact hole (not shown) for connecting the semiconductor element or the wiring layer formed on the surface of the substrate 10 to the first wiring layer 20 is formed. In the contact hole, a contact layer (not shown) such as a tungsten plug or an aluminum alloy layer is formed.

On the first wiring layer 20 and the first interlayer insulating layer 12, a second interlayer insulating layer 30 is formed.
Through holes 40 are formed at predetermined positions of the second interlayer insulating layer 30. On the bottom surface of the through hole 40, the upper surface 20a of the first wiring layer and the upper surface 30a of the second interlayer insulating layer form a continuous surface. Through hole 4
In 0, a contact layer 50 is formed. On the second interlayer insulating layer 30 and the contact layer 50, a second wiring layer 60 is formed. The second wiring layer 60 includes a conductive layer 62 and an antireflection film 6 formed on the conductive layer 62.
4 Further, the second wiring layer 60 is connected to the first wiring layer 20 via the contact layer 50.

The semiconductor device 100 according to the present embodiment is characterized in that, for example, on the bottom surface of the through hole 40, the upper surface 20a of the first wiring layer and the upper surface 30a of the second interlayer insulating layer are continuous. That is, it constitutes a surface. That is, in the vicinity of the side wall of the first wiring layer 20, there is no trench (see Background Art) generated by excessive etching of the second interlayer insulating layer 30.
Upper surface 20a of first wiring layer and upper surface 3 of second interlayer insulating layer
The conductive material forming the contact layer 50 can be satisfactorily buried in the through-hole 40 because 0a forms a continuous surface. That is, the conductive material can be embedded in the through hole 40 without generating a void. Therefore, the semiconductor device 100 according to the present embodiment has high reliability of the wiring layer. Further, according to the configuration of the semiconductor device 100 according to the present embodiment, the wiring structure can be miniaturized and high integration can be achieved while ensuring the reliability of the wiring layer.

(Second Embodiment) (First Method of Manufacturing Semiconductor Device) Next, a method of manufacturing a semiconductor device 100 according to the present embodiment will be described. 2 to 4 are cross-sectional views schematically showing manufacturing steps of the semiconductor device 100 according to the present embodiment.

(1) Formation of First Wiring Layer First, description will be made with reference to FIG. By a general method, a semiconductor element (for example, MOSF
ET), a wiring layer and an element isolation region (not shown) are formed. A first interlayer insulating layer 12 is formed on a substrate 10.
Details of first interlayer insulating layer 12 (formation method, material, film thickness)
Is the same as that of a second interlayer insulating layer 30 described later. A contact hole (not shown) is formed in the first interlayer insulating layer 12 by anisotropic reactive ion etching (RIE). A contact layer (not shown) such as a tungsten plug or an aluminum alloy layer is formed in the contact hole by a known method.

A first wiring layer 20 is formed on the first interlayer insulating layer 12 and the contact layer. First wiring layer 20
Is composed of a conductive layer 22 and an antireflection film 24, and is formed, for example, as follows.

First, a conductive layer 22 is formed on the first interlayer insulating layer 12 and the contact layer. The thickness of the conductive layer 22 varies depending on the design of the device.
1000 nm. The material of the conductive layer 22 is not particularly limited, and examples thereof include aluminum, copper, an aluminum alloy, a copper alloy, polycrystalline silicon, and tungsten. The conductive layer 22 may be formed by CVD
Method, sputtering method, vapor deposition method, coating method and the like.

Next, an antireflection film 24 is formed on the conductive layer 22. The thickness of the antireflection film 24 is not particularly limited,
For example, it is 20 to 100 nm. The material of the antireflection film 24 is, for example, titanium nitride or titanium tungsten. The method for forming the anti-reflection film 24 is not particularly limited, and when the anti-reflection film 24 is made of titanium nitride, sputtering can be used. When the conductive layer 22 and the antireflection film 24 are formed by sputtering, it is preferable that the conductive layer 22 and the antireflection film 24 be formed continuously in a vacuum.

Next, the conductive layer 22 and the antireflection film 24
Is patterned by photolithography and dry etching to form a first wiring layer 20.

(2) Formation of Second Interlayer Insulating Layer Next, as shown in FIG.
A second interlayer insulating layer 30 is formed on the interlayer insulating layer 12 of FIG. The thickness of the second interlayer insulating layer 30 is not particularly limited, and may be, for example, 50 with respect to the upper surface of the first wiring layer 20.
0 to 1500 nm. As a material of the second interlayer insulating layer 30, for example, silicon oxide can be given. When silicon oxide is used as the material of the second interlayer insulating layer 30, the silicon oxide may contain phosphorus, boron, or the like. As a method of forming the second interlayer insulating layer 30, for example, a high-density plasma CVD method, a thermal CVD method,
Examples include a coating method (a method using SOG) such as a plasma CVD method, a normal pressure CVD method, and a spin coating method, a sputtering method, and a thermal evaporation method. When the second interlayer insulating layer 30 is formed by a plasma CVD method, it is preferable to form the second interlayer insulating layer 30 by a parallel plate RF plasma CVD apparatus. When the second interlayer insulating layer 30 is formed by a parallel plate RF plasma CVD apparatus, tetraethoxysilane (TEOS) can be used as a gas.

Next, if necessary, the second interlayer insulating layer 3
The second interlayer insulating layer 30 is flattened by the CMP method until the thickness of 0 becomes, for example, 500 to 1500 nm based on the upper surface of the first wiring layer.

(3) Formation of Through Hole Next, as shown in FIG. 4, a resist layer R1 having a predetermined pattern is formed on the second interlayer insulating layer 30 by photolithography. The resist layer R1 has the first
Has an opening above the wiring layer 20. That is, the resist layer R1 has an opening above the region of the second interlayer insulating layer 30 where the through hole 40 is to be formed.

Next, using the resist layer R1 as a mask, the second interlayer insulating layer 30 is etched to form a through hole 40.
To form The etching of the second interlayer insulating layer 30 is performed by a method capable of simultaneously etching the second interlayer insulating layer 30 and the first wiring layer 20, for example, by dry etching. Specific examples of preferable dry etching include, for example, reactive ion etching, inductively coupled plasma etching, and ECR plasma etching. The etchant of this etching is performed by using the second interlayer insulating layer 30 and the first wiring layer 20.
Are not particularly limited as long as they can be simultaneously etched. Preferred examples of the etchant include a mixed gas containing a CF-based gas. As the CF-based _{gas, CF 4, CHF 3, C} 2 F 6, C 4 F 8, it is preferable from the C ₅ F ₈ is at least one selected. Further, the mixed gas containing CF-based gas is CO, Ar,
It is preferable to include at least one selected from O ₂ and N ₂ . First wiring layer 2 for second interlayer insulating layer 30
The selectivity of 0 (the etching rate of the first wiring layer / the etching rate of the second interlayer insulating layer) is preferably in the range of 0.5 to 2.0.

By such an etching method, the second
When the pattern of the resist layer R1 is misaligned by etching the interlayer insulating layer 30 of
When the first interlayer insulating layer 30 is etched,
0 can be etched simultaneously. For this reason, when the misalignment of the pattern of the resist layer R1 occurs,
On the bottom surface of the through hole 40, the upper surface 30a of the second interlayer insulating layer and the upper surface 20a of the first wiring layer form a continuous surface. That is, the trench 32 does not occur near the side wall of the first wiring layer 20. Further, by controlling the selection ratio and the like, the bottom surface of the through-hole 40 can be made a better continuous surface.

(4) Formation of Contact Layer to Second Wiring Layer Next, after the resist layer R1 is removed by ashing, a contact layer 50 is formed in the through hole 40 as shown in FIG. Contact layer 50 is formed, for example, by filling a conductive material in through hole 40 and etching back the conductive material. Examples of the conductive material include tungsten, aluminum, an aluminum alloy, copper, and a copper alloy. Conductive material through hole 40
As a method of filling the inside, a CVD method, a PVD method, and a plating method can be exemplified. Also, the second interlayer insulating layer 3
At least one of a wetting layer and a barrier layer may be interposed between the zero and second wiring layers 60 and the contact layer 50.

The second wiring layer 60 is formed on the second interlayer insulating layer 30 and the contact layer 50. The details (for example, film thickness, material, forming method) of the second wiring layer 60 are the same as those of the first wiring layer 20. Thus, the semiconductor device 1
00 is completed.

The features of this embodiment are, for example, as follows. That is, when the second interlayer insulating layer 30 is etched to form the through hole 40, an etching method that can simultaneously etch the second interlayer insulating layer 30 and the first wiring layer 20 is used. It is that you are. Thereby, when misalignment of the resist pattern occurs, the second interlayer insulating layer 30 and the first wiring layer 20 can be simultaneously etched. Therefore, when misalignment occurs, the upper surface 30a of the second interlayer insulating layer is formed on the bottom surface of the through hole 40.
And the upper surface 20a of the first wiring layer can form a continuous surface. That is, a trench due to partial overetching of the second interlayer insulating layer 30 does not occur near the side wall of the first wiring layer 20.

Since the upper surface 30a of the second interlayer insulating layer and the upper surface 20a of the first wiring layer form a continuous surface, when forming the contact layer 50, the contact hole is formed in the through hole 40. The conductive material forming the layer 50 can be satisfactorily embedded. That is, the conductive material can be embedded in the through hole 40 without generating a void.

Therefore, according to the method of manufacturing a semiconductor device according to the present embodiment, the reliability of the wiring layer can be improved. In addition, according to the configuration of the semiconductor device obtained by this method of manufacturing a semiconductor device, it is possible to miniaturize the wiring structure and achieve high integration while securing the reliability of the wiring layer.

(Third Embodiment) (Manufacturing Method of Second Semiconductor Device) The manufacturing method of a semiconductor device according to the third embodiment is different from the second embodiment in the method of forming the through hole 40. This is different from the method for manufacturing a semiconductor device according to the embodiment. Otherwise, the second embodiment is substantially the same as the second embodiment, and a detailed description thereof will be omitted. Parts having the same functions are denoted by the same reference numerals.

(1) Formation of Through-hole In the same manner as in the steps (1) and (2) according to the second embodiment, the formation up to the second interlayer insulating layer 30 is performed.

FIGS. 5 and 6 are cross-sectional views schematically showing steps for forming through holes.

As shown in FIG. 5, the second interlayer insulating layer 30
A resist layer R1 having a pattern similar to that of the second embodiment is formed on the substrate by photolithography.
Using the resist layer R1 as a mask, the second interlayer insulating layer 30
Is etched. Hereinafter, the etching of the second interlayer insulating layer 30 is referred to as “first etching”. The first etching is performed until the upper surface of the first wiring layer 20 is exposed. Here, as shown in FIG. 5, when the pattern of the resist layer R1 is misaligned, a trench 32 is formed near the side wall of the first wiring layer 20. The first etching method is not particularly limited, and includes, for example, dry etching. Specific examples of preferable dry etching include reactive ion etching, inductively coupled plasma etching, and ECR plasma etching. The etchant is not particularly limited as long as it can etch the second interlayer insulating layer 30, and a mixed gas containing a CF-based gas can be used. As the CF-based _{gas, CF 4, CHF 3, C} 2 F 6, C 4 F 8, it is preferable from the C ₅ F ₈ is at least one selected. Also,
The mixed gas containing the CF-based gas is CO, Ar, O ₂ , N ₂
It is preferable to include at least one selected from

Next, as shown in FIG.
After the ashing is removed, the first wiring layer 20 is etched using the second interlayer insulating layer 30 as a mask. The first wiring layer 20 is etched by the depth of the trench 32 generated in the first etching. That is, the upper surface 20 of the first wiring layer on the bottom surface of the through hole 40
The first wiring layer 20 is etched until a and the upper surface 30a of the second interlayer insulating layer form a continuous surface. Thus, even if the trench 32 occurs due to misalignment of the pattern of the resist layer R1, the trench 32 can be eliminated. Hereinafter, the etching of the first wiring layer 20 is referred to as “second etching”. When the second etching is completed, a through hole 40 is formed. As the etching method of the second etching, the first method
The method is not particularly limited as long as the method can etch the wiring layer 20. Preferred etching methods include inductively coupled plasma etching, downflow plasma etching, and reactive ion etching. The etchant is not particularly limited as long as it can etch the first wiring layer 20. Preferred examples of the etchant include a mixed gas containing a chlorine-based gas. As this chlorine-based gas, C
It is preferably at least one selected from l ₂ and BCl ₃ . The mixed gas containing chlorine-based gas is C
It is preferable to include at least one selected from O, Ar, O ₂ , and N ₂ . The second etching is preferably performed under conditions that do not cause side etching of the first wiring layer 20.

(2) Formation of Contact Layer to Second Wiring Layer As shown in FIG. 1, a contact layer 50 is formed in the through hole 40, as in the second embodiment. Then, a second wiring layer 60 is formed on the second interlayer insulating layer 30 and the contact layer 50 as in the second embodiment. Thus, the semiconductor device 100 is completed.

The feature of this embodiment is that the first
Is performed, and then the second etching is performed. That is, even if a trench 32 is generated at the time when the first etching is completed due to the misalignment of the resist layer R1, the second etching allows the second interlayer to be formed on the bottom surface of the through hole 40. Upper surface 30a of insulating layer and upper surface 20 of first wiring layer
a constitutes a continuous surface. Since the upper surface 30a of the second interlayer insulating layer and the upper surface 20a of the first wiring layer form a continuous surface, when the contact layer 50 is formed, the conductive material is favorably placed in the through hole 40. Can be embedded. That is, the conductive material can be embedded in the through hole 40 without generating a void. Therefore, according to the method of manufacturing a semiconductor device according to the present embodiment, the reliability of the wiring layer can be improved. Also,
According to the configuration of the semiconductor device obtained by the method of manufacturing a semiconductor device, the wiring structure can be miniaturized and high integration can be achieved while ensuring the reliability of the wiring layer.

In the present embodiment, the upper surface 20a of the first wiring layer on the bottom surface of the through hole 40,
As long as the upper surface 30a of the second interlayer insulating layer forms a continuous surface, the second interlayer insulating layer 3
0 may be etched.

(Experimental Example) (First Experimental Example) A through hole was formed by etching the second interlayer insulating layer under the following experimental conditions according to the method of manufacturing the semiconductor device of the second embodiment. The following findings were obtained. That is, when the through holes were formed under the following experimental conditions, the etching rates of the first wiring layer and the second interlayer insulating layer 30 could be made substantially equal. Therefore, at the bottom of the through hole,
The upper surface of the second interlayer insulating layer and the upper surface of the first wiring layer formed a continuous surface (substantially horizontal plane). That is, no trench was formed near the side wall of the first wiring layer.

(Experimental Conditions) (Etching Conditions) Etching Equipment: Reactive Ion Etching (RI
E) Apparatus Etching gas: CHF ₃ / Ar / N ₂ = 80 sccm / 20
0 sccm / 6 sccm RF power: 1300 W Pressure: 150 mTorr (= 19.95 Pa) Substrate temperature: 50 ° C. (second interlayer insulating layer) Material: silicon oxide Film thickness: 0.8 μm (first wiring layer) Material of conductive layer ： Aluminum alloy Anti-reflective coating material ： Titanium nitride

(Second Experimental Example) Through holes were formed under the following experimental conditions according to the method of manufacturing a semiconductor device according to the third embodiment. The following findings were obtained. That is, by forming the through hole under the following experimental conditions, the upper surface of the second interlayer insulating layer and the upper surface of the first wiring layer formed a continuous surface (substantially horizontal surface) on the bottom surface of the through hole. . That is, no trench was formed near the side wall of the first wiring layer.

(Experimental Conditions) (First Etching Conditions) Etching apparatus: Reactive ion etching (RI
E) Apparatus Etching gas: CHF ₃ / Ar / N ₂ = 80 sccm / 50
sccm / 10 sccm RF power: 500 W Pressure: 100 mTorr (= 13.3 Pa) Substrate temperature: 20 ° C. (second etching condition) Etching apparatus: Inductively coupled plasma etching apparatus Etching gas: Cl ₂ / BCl ₃ / Ar = 40 sccm / 5
0 sccm / 70 sccm Pressure: 3 mTorr (= 0.339 Pa) Source power: 1000 W Bias power: 1500 W Substrate temperature: 40 ° C. Etching time: 10 sec (Other conditions) (Second interlayer insulating layer) Material: Silicon oxide Film thickness: 0 0.8 μm (first wiring layer) Material of conductive layer: aluminum alloy Material of antireflection film: titanium nitride Various modifications can be made to the above embodiment without departing from the scope of the present invention. For example, the following changes are possible.

Although the contact layer 50 and the conductive layer 62 forming the second wiring layer 60 are formed separately in the second and third embodiments, they may be formed simultaneously. The material of the contact layer 50 and the second wiring layer in this case is, for example, aluminum, aluminum alloy,
Copper, copper alloy, tungsten and the like can be mentioned.
In addition, as a method for forming the contact layer 50 and the conductive layer 62, a CVD method, a PVD method, a plating method, and the like can be given.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to the first embodiment.

FIG. 4 is a cross-sectional view schematically showing steps of a method for manufacturing the semiconductor device according to the first embodiment.

FIG. 5 is a sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a second embodiment.

FIG. 6 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 7 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 8 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 9 is a cross-sectional view schematically showing steps of a method for manufacturing a semiconductor device according to a conventional example.

[Explanation of symbols]

 Reference Signs List 10 substrate 12 first interlayer insulating layer 20 first wiring layer 20a upper surface of first wiring layer 30 second interlayer insulating layer 30a upper surface of second interlayer insulating layer 32 trench 40 through hole 50 contact layer 60 second Wiring layer R1 resist layer

Claims (15)

[Claims] A first wiring layer; an interlayer insulating layer formed on the first wiring layer; a second wiring layer formed on the interlayer insulating layer; A plurality of through holes for connecting a wiring layer and the second wiring layer; and a contact layer formed in the plurality of through holes, wherein at least one through hole includes at least the first
A semiconductor device, wherein a part of the wiring layer is removed and a bottom surface thereof is a continuous surface formed by a surface of the interlayer insulating layer and a surface of the first wiring layer. 2. The semiconductor device according to claim 1, wherein the continuous surface is a flat surface or a curved surface. 3. The semiconductor device according to claim 1, wherein the continuous surface has a curved surface. 4. The semiconductor device according to claim 1, wherein the first wiring layer includes at least one of silicon and a metal layer. 5. A step of forming a first wiring layer.
(B) a step of forming an interlayer insulating layer on the first wiring layer; (C) forming the first insulating layer at a predetermined position of the interlayer insulating layer;
A process of forming a plurality of through holes reaching the wiring layer of
And (D) forming a contact layer in the plurality of through holes and a second wiring layer on the interlayer insulating layer, wherein at least one through hole formed in the step (C) is A semiconductor device, wherein at least a part of the first wiring layer is removed and a bottom surface thereof is a continuous surface formed by a surface of the interlayer insulating layer and a surface of the first wiring layer; Manufacturing method. 6. The method according to claim 5, wherein the continuous surface is a flat surface or a curved surface. 7. The method according to claim 5, wherein the continuous surface has a curved surface. 8. The method for manufacturing a semiconductor device according to claim 5, wherein the first wiring layer is made of at least one of a silicon layer and a metal layer. 9. The method according to claim 5, wherein the at least one through hole is formed by simultaneously etching a part of the first wiring layer and a part of the interlayer insulating layer. A method for manufacturing a semiconductor device. 10. The etching method according to claim 9, wherein the etching method includes reactive ion etching, inductively coupled plasma etching, and ECR.
A method for manufacturing a semiconductor device, which is plasma etching. 11. The method of manufacturing a semiconductor device according to claim 9, wherein the etchant for etching is a mixed gas containing a CF-based gas. 12. The selectivity of the first wiring layer with respect to the interlayer insulating layer in the etching according to claim 9, wherein the etching rate of the first wiring layer / the etching rate of the interlayer insulating layer. Is from 0.5 to 2.0. 13. The at least one through hole according to claim 5, wherein the at least one through hole is formed by etching a part of the interlayer insulating layer and further etching a part of the first wiring layer. Manufacturing method of a semiconductor device. 14. The method of manufacturing a semiconductor device according to claim 13, wherein an etching method for etching a part of the first wiring layer is inductively coupled plasma etching, downflow plasma etching, or reactive ion etching. 15. The method for manufacturing a semiconductor device according to claim 13, wherein an etchant for etching part of the first wiring layer is a mixed gas containing a chlorine-based gas.