JP2002198422A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a wiring layer which can reduce a parasitic capacitance between wirings. SOLUTION: A wiring layer wherein a damascene wiring structure having high-level wirings 14 and 15 and a damascene wiring structure having low-level wirings 9 and 10 is formed, and a distance L between the two adjacent damascene wirings structures is set to be long.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device characterized by a wiring structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor elements and the speeding up of semiconductor devices, the wiring structure has been changed from a single-layer structure to a multi-layer structure, and semiconductor devices having five or more multi-layer wirings have been developed and produced. However, as miniaturization, high speed, and multi-layering progress,
Signal transmission delay due to so-called parasitic capacitance between wirings and wiring resistance has become a serious problem.

[0003] Various methods have been employed to avoid signal transmission delay. For example, in order to reduce the wiring resistance, A
Cu having a resistivity lower than 1 is used as a wiring material. Since it is extremely difficult with the current technology to dry-etch a Cu film into a wiring shape in the same manner as in the past, a buried wiring structure (damascene structure) is adopted in the case of Cu wiring. On the other hand, in order to reduce the parasitic capacitance between wirings, a so-called l having a lower dielectric constant than SiO ₂ is used.
What is called ow-k is used as an insulating material.

However, as miniaturization further progresses in the future, it is expected that it will be difficult to cope with signal transmission delay due to inter-wiring parasitic capacitance and wiring resistance only by a wiring structure combining Low-k and Cu. Further, it becomes difficult to process the insulating film and bury the wiring material.

[0005]

As described above, with further miniaturization in the future, it is difficult to cope with signal transmission delay due to inter-wiring parasitic capacitance and wiring resistance only by a wiring structure combining Low-k and Cu. It is expected to be.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device having a wiring structure capable of coping with further miniaturization, higher layers, and multilayers, and a method of manufacturing the same. It is in.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

That is, in order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate and a wiring layer formed on the semiconductor substrate and including first and second wiring structures, The first wiring structure includes a first plug and a first wiring formed thereon, the second wiring structure includes a second plug and a second wiring formed thereon; The upper surface of the first wiring is higher than the upper surface of the second wiring, and the lower surface of the first wiring is the same height as the upper surface of the second wiring or lower than the upper surface of the second wiring. And a formed wiring layer.

With this configuration, the distance between the wirings between the first wiring structure and the second wiring structure is equal to the distance between the first plug of the first wiring structure and the second plug of the second wiring structure. Is determined by the distance between the wirings, so that the distance between the wirings can be made shorter than before. As a result, the parasitic capacitance between the wirings can be reduced, and accordingly, it is possible to cope with further miniaturization, higher layers, and more layers.

Here, the first and second wirings include an intermediate film when there is a barrier metal film or a liner film (intermediate film) between the wiring main body and the wiring groove. Similarly,
The first and second plugs include an intermediate film when there is an intermediate film between the plug body and the connection hole.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a first insulating film on a semiconductor substrate, etching the first insulating film, and forming a first insulating film on a surface of the first insulating film. A first wiring groove, a first connection hole penetrating the first insulating film between the bottom of the first wiring groove and the semiconductor substrate, and a second connection penetrating the first insulating film. Forming a hole, and filling the first wiring groove, the first connection hole, and the second connection hole with a first conductive film;
Forming a second insulating film on the first insulating film in which the first conductive film is embedded; etching the second insulating film to connect to the second connection hole; Forming a second wiring groove substantially parallel to the wiring groove of the second insulating film, and embedding the second wiring groove with a second conductive film.

In another method for manufacturing a semiconductor device according to the present invention, a step of forming a first insulating film on a semiconductor substrate, and etching the first insulating film to form the first insulating film. A first wiring groove on the surface, a first connection hole penetrating the first insulating film from the bottom of the first wiring groove to the semiconductor substrate, and a second connection hole penetrating the first insulating film. Forming the first connection groove, filling the first wiring groove, the first connection hole, and the second connection hole with a first conductive film, and filling the first conductive film with the first conductive groove. Forming a second insulating film on the first insulating film; etching the second insulating film to connect to the second connection hole;
Forming a second wiring groove substantially parallel to the second wiring groove in the second insulating film, filling the second wiring groove with a second conductive film, and forming a second wiring groove around the second wiring groove. Removing the second insulating film to form a cavity around the second wiring.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating film on a semiconductor substrate; etching the first insulating film to form the first insulating film; A first wiring groove on the surface, a first connection hole penetrating the first insulating film from the bottom of the first wiring groove to the semiconductor substrate, and a second connection hole penetrating the first insulating film. Forming the first connection groove, filling the first wiring groove, the first connection hole, and the second connection hole with a first conductive film, and filling the first conductive film with the first conductive groove. Forming a second insulating film on the first insulating film; etching the second insulating film to connect to the second connection hole;
Forming a second wiring groove substantially parallel to the second wiring groove in the second insulating film, embedding the second wiring groove in a second conductive film, and forming the first and second plugs. And removing the second insulating film around the first and second wirings to form a cavity around the first and second plugs and the first and second wirings. It is characterized by having.

The wiring formed by the method of manufacturing a semiconductor device according to the present invention is, for example, a wiring of a certain layer of a multilayer wiring layer, and specifically, the wiring at the bottom of the multilayer wiring layer and the wiring at the top of the multilayer wiring layer. Or the wiring between the bottom wiring and the top wiring. The bottom wiring is, for example, a wiring connected to a trench capacitor formed in a semiconductor substrate. The wiring of all layers of the multilayer wiring layer may be formed by the method of manufacturing a semiconductor device according to the present invention.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 to 4 are process sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. Here, a magnetron RIE apparatus is used as an etching apparatus for performing the etching of the present invention. The specific configuration of the magnetron RIE apparatus will be described later.

First, as shown in FIG. 1A, S as an interlayer insulating film is formed on a silicon substrate 1 on which elements are integrated.
An iO ₂ film 2 is formed. Then as a hard mask of the SiO ₂ film 2, a polysilicon film 3 on the SiO ₂ film 2. Next, after an antireflection film (for example, a carbon film) 4 is formed on the polysilicon film 3, a photoresist pattern 5 is formed on the antireflection film 4. The photoresist pattern 5 has a first opening O1 corresponding to the first wiring groove and a second opening O2 corresponding to the second connection hole (contact hole).
have.

Next, as shown in FIG. 1B, the antireflection film 4 and the polysilicon film 3 are selectively etched using the photoresist pattern 5 as a mask, and the photoresist pattern 5 Transcribe

The etching conditions at this time are, for example, pressure = 75 [mTorr], input power = 300 [W], etching gas = Cl (75 [sccm]) / O ₂ (10
[Sccm]). Under this condition, S
Since the etching selectivity of the polysilicon film 3 to the iO ₂ film 2 is very high, about 100, the SiO ₂ film 2
Serves as an etching stopper, and the SiO ₂ film 2 is not excessively shaved.

Next, as shown in FIG. 1C, the photoresist pattern 5 and the antireflection film 4 are removed.

Next, as shown in FIG.
After forming a resist 6 of about nm on the entire surface, the resist 6
An SOG film 7 having a thickness of about 100 nm is formed thereon by a coating method. Next, a resist having a thickness of about 300 nm is formed on the SOG film 7, and the resist is exposed and developed to form a photoresist pattern 8. At this time, the SOG film 7 functions as an anti-reflection film at the time of exposure. The photoresist pattern 8 has a third opening O3 corresponding to the first connection hole and a fourth opening O4 corresponding to the second wiring groove.

Next, the photoresist pattern 8 and SO
The resist 6 is selectively etched using the G film 7 as a mask.

At this time, the SOG film 7 is etched using the photoresist pattern 8 as a mask. The etching condition of the SOG film 7 at this time is, for example, pressure = 20 [m
Torr], input power = 1000 [W], etching gas = CF ₄ (60 [sccm]) / O ₂ (10 [scc]
m]).

The resist 6 is initially etched using the photoresist pattern 8 as a mask, but disappears on the way, and is eventually etched using the SOG film 7 as a mask. A cross-sectional view at this stage is shown in FIG. As shown in the figure, a fifth opening O5 corresponding to the first connection hole and a sixth opening O6 corresponding to the second wiring groove are formed in the resist 6.

The etching conditions of the resist 6 are, for example, pressure = 40 [mTorr], input power = 500 [W], etching gas = N ₂ (150 [sccm]) / O ₂ (1
0 [sccm]).

Under the above conditions, the etching selectivity of the resist 6 to the SOG film 7 is 50 or more. The etching selectivity of the SiO ₂ film 2 with respect to the resist 6 is 1
It becomes very high when it is 00 or more. Further, the etching selectivity of the resist 6 with respect to the polysilicon film 3 is also increased, and the polysilicon film 3 becomes an etching stopper.

Next, the SiO ₂ film 2 is selectively etched by using the SOG film 7, the resist 6, and the polysilicon film 3 as a mask, and first and second connection holes (contact holes) are opened in the SiO ₂ film 2. I do. These first and second
Are connected to the first and second conductive regions (for example, diffusion layers) (not shown) formed on the surface of the silicon substrate 1. The SOG film 7 disappears during the etching, and finally the SiO ₂ film 2 is etched using the resist 6 and the polysilicon film as a mask. A cross-sectional view at this stage is shown in FIG.

The etching conditions of the SiO ₂ film 2 are, for example, pressure = 20 [mTorr], input power = 1400
[W], etching gas = C ₄ F ₈ (10 [scc]
m]) / CO (50 [sccm]) / O ₂ (5 [scc
m]) / Ar (100 [sccm]). Under this condition, the SiO ₂ film 2 for the resist 6
Is about 15, and the etching selectivity of the resist 6 to the polysilicon film 3 is about 40.

Although a conductive region such as a diffusion layer having a base formed on the substrate surface has been described herein, a metal wiring layer formed on the silicon substrate 1 may be a base. In this case, the wiring layer described in the present embodiment is a second or higher wiring layer.

Next, as shown in FIG.
Is removed by O ₂ RIE, the SiO ₂ film 2 is etched using the polysilicon film 3 (hard mask) as a mask, and a first wiring groove is formed on the surface of the SiO ₂ film 2. The first wiring groove is substantially parallel to the second wiring groove. The etching conditions at this time are the same as the etching conditions for forming the first and second connection holes (contact holes).

Next, as shown in FIG. 3H, after a barrier metal film or a liner film 9 (intermediate film) and a metal film to be a plug or a plug / wiring 10 are deposited on the entire surface, the CMP is performed.
Unnecessary barrier metal film 9 and metal film outside the first wiring groove and the first and second connection holes (contact holes) are removed by a method, and the surface is flattened. As a result, two dual damascene wiring structures and one plug therebetween are formed simultaneously.

The plug or plug / wiring 10 is
A plug having a higher wiring upper surface (first wiring structure) (a plug body not including an intermediate film) and a plug having a lower wiring upper surface (a second wiring structure) (including an intermediate film) (Plug body without wiring) and wiring (wiring body without intermediate film). In the following description, a plug 10 is a plug having a first wiring structure, a wiring 1
0 is used to mean the wiring of the second wiring structure.

The material of the plug or plug / wiring 10 is A
In the case of l-Cu, examples of the barrier metal film or the liner film 9 include an Nb film (liner film), a Ti film, and a TiN film.
A conductive film such as a film, a Ta film, a TaN film, a Ti film / TiN film, or an insulating thin film having a thickness that can secure electrical connection can be used.

The material of the plug or plug / wiring 10 is
The present invention is not limited to Al-Cu.
l-Si-Cu, Ag, Au, Cu can be used.
Depending on the material, the barrier metal film or the liner film 9 becomes unnecessary.

Next, as shown in FIG. 3I, an SiO ₂ film 11 as an interlayer insulating film is deposited on the entire surface.

Next, as shown in FIG. 3J, an antireflection film 12 and a resist pattern 13 are sequentially formed on the SiO ₂ film 11. The resist pattern 13 has an opening corresponding to the second wiring groove.

[0038] Next, as shown in FIG. 3 (k), the SiO ₂ film 11 is etched by using the resist pattern 13 as a mask, the second leading to the barrier metal film or liner film 9 and the plug 10 in the SiO ₂ film 11 Form wiring grooves.

The figure shows a case where the bottom of the second wiring groove and the upper surface of the wiring 10 are at the same height, that is, an ideal case. However, actually, the bottom of the second wiring groove is 10 is often lower than the top surface. As a result, the bottom surface of the wiring (including the barrier metal film or the liner film, if any) formed in the second wiring groove in a later step is actually lower than the upper surface of the wiring 10. Often.

Next, as shown in FIG. 4L, the resist pattern 13 and the antireflection film 12 are removed. If the anti-reflection film 12 is a film containing carbon as a main component, the resist pattern 13 and the anti-reflection film 12 can be simultaneously peeled off by an asher.

Next, as shown in FIG. 4 (m), after a barrier metal film or a liner film 14 and a metal film to be the wiring 15 (wiring body) are deposited on the entire surface, unnecessary portions outside the wiring grooves are removed by CMP. The barrier metal film or liner film 14 and the metal film are removed to form the wiring 15 and to flatten the surface.

In this way, two dual damascene wirings having different structures are obtained. However, a dual damascene wiring which is higher in terms of process requires two steps of embedding a conductive material and the like, and therefore cannot be called a dual damascene wiring accurately. In the present invention, such wirings having different heights are referred to as damascene wirings for convenience. What is made convenient is whether the damascene wiring is different from the so-called single damascene wiring.

The materials of the barrier metal film or the liner film 14 and the wiring 15 are the same as the material of the barrier metal film or the liner film 9 and the plug or the plug / wiring 10, respectively. The barrier metal film or the liner film 14 becomes unnecessary depending on the material of the wiring 15.

Further, the material of the barrier metal film or the liner film 14 and the material of the wiring 15 may be different from the material of the barrier metal film or the liner film 9 and the plug or the plug / wiring 10, respectively. For example, plug or plug
The material of the wiring 10 is Cu, the material of the wiring 15 is Al, Cu,
It may be Ag or Au or vice versa. That is, at this time, the first and second wirings can be formed using different materials.

As described above, according to the present embodiment, it is possible to obtain a wiring layer in which wiring structures (plugs + wirings) having different wiring heights are alternately formed. That is, it is possible to obtain a wiring layer in which the side surfaces of the wirings of two adjacent wiring structures do not face each other. As a result, the wiring and the adjacent plug are opposed to each other, so that the distance between the wirings adjacent to each other becomes longer, and the parasitic capacitance between the wirings is reduced.

Therefore, it is possible to effectively suppress a signal transmission delay caused by an inter-wiring parasitic capacitance, which becomes conspicuous as the inter-wiring spacing becomes finer. Conversely, if the distance between the wirings is the same, the signal propagation speed increases. Further, according to the present embodiment, it is only necessary to change the height of the wiring alternately, and the wiring pattern viewed from above can be the same as the conventional one, so that the pattern design of the wiring layer is easy.

Further, the distance L1 in the wiring width direction between the wirings (wiring body + intermediate film) of two adjacent wiring structures having different wiring heights is preferably 0.13 [μm] or less. The reason is that the effect of the parasitic capacitance increases when such fine wiring is used, and the effect of the present invention is enormous.
The lower limit of the distance L is larger than 0.

In each of the wiring structures having different wiring heights, the wiring (wiring body + intermediate film) in the wiring width direction corresponds to the dimension L3 (L4) of the plug (plug main body + intermediate film) in the wiring width direction. Ratio L2 / L3 of dimension L2 (L5)
(L5 / L4) [μm] is typically 10 or less (FIG. 4 (m)). The lower limit is greater than one.

Further, according to the present embodiment, since the wiring 15 is disposed above, it is possible to satisfy 1 ≦ L2 / L1. In the conventional case, the value of L2 / L1 is 1.

L1 can be reduced to 0.01 [μm].
The current minimum wiring width is 0.13 [μm]. Therefore, with the current technology, the upper limit of L2 / L1 can be reduced to 13.

In this embodiment, the polysilicon film 3 is used as a hard mask, but a silicon nitride film, a tungsten film, or a WSi film may be used instead.
Also, a SiO ₂ film (silicon oxide film) as an interlayer insulating film
2, but another inorganic silicon oxide film, Low-k film, or organic silicon oxide film may be used instead.

As the Low-k film, polysiloxane,
Examples include an organic silicon oxide film such as benzocyclobutene (BCB), an inorganic silicon oxide film such as hydrogen-silsesquioxane, and a CF-based film such as polyarylene ether, parylene, and polyimide fluoropolymer.

FIGS. 5 and 6 show a first modification of the present embodiment. The difference between the first modification and the present embodiment is that the dimension of the wiring 15 in the horizontal direction (wiring width direction) is increased. As a result, the wiring cross-sectional area of the wiring 15
Larger than the wiring cross-sectional area.

FIG. 7 shows a second modification of the present embodiment.
The second modification is different from the present embodiment in that the high wiring 15
This is to reduce the distance in the wiring width direction between two adjacent wiring structures within a range in which the low wiring 10 and the low wiring 10 are not electrically connected.

FIG. 8 shows a third modification of the present embodiment.
The third modified example is different from the present embodiment in that the wiring 15 is vertically elongated.

FIG. 9 shows a fourth modification of the present embodiment.
The fourth modified example is different from the present embodiment in that one high wiring 15 and one low wiring 10 are not formed alternately. FIG. 9A shows an example in which two high wirings 15 and two low wirings 10 are alternately formed, and FIG. 9B shows one high wiring 15 and two low wirings 10 alternately formed. The example which is formed is shown. In short, one high wiring 15 and two or more low wirings 10 are alternately formed, two or more high wirings 15 and one low wiring 10 are formed alternately, or It is only necessary that the high wirings 15 and the two or more low wirings 1 are alternately formed.

FIG. 83 shows the structure of the above-described magnetron RIE apparatus.

In the figure, reference numeral 51 denotes a vacuum chamber.
A mounting table 53 for mounting the substrate to be processed 52 is provided inside the vacuum chamber 51. A counter electrode 54 is provided above the mounting table 53 so as to face the mounting table 53. The mounting table 53 includes a temperature control mechanism (not shown) so that the temperature of the substrate 52 to be processed can be controlled.

A gas introduction pipe 56 is connected to the top wall 55 of the vacuum chamber 51. An etching gas is introduced into the vacuum chamber 51 from the gas introduction pipe 56. The pressure in the vacuum chamber 51 can be adjusted by a valve (not shown) at the exhaust port 57. Below the vacuum chamber 51, a high-frequency power supply 58 connected to the mounting table 53 is provided.

After the pressure in the vacuum chamber 51 is stabilized,
By applying high-frequency power to the mounting table 53 by the high-frequency power supply 58, plasma can be generated in the vacuum chamber 51.

A magnet 59 is provided on the outer periphery of the vacuum chamber 51. The magnet 59 generates a high-density magnetic field in the vacuum chamber 51. As a result, the ions in the plasma have anisotropy. The substrate 52 to be processed is etched by the anisotropic ions. The dry etching apparatus that can be used in the present invention is not limited to a magnetron RIE apparatus, but may be another dry etching apparatus that uses, for example, electron cyclotron resonance (ECR), helicon waves, inductively coupled plasma, or the like. Can also be used.

(Second Embodiment) FIGS. 10 and 11
FIG. 7 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention. In the following embodiments including this embodiment, portions corresponding to FIGS. 1 to 9, that is, the same reference numerals (including those having different suffixes) from the above-described drawings are denoted by the same reference numerals or corresponding portions. Detailed description is omitted. Therefore, when there is no specific description of the thickness, material, condition, effect, and the like, the specific thickness, material, condition, effect, and the like described above are applied mutatis mutandis as a specific example.

First, FIG. 1A to FIG. 3 of the first embodiment
The steps up to (h) are performed (FIG. 10A).

Next, as shown in FIG. 10B, an organic silicon oxide film 16 as an interlayer insulating film is deposited on the entire surface.

After that, FIG. 3 (j) to FIG.
The steps up to FIG. 4M are performed (FIGS. 10C to 11).
(F)).

According to this embodiment, since the organic silicon oxide film 16 is used as the interlayer insulating film, the parasitic capacitance between the wirings can be further reduced as compared with the first embodiment. Although the organic silicon oxide film 16 is used in this embodiment, a low dielectric constant film such as a low-k film or an inorganic silicon oxide film may be used instead.

Further, the plug / wiring 15 is buried.
First insulating film (here, SiO 1 _TwoFilm 2) and wiring 1
5 is embedded in a second insulating film (here, an organic silicon film).
The combination with the silicon oxide film 16) is made of SiO_TwoMembrane 2 and organic
It is not limited to the combination with the silicon oxide film 16.
In short, the first and second insulating films are low-k films,
Either inorganic silicon oxide film or organic silicon oxide film
Or a combination of different insulating films. In other words,
The first and second wirings are made of different materials
Can be.

FIGS. 12 and 13 show a first modification of this embodiment, FIG. 14 shows a second modification of this embodiment, FIG. 15 shows a third modification of this embodiment, and FIG. 4th form
Are shown below. The first to fourth modified examples of the present embodiment respectively correspond to the first to fourth modified examples of the first embodiment. In addition, in the case of FIG.
Since the distance between the two wirings 10 is the shortest distance between the wirings, the SiO ₂ film 2 may be replaced with a low dielectric constant film such as the organic silicon oxide film 16 if necessary, contrary to the present embodiment. Is also good. In addition, various modifications similar to the first embodiment are possible.

(Third Embodiment) FIGS. 17 and 18
FIG. 9 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

First, FIGS. 1A to 3 of the first embodiment
The steps up to (h) are performed (FIG. 17A).

Next, as shown in FIG.
A k film 17 is formed on the entire surface. The Low-k film 17 is a CF-based film such as flare or silk. In addition, the same effect can be obtained by using a resist, a simple substance of C, or another C-based film not containing Si.

Next, as shown in FIG.
SOG film 7 having a thickness of 100 nm and a thickness of 300 on k film 17
A photoresist pattern 13 of nm is sequentially formed.

Next, the SOG film 7 is anisotropically etched using the photoresist pattern 13 as a mask, the pattern of the photoresist pattern 13 is transferred to the SOG film 7, and subsequently, the photoresist pattern 13 and the SOG film 7 are used as a mask. To etch the Low-k film 17,
A wiring groove is formed in the film 17.

The low-k film 17 is initially etched using the photoresist pattern 13 as a mask, but disappears on the way, and is eventually etched using the SOG film 7 as a mask. FIG. 17D shows a cross-sectional view at this stage.

The etching conditions of the SOG film 7 are, for example, pressure = 20 [mTorr], input power = 1000 [W],
Etching gas = CF ₄ (60 [sccm]) / O
₂ (10 [sccm]) mixed gas.

On the other hand, the etching conditions of the Low-k film 17 are, for example, pressure = 40 [mTorr], input power = 50.
0 [W], etching gas = N ₂ (150 [scc
m]) / O ₂ (10 [sccm]).
Under this condition, the Low-k film 17 with respect to the SOG film 7
Etching selectivity and SOG for SiO ₂ film 2
The etching selectivity of the film 7 is as extremely high as 100 or more.

Next, as shown in FIG. 18E, after a barrier metal film or a metal film to be the liner film 14 and the wiring 15 is deposited on the entire surface, an unnecessary barrier metal film outside the wiring groove is formed by the CMP method. Alternatively, the liner film 14, the metal film, and the SOG film 7 are removed, the wiring 15 is formed, and the surface is flattened. After that, the SOG film 7 is formed again on the entire surface. Note that the wiring formation may be terminated here without forming the aerial wiring described in the following steps.

Next, as shown in FIG.
After making a hole in a part of the SOG film 7 on the k film 17, the low-k film 17 is removed by an O ₂ asher to form an aerial wiring. Since the upper wiring 15 is an aerial wiring as described above, a signal transmission delay due to a parasitic capacitance between wirings can be more effectively suppressed.

FIGS. 19 and 20 show a first modification of this embodiment, FIG. 21 shows a second modification of this embodiment, FIG. 22 shows a third modification of this embodiment, and FIG. 4th form
Are shown below. The first to fourth modified examples of the present embodiment respectively correspond to the first to fourth modified examples of the first embodiment. In these modifications as well, FIG.
The wiring formation may be completed in a step corresponding to the step 8 (e). In addition, various modifications similar to the first embodiment are possible.

(Fourth Embodiment) FIGS. 24 and 25
FIG. 9 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention. This embodiment is an example in which all of the wiring structures in the same layer have an aerial wiring structure.

First, FIG. 1A to FIG. 3 of the first embodiment
The steps up to (h) are performed (FIG. 24A). Where S
A low dielectric constant film 18 is used instead of the iO ₂ film 2. As the material of the low dielectric constant film 18, the same material as the material of the low dielectric constant film 17 can be used.

Next, as shown in FIG. 24B, a low dielectric constant film 17 is formed on the entire surface.

Next, as shown in FIG. 24C, an SOG film 7 and a resist pattern 13 are formed on the low dielectric constant film 17.

Next, the SOG film 7 is anisotropically etched using the photoresist pattern 13 as a mask, the pattern of the photoresist pattern 13 is transferred to the SOG film 7, and subsequently the photoresist pattern 13 and the SOG film 7 are used as a mask. To etch the Low-k film 17,
A wiring groove is formed in the film 17.

The low-k film 17 is initially etched using the photoresist pattern 13 as a mask, but disappears on the way, and is eventually etched using the SOG film 7 as a mask. A cross-sectional view at this stage is shown in FIG. SOG film 7 and Low-k film 17
Are the same as those of the third embodiment.

Next, as shown in FIG. 25E, after a barrier metal film or a metal film to be the liner film 14 and the wiring 15 is deposited on the entire surface, an unnecessary barrier metal film outside the wiring groove is formed by the CMP method. Alternatively, the liner film 14 and the metal film are removed, the wiring 15 is formed, and the surface is flattened. The SOG film 7 may be formed again on the entire surface as shown in FIG. 18E of the third embodiment.

Next, as shown in FIG.
After making a hole in a part of the SOG film 7 on the k film 17, the low-k films 17 and 18 are removed by an O ₂ asher to form an aerial wiring. Since the entire wiring structure in the same layer has an aerial wiring structure in this manner, it is possible to more effectively suppress signal transmission delay due to parasitic capacitance between wirings.

FIGS. 26 and 27 show a first modification of this embodiment, FIG. 28 shows a second modification of this embodiment, FIG. 29 shows a third modification of this embodiment, and FIG. 4th form
Are shown below. The first to fourth modified examples of the present embodiment respectively correspond to the first to fourth modified examples of the first embodiment. In addition, various modifications similar to the first embodiment are possible.

(Fifth Embodiment) FIGS. 31 to 33 are process sectional views showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

First, as shown in FIG. 31A, an Al film 19 is formed on a silicon substrate 1. Next, a TEOS oxide film 2 is formed on the Al film 19 as a hard mask for the Al film 19.
0 is formed. Next, the anti-reflection film 4 is formed on the TEOS film 20,
A resist pattern 5 is formed sequentially.

Next, as shown in FIG. 31 (b), using the photoresist pattern 5 as a mask,
The S film 20 is etched, and the photoresist pattern 5 is transferred to these films 20 and 4.

The etching conditions for the anti-reflection film 4 are, for example, pressure = 50 [mTorr], input power = 1000.
[W], etching gas = CF ₄ (50 [sccm])
/ O ₂ (10 [sccm]) mixed gas.

On the other hand, the etching conditions of the TEOS film 20 are, for example, pressure = 50 [mTorr], input power = 10
00 [W], etching gas = C ₄ F ₈ (10 [scc]
m]) / CO (100 [sccm]) / Ar (100
[Sccm]).

[0094] Next, as shown in FIG. 31 (c), the O ₂ asher photoresist pattern 5, the antireflection film 4
After removing the Al film 1 using the TEOS film 20 as a mask,
9 is anisotropically etched to form an Al plug 19.

The etching conditions of the Al film 19 are, for example, pressure = 4 [mTorr], input power = 500 [W], etching gas = Cl (75 [sccm]) / O ₂ (10
[Sccm]).

Under these conditions, the etching selectivity of the Al film 19 with respect to the TEOS oxide film 20 becomes very high, about 50, so that the TEOS oxide film 20 becomes a sufficient etching mask.

Next, as shown in FIG. 32D, the space between the Al plugs 19 is filled with a TEOS oxide film 21 to flatten the surface.

Next, as shown in FIG. 32E, after forming the anti-reflection film 22 on the entire surface, a resist pattern 23 is formed on the anti-reflection film 22.

Next, as shown in FIG. 32 (f), using the resist pattern 23 as a mask, the anti-reflection film 22 and TE
The OS oxide film 21 is etched to form a wiring groove.

The etching conditions for the anti-reflection film 22 are, for example, pressure = 50 [mTorr], input power = 1000.
[W], etching gas = CF ₄ (50 [sccm])
/ O ₂ (10 [sccm]) mixed gas.

The etching conditions for the TEOS oxide film 21 are as follows:
For example, pressure = 50 [mTorr], input power = 1000
[W], etching gas = C ₄ F ₈ (10 [scc]
m]) / CO (100 [sccm]) / Ar (100
[Sccm]).

Next, as shown in FIG. 32 (g), after removing the antireflection film 22 and the TEOS oxide film 21, an Al film is deposited and an Al film is subjected to CMP (damascene process) to form an Al wiring 24. I do. A part of the Al wiring 24 is A
It is composed of an l plug 19.

Next, as shown in FIG. 33 (h), after depositing an SiO ₂ film 25 as an interlayer insulating film on the entire surface,
An antireflection film 12 and a photoresist pattern 13 are sequentially formed. Instead of the SiO ₂ film 25, another insulating film such as a TEOS oxide film may be used.

Next, as shown in FIG. 33 (i), using the photoresist pattern 13 as a mask,
The iO ₂ film 25 is etched to form a wiring groove.

[0105] Next, as shown in FIG. 33 (j), O ₂ asher anti-reflection film 12, a photoresist pattern 1
3 is removed, and the Al wiring 26 is formed by a damascene process.
To form

As described above, according to the present embodiment, it is possible to obtain a wiring layer in which Al wiring structures (Al plug + Al wiring) having different wiring heights are alternately formed. The same effect as in the embodiment can be obtained.

In this embodiment, SiO 2 is used as the interlayer insulating film.
_{Although the two} films (silicon oxide films) 2 are used, a Low-k film, an organic silicon oxide film, or an inorganic silicon oxide film may be used instead.

In the present embodiment, Al is used as the wiring material, but Al—Cu or Al—Si—Cu, Ag, A
Other wiring materials such as u may be used.

In this embodiment, a TEOS oxide film is used as a hard mask for the Al film 19, but a silicon nitride film or an insulating film containing silicon, nitrogen and oxygen (Si
Another insulating film such as an ON film may be used.

In this embodiment, the barrier metal film,
Although a liner film is not used, it may be used if necessary. As the barrier metal film and the liner film, for example, the first
The one described in the embodiment is used.

FIGS. 34 and 35 show a first modification of this embodiment, FIG. 36 shows a second modification of this embodiment, FIG. 37 shows a third modification of this embodiment, and FIG. 4th form
Are shown below. The first to fourth modified examples of the present embodiment respectively correspond to the first to fourth modified examples of the first embodiment. In addition, various modifications similar to the first embodiment are possible. For example, here, a conductive region such as a diffusion layer having a base formed on a substrate surface has been described, but a metal wiring layer formed on a silicon substrate may be a base.

(Sixth Embodiment) FIGS. 39 and 40
FIG. 19 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the sixth embodiment of the present invention.

First, the steps of FIGS. 31 (a) to 32 (g) of the fifth embodiment are performed (FIG. 39 (a)).

Next, as shown in FIG. 10B, an organic silicon oxide film 16 as an interlayer insulating film is deposited on the entire surface.

Thereafter, FIG. 3 (j) to FIG.
The steps up to FIG. 4 (m) are performed (FIGS. 10 (c) to 11).
(F)).

According to the present embodiment, since the organic silicon oxide film 16 is used as the interlayer insulating film, the parasitic capacitance between wirings can be further reduced as compared with the fifth embodiment. In addition. In the present embodiment, the organic silicon oxide film 16 is used, but a low dielectric constant film such as a Low-k film or an inorganic silicon oxide film may be used instead.

Further, similarly to the second embodiment, the first and second insulating films may be any combination of a low-k film, an inorganic silicon oxide film, and an organic silicon oxide film, which are different from each other. .

FIG. 41 shows a first modification of the present embodiment, and FIG.
2 shows a second modification of this embodiment, FIG. 43 shows a third modification of this embodiment, and FIG. 44 shows a fourth modification of this embodiment. The first to fourth modified examples of the present embodiment respectively correspond to the first to fourth modified examples of the first embodiment. In addition, various modifications similar to the fifth embodiment are possible.

(Seventh Embodiment) FIGS. 45 and 46
FIG. 19 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the sixth embodiment of the present invention.

First, the steps of FIGS. 31A to 32G of the fifth embodiment are performed (FIG. 45A).

Next, as shown in FIG.
A k film 17 is formed on the entire surface. The material of the Low-k film 17 is a CF-based material such as flare or silk. In addition, the same effect can be obtained with resist, C alone or C-based such as C and an additive (excluding Si).

Next, as shown in FIG.
SOG film 7 having a thickness of 100 nm and a thickness of 300 on k film 17
A photoresist pattern 13 of nm is sequentially formed.

Next, the SOG film 7 is anisotropically etched using the photoresist pattern 13 as a mask, the pattern of the photoresist pattern 13 is transferred to the SOG film 7, and subsequently the photoresist pattern 13 and the SOG film 7 are used as a mask. To etch the Low-k film 17,
A wiring groove is formed in the film 17.

The low-k film 17 is initially etched using the photoresist pattern 13 as a mask, but disappears on the way, and is eventually etched using the SOG film 7 as a mask. A cross-sectional view at this stage is shown in FIG.

The etching conditions of the SOG film 7 are, for example, pressure = 20 [mTorr], input power = 1000 [W],
Etching gas = CF ₄ (60 [sccm]) / O
₂ (10 [sccm]) mixed gas.

On the other hand, the etching conditions for the Low-k film 17 are, for example, pressure = 40 [mTorr], input power = 50.
0 [W], etching gas = N ₂ (150 [scc
m]) / O ₂ (10 [sccm]).
Under this condition, the Low-k film 17 with respect to the SOG film 7
Etching selectivity and SOG for SiO ₂ film 2
The etching selectivity of the film 7 is as extremely high as 100 or more.

Next, as shown in FIG. 46 (e), after an Al film is deposited on the entire surface so as to fill the wiring groove, an unnecessary Al film outside the wiring groove is removed by a CMP method. And flatten the surface. afterwards,
The SOG film 7 is formed again on the entire surface. Note that the wiring formation may be terminated here without forming the aerial wiring described in the following steps.

Next, as shown in FIG.
After making a hole in a part of the SOG film 7 on the k film 17, the low-k film 17 is removed by an O ₂ asher to form an aerial wiring. Since the upper Al wiring 26 is an aerial wiring in this way, it is possible to more effectively suppress signal transmission delay due to parasitic capacitance between wirings.

FIGS. 47 and 48 show a first modification of this embodiment, FIG. 49 shows a second modification of this embodiment, FIG. 50 shows a third modification of this embodiment, and FIG. 4th form
Are shown below. The first to fourth modified examples of the present embodiment respectively correspond to the first to fourth modified examples of the first embodiment. In these modifications as well, FIG.
The wiring formation may be completed in a step corresponding to the step 6 (e). In addition, various modifications similar to the fifth embodiment are possible.

(Eighth Embodiment) FIGS. 52 and 53
FIG. 14 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the eighth embodiment of the present invention.

First, the steps from FIG. 31A to FIG. 32G of the fifth embodiment are performed (FIG. 52A). However, the low dielectric constant film 18 is used instead of the TEOS oxide film 21.

Next, as shown in FIG. 52B, a low dielectric constant film 17 is formed on the entire surface.

Next, as shown in FIG. 52C, an SOG film 7 and a resist pattern 13 are formed on the low dielectric constant film 17.

Next, the SOG film 7 is anisotropically etched using the photoresist pattern 13 as a mask, the pattern of the photoresist pattern 13 is transferred to the SOG film 7, and subsequently the photoresist pattern 13 and the SOG film 7 are used as a mask. To etch the Low-k film 17,
A wiring groove is formed in the film 17.

The low-k film 17 is initially etched using the photoresist pattern 13 as a mask, but disappears on the way, and is eventually etched using the SOG film 7 as a mask. FIG. 52D shows a cross-sectional view at this stage. SOG film 7 and Low-k film 17
Are the same as those of the third embodiment.

Next, as shown in FIG. 53 (e), after depositing an Al film on the entire surface, unnecessary Al films outside the wiring trenches are removed by a CMP method to form an Al wiring 26.
Flatten the surface. FIG. 18 of the third embodiment.
As shown in (e), the SOG film 7 may be formed again on the entire surface.

Next, as shown in FIG.
After making a hole in a part of the SOG film 7 on the k film 17, the low-k films 17 and 9 are removed by an O ₂ asher to form an aerial wiring. Since the entire wiring structure in the same layer has an aerial wiring structure in this manner, it is possible to more effectively suppress signal transmission delay due to parasitic capacitance between wirings.

FIGS. 54 and 55 show a first modification of this embodiment, FIG. 56 shows a second modification of this embodiment, FIG. 57 shows a third modification of this embodiment, and FIG. 4th form
Are shown below. The first to fourth modified examples of the present embodiment respectively correspond to the first to fourth modified examples of the first embodiment. In addition, various modifications similar to the fifth embodiment are possible.

(Ninth Embodiment) FIG. 59 is a sectional view showing a semiconductor device according to a ninth embodiment of the present invention.

FIG. 59A shows a portion (bit line) of a self-aligned contact (SAC) formed by a known method. In the figure, 29 is a gate insulating film, 30 is a polysilicon film constituting a polycide gate, 31 is a tungsten silicide film constituting a polycide gate, 32 is a silicon nitride film, and 33 is an etching selectivity with the silicon nitride film. An interlayer insulating film (for example, a BPSG film) and 34 indicate plugs, respectively. Here, a polycide gate is used, but another gate structure such as a polymetal gate may be used. The three polycide gates (element regions) in the figure are not on the same straight line, and two adjacent polycide gates are formed at a pitch shifted from each other by F (design rule).

FIG. 59B shows a portion of a wiring layer formed by the method according to the first embodiment.
3 corresponds to the SiO ₂ film 2, a plug or plug / wiring 35 made of a polysilicon film corresponds to the plug or plug / wiring 10, and the TEOS oxide film 36 is an SiO ₂ film 11
, And the wiring 37 corresponds to the wiring 15. The material of the plug or plug / wiring 35 is W, WSi, Al,
Other pure metals such as Al-Cu, Al-Si-Cu, Cu, Ag, and Au, silicides, or alloys may be used. It is appropriately selected according to a barrier metal film or a liner film (not shown), a plug or a plug / wiring 35. For example, when the material of the plug or the plug / wiring 35 is Cu, the barrier metal film or the liner film is made of, for example, T
An i film, a Ti / TiN film, a TiN film, a TaN film, and a Ta film are used. In the case of Al, for example, an Nb film or an NbN film may be used.

In the present embodiment, the antireflection film 12 in the step corresponding to the step of FIG.
Etching conditions are, for example, pressure = 50 [mTorr]
r], input power = 1000 [W], etching gas = C
F ₄ (50 [sccm]) / O ₂ (10 [sccm])
Is a mixed gas. The etching conditions for the TEOS oxide film 36 are, for example, pressure = 50 [mTorr], input power = 1000 [W], and etching gas = C ₄ F ₈ (10
[Sccm]) / CO (100 [sccm]) / Ar
(100 [sccm]).

FIG. 60 shows a first modification of the present embodiment, and FIG.
1 shows a second modification of this embodiment, FIG. 62 shows a third modification of this embodiment, and FIGS. 63 and 64 show a fourth modification of this embodiment.
Are shown below. The first to fourth modified examples of the present embodiment respectively correspond to the first to fourth modified examples of the first embodiment. In addition, various modifications similar to those of the first embodiment can be made with respect to materials and the like.

(Tenth Embodiment) FIG. 65 is a sectional view showing a semiconductor device according to a tenth embodiment of the present invention.

The present embodiment differs from the ninth embodiment in that an organic silicon oxide film 16 is formed instead of the TEOS oxide film 36. The method for manufacturing a wiring layer using the organic silicon oxide film 16 conforms to the second embodiment. Further, similarly to the second embodiment, a first insulating film (interlayer insulating film) and a second insulating film (organic silicon oxide film 16)
May be any combination of different insulating films of a low-k film, an inorganic silicon oxide film, and an organic silicon oxide film.

FIG. 66 shows a first modification of the present embodiment, and FIG.
7 shows a second modified example of the present embodiment, FIG. 68 shows a third modified example of the present embodiment, and FIGS. 69 and 70 show a fourth modified example of the present embodiment.
Are shown below. The first to fourth modified examples of the present embodiment respectively correspond to the first to fourth modified examples of the first embodiment. In addition, various modifications of the material and the like similar to the second embodiment are possible.

(Eleventh Embodiment) FIG. 71 is a sectional view showing a semiconductor device according to an eleventh embodiment of the present invention.

The present embodiment differs from the ninth embodiment in that the higher wiring 36 is an aerial wiring. The method of manufacturing the wiring layer having such an aerial wiring conforms to that of the third embodiment.

FIG. 72 shows a first modification of the present embodiment, and FIG.
3 shows a second modification of the present embodiment, FIG. 74 shows a third modification of the present embodiment, and FIGS. 75 and 76 show a fourth modification of the present embodiment.
Are shown below. The first to fourth modified examples of the present embodiment respectively correspond to the first to fourth modified examples of the first embodiment. In addition, with respect to materials and the like, various modifications similar to those of the third embodiment are possible.

(Twelfth Embodiment) FIG. 77 is a sectional view showing a semiconductor device according to a twelfth embodiment of the present invention.

The present embodiment differs from the ninth embodiment in that the entire wiring structure is aerial wiring. The method for manufacturing a wiring layer having such an aerial wiring conforms to that of the fourth embodiment.

FIG. 78 shows a first modification of the present embodiment, and FIG.
9 shows a second modification of the present embodiment, FIG. 80 shows a third modification of the present embodiment, and FIGS. 81 and 82 show a fourth modification of the present embodiment.
Are shown below. The first to fourth modified examples of the present embodiment respectively correspond to the first to fourth modified examples of the first embodiment. In addition, various modifications similar to those of the fourth embodiment can be made with respect to materials and the like.

Note that the present invention is not limited to the above embodiment. For example, in the above embodiment, an example in which the present invention is applied to one wiring layer has been described.
It can be applied to two or more wiring layers. The present invention may be applied to, for example, only upper wiring layers, instead of being applied to all wiring layers.

In the above embodiment, a silicon substrate is used as a semiconductor substrate. However, an SOI substrate may be used to further reduce parasitic capacitance, and a SiGe substrate may be used to cope with a higher signal speed. May be used.

Furthermore, the above-described embodiment includes various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent features. For example, even if some components are deleted from all the components shown in the embodiment, if the problem described in the section of the problem to be solved by the invention can be solved, the configuration in which the components are deleted is Can be extracted as an invention. In addition, various modifications can be made without departing from the scope of the present invention.

[0156]

As described above, according to the present invention, a semiconductor device having a wiring structure capable of coping with further miniaturization and the like and a method of manufacturing the same can be realized.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing a manufacturing method of the manufacturing method of the semiconductor device following FIG. 1;

3 is a process sectional view illustrating the manufacturing method of the semiconductor device, following FIG. 2;

FIG. 4 is a process sectional view illustrating the manufacturing method of the manufacturing method of the semiconductor device, following FIG. 3;

FIG. 5 is a process cross-sectional view showing a first modification of the first embodiment.

FIG. 6 is a process sectional view showing the modified example following FIG. 5;

FIG. 7 is a process cross-sectional view showing a second modification of the first embodiment.

FIG. 8 is a process sectional view showing a third modification of the first embodiment;

FIG. 9 is a process sectional view showing a fourth modification of the first embodiment;

FIG. 10 is a process cross-sectional view illustrating the method of manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a process sectional view illustrating the manufacturing method of the manufacturing method of the semiconductor device, following FIG. 10;

FIG. 12 is a process cross-sectional view showing a first modification of the second embodiment.

FIG. 13 is a process cross-sectional view showing the same modified example following FIG. 12;

FIG. 14 is a process cross-sectional view showing a second modification of the second embodiment.

FIG. 15 is a process cross-sectional view showing a third modification of the second embodiment.

FIG. 16 is a process sectional view showing a fourth modification of the second embodiment;

FIG. 17 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 18 is a process sectional view illustrating the method of manufacturing the semiconductor device, following FIG. 17;

FIG. 19 is a process sectional view showing a first modification of the third embodiment;

FIG. 20 is a process cross-sectional view showing the same modified example following FIG. 19;

FIG. 21 is a process cross-sectional view showing a second modification of the third embodiment.

FIG. 22 is a process cross-sectional view showing a third modification of the third embodiment.

FIG. 23 is a process cross-sectional view showing a third modification of the fourth embodiment.

FIG. 24 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 25 is a process sectional view illustrating the method of manufacturing the semiconductor device, following FIG. 24;

FIG. 26 is a process sectional view showing a first modification of the fourth embodiment;

FIG. 27 is a process cross-sectional view showing the same modified example following FIG. 26;

FIG. 28 is a process sectional view showing a second modification of the fourth embodiment;

FIG. 29 is a process cross-sectional view showing a third modification of the fourth embodiment;

FIG. 30 is a process cross-sectional view showing a fourth modification of the fourth embodiment;

FIG. 31 is a process sectional view illustrating the method of manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 32 is a process sectional view illustrating the method of manufacturing the semiconductor device, following FIG. 31;

FIG. 33 is a process sectional view illustrating the method of manufacturing the same semiconductor device, following FIG. 32;

FIG. 34 is a process sectional view showing a first modified example of the fifth embodiment;

FIG. 35 is a process sectional view showing the same modified example following FIG. 34;

FIG. 36 is a process cross-sectional view showing a second modification of the fifth embodiment;

FIG. 37 is a process cross-sectional view showing a third modification of the fifth embodiment;

FIG. 38 is a process cross-sectional view showing a fourth modification of the fifth embodiment;

FIG. 39 is a process cross-sectional view showing the method for manufacturing the semiconductor device according to the sixth embodiment of the present invention;

40 is a process sectional view illustrating the method of manufacturing the semiconductor device, following FIG. 39;

FIG. 41 is a process sectional view showing a first modification of the sixth embodiment;

FIG. 42 is a process sectional view showing a second modification of the sixth embodiment;

FIG. 43 is a process sectional view showing a third modification of the sixth embodiment;

FIG. 44 is a process sectional view showing a fourth modification of the sixth embodiment;

FIG. 45 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the seventh embodiment of the present invention;

46 is a process sectional view illustrating the method of manufacturing the semiconductor device, following FIG. 45;

FIG. 47 is a process sectional view showing a first modification of the seventh embodiment;

FIG. 48 is a process sectional view showing the same modified example following FIG. 47;

FIG. 49 is a process sectional view showing a second modification of the seventh embodiment;

FIG. 50 is a process sectional view showing a third modification of the seventh embodiment;

FIG. 51 is a process sectional view showing a fourth modification of the seventh embodiment;

FIG. 52 is a process sectional view showing the method of manufacturing the semiconductor device according to the eighth embodiment of the present invention;

FIG. 53 is a process sectional view showing the method of manufacturing the same semiconductor device, following FIG. 52;

FIG. 54 is a sectional view showing a first modification of the eighth embodiment;

FIG. 55 is a sectional view showing the modification example following FIG. 54;

FIG. 56 is a sectional view showing a second modification of the eighth embodiment;

FIG. 57 is a sectional view showing a third modification of the eighth embodiment;

FIG. 58 is a sectional view showing a fourth modification of the eighth embodiment;

FIG. 59 is a sectional view showing a semiconductor device according to a ninth embodiment of the present invention;

FIG. 60 is a sectional view showing a first modification of the ninth embodiment;

FIG. 61 is a sectional view showing a second modification of the ninth embodiment;

FIG. 62 is a sectional view showing a third modification of the ninth embodiment;

FIG. 63 is a sectional view showing a fourth modification of the ninth embodiment;

FIG. 64 is a sectional view showing a fourth modification of the ninth embodiment;

FIG. 65 is a sectional view showing a semiconductor device according to a tenth embodiment of the present invention;

FIG. 66 is a sectional view showing a first modification of the tenth embodiment;

FIG. 67 is a sectional view showing a second modification of the tenth embodiment;

FIG. 68 is a sectional view showing a third modification of the tenth embodiment;

FIG. 69 is a sectional view showing a fourth modification of the tenth embodiment;

FIG. 70 is a sectional view showing a fourth modification of the tenth embodiment;

FIG. 71 is a sectional view showing a semiconductor device according to an eleventh embodiment of the present invention;

FIG. 72 is a sectional view showing a first modification of the eleventh embodiment;

FIG. 73 is a sectional view showing a second modification of the eleventh embodiment;

FIG. 74 is a sectional view showing a third modification of the eleventh embodiment;

FIG. 75 is a sectional view showing a fourth modification of the eleventh embodiment;

FIG. 76 is a sectional view showing a fourth modification of the eleventh embodiment;

FIG. 77 is a sectional view showing a semiconductor device according to a twelfth embodiment of the present invention;

FIG. 78 is a sectional view showing a first modification of the twelfth embodiment;

FIG. 79 is a sectional view showing a second modification of the twelfth embodiment;

FIG. 80 is a sectional view showing a third modification of the twelfth embodiment;

FIG. 81 is a sectional view showing a fourth modification of the twelfth embodiment;

FIG. 82 is a sectional view showing a fourth modification of the twelfth embodiment;

FIG. 83 is a diagram showing a configuration of a magnetron RIE device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 SiO ₂ film (first insulating film) 3 polysilicon film 4 antireflection film 5 photoresist pattern 6 resist 7 SOG film 8 resist pattern 9 barrier metal film or liner film 10 ... plug or plug wire 11 ... SiO ₂ film (second insulating film) 12 ... antireflection film 13 ... photo-resist pattern 14 ... barrier metal film 15 ... wire 16 ... organic silicon oxide film (second insulating film) 17 ... Low-k film (second insulating film) 18 ... Low-k film (first insulating film) 19 ... Al film (Al plug) 20 ... SiO ₂ film 21 ... SiO ₂ film 22 ... antireflection film 23 ... resist pattern 24 ... Al wiring 25 ... SiO ₂ film (second insulating film) 26 ... Al wires 29 gate insulating film 30 ... polysilicon film 31 ... tungsten silicide film 2 ... silicon nitride film 33 ... interlayer insulating film 34 ... Plug 35 ... plug or plug wire 36 ... TEOS oxide film 37 ... wire

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) H01L 27/04 DF Term (Reference) 4M104 AA01 AA03 AA09 BB01 BB02 BB04 BB14 BB17 BB30 BB32 BB36 CC01 DD02 DD08 DD15 DD16 DD17 DD18 DD19 DD20 DD75 EE08 EE12 EE14 EE15 EE17 EE18 FF00 FF13 FF14 FF17 FF18 FF22 GG13 HH14 HH20 5F004 AA04 BA04 CA01 CA02 DA01 DA04 DA21 DA25 DA26 DB00 DB02 DB03 DB26 EA03 H01 H03 H03 H01 H03 H03 H03 H03 H03 H03 GG HH21 HH28 HH32 HH33 JJ01 JJ07 JJ08 JJ09 JJ11 JJ13 JJ14 JJ18 JJ19 JJ21 JJ28 JJ32 JJ33 KK01 KK07 KK08 KK09 KK11 KK13 KK14 KK18 KK19 KK21 KK28 KK32 KK33 MM01 MM02 MM07 MM12 MM13 MM28 MM29 NN06 NN07 NN40 QQ04 QQ08 QQ09 QQ13 QQ16 QQ24 QQ25 QQ27 QQ28 QQ37 QQ48 RR00 RR01 RR02 RR04 RR06 RR08 RR09 RR15 RR21 RR22 RR25 SS04 TT04 WW01 XX03 XX15 XX24 XX25 XX27 5F038 CD09 CD13 CD18 EZ15 EZ20

Claims (19)

[Claims] 1. A wiring layer including a semiconductor substrate and first and second wiring structures formed on the semiconductor substrate, wherein the first wiring structure is a first wiring structure.
And a first wiring formed thereon,
The second wiring structure includes a second plug and a second wiring formed thereon, and an upper surface of the first wiring is higher than an upper surface of the second wiring; A semiconductor device having a lower surface having the same height as the upper surface of the second wiring or a wiring layer formed lower than the upper surface of the second wiring. 2. The semiconductor device according to claim 1, wherein said wiring layer is a single-layer or multi-layer wiring layer, and said first and second wiring structures are formed in the same wiring layer. 13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein said first and second plugs and said first and second wirings are surrounded by an insulating film. 4. The insulating film includes a first insulating film and a second insulating film formed thereon, wherein the first plug, the second plug and the second plug are formed on the first insulating film. 4. The semiconductor device according to claim 3, wherein two wirings are buried and the second wiring is buried in the second insulating film. 5. The semiconductor device according to claim 4, wherein said first and second insulating films are different types of insulating films. 6. The semiconductor device according to claim 5, wherein each of said first and second insulating films is a low dielectric constant film, an organic insulating film, or an inorganic insulating film. 7. The device according to claim 1, wherein the first and second plugs and the periphery of the first wiring are insulating films, and the periphery of the second wiring is a cavity. Semiconductor device. 8. The semiconductor device according to claim 1, wherein said first and second plugs and said first and second wirings are hollow. 9. The wiring cross-sectional area of the first wiring is equal to that of the second wiring.
9. The semiconductor device according to claim 1, wherein the wiring is larger than a wiring cross-sectional area of the wiring. 10. The semiconductor device according to claim 1, wherein a wiring width of said first wiring is wider than a wiring width of said second wiring. 11. The size of the first wiring in the wiring thickness direction is:
9. The semiconductor device according to claim 1, wherein the size of the second interconnect is larger than a dimension in a thickness direction of the second interconnect. 9. 12. The distance between the first wiring and the second wiring in the wiring width direction is larger than 0 μm and 0.13 μm.
The semiconductor device according to claim 1, wherein: 13. 1 <L2 / L1 ≦ 13 (L1 is the first
Distance between the second wiring and the second wiring [μ]
9. The semiconductor device according to claim 1, wherein m] and L2 satisfy an inequality of a wiring width [μm] of the first wiring. 14. L ≦ L2 / L3 ≦ 10 (L3 is the first
Of the first plug in the width direction of the wiring [μ]
m] and L2 are inequalities of the wiring width [μm] of the first wiring, and 1 ≦ L5 / L4 ≦ 10 (L4 is the dimension [μm of the second plug in the wiring width direction of the second wiring). 9. The semiconductor device according to claim 1, wherein L5 satisfies an inequality of a wiring width [μm] of the second wiring. 15. The semiconductor device according to claim 1, wherein a material of said first wiring and a material of said second wiring are different from each other. 16. A step of forming a first insulating film on a semiconductor substrate; etching the first insulating film; forming a first wiring groove on a surface of the first insulating film; Forming a first connection hole penetrating the first insulating film between the bottom of the groove and the semiconductor substrate, a second connection hole penetrating the first insulating film; Embedding a wiring groove, the first connection hole, and the second connection hole with a first conductive film; and a second insulating film on the first insulating film in which the first conductive film is embedded. And forming a second wiring groove in the second insulating film, which is connected to the second connection hole and is substantially parallel to the first wiring groove, by etching the second insulating film. And a step of burying the second wiring groove with a second conductive film. 17. The method according to claim 17, wherein the first wiring groove, the first connection hole,
The step of forming the second connection hole comprises: forming a first mask pattern having a first opening corresponding to the first wiring groove and a second opening corresponding to the second connection hole; A step of forming a resist on the first insulating film; a step of forming a resist on the first insulating film on which the first mask pattern is formed; a third opening corresponding to the first connection hole Forming a second mask pattern having a portion and a fourth opening corresponding to the second wiring groove on the resist,
Forming the second mask pattern by adjusting the positions of the first opening and the third opening and the positions of the second opening and the fourth opening, respectively; The resist is etched using the second mask pattern as a mask, and a fifth opening corresponding to the first connection hole and a sixth opening corresponding to the second wiring groove are formed in the resist. Removing the second mask pattern, etching the first insulating film using the resist and the first mask pattern as a mask, and forming the first and second insulating films on the first insulating film. Forming a connection hole, and after removing the resist, etching the first insulating film using the first mask pattern as a mask to form the first wiring groove. Characterized by The method of manufacturing a semiconductor device according to Motomeko 16. 18. A step of forming a first insulating film on a semiconductor substrate; etching the first insulating film; forming a first wiring groove on a surface of the first insulating film; Forming a first connection hole penetrating the first insulating film between the bottom of the groove and the semiconductor substrate, and a second connection hole penetrating the first insulating film; Embedding a wiring groove, the first connection hole, and the second connection hole with a first conductive film; and a second insulating film on the first insulating film in which the first conductive film is embedded. And forming a second wiring groove in the second insulating film, which is connected to the second connection hole and is substantially parallel to the first wiring groove, by etching the second insulating film. Filling the second wiring groove with a second conductive film; and removing the second insulating film around the second wiring. And, a method of manufacturing a semiconductor device characterized by a step of the periphery of the second wiring in the cavity. 19. A step of forming a first insulating film on a semiconductor substrate; etching the first insulating film; forming a first wiring groove on a surface of the first insulating film; Forming a first connection hole penetrating the first insulating film between the bottom of the groove and the semiconductor substrate, and a second connection hole penetrating the first insulating film; Embedding a wiring groove, the first connection hole, and the second connection hole with a first conductive film; and a second insulating film on the first insulating film in which the first conductive film is embedded. And forming a second wiring groove in the second insulating film, which is connected to the second connection hole and is substantially parallel to the first wiring groove, by etching the second insulating film. Embedding the second wiring groove with a second conductive film; the first and second plugs; And removing the second insulating film around the second wiring to form a cavity around the first and second plugs and the first and second wirings. Semiconductor device manufacturing method.