CN106952863B - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- CN106952863B CN106952863B CN201610006648.9A CN201610006648A CN106952863B CN 106952863 B CN106952863 B CN 106952863B CN 201610006648 A CN201610006648 A CN 201610006648A CN 106952863 B CN106952863 B CN 106952863B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
A method of forming a semiconductor device, comprising: providing a substrate and a dielectric layer on the substrate, wherein the substrate is internally provided with an underlying metal layer; forming a mask layer with a plurality of discrete groove pattern openings on the dielectric layer; after the mask layer on the side wall of the groove pattern opening is subjected to oxygen plasma treatment, a flat layer covering the mask layer and the groove pattern opening is formed; forming a photoresist layer with contact hole pattern openings on the flat layer, wherein at least one groove pattern opening is provided with a corresponding contact hole pattern opening; etching the dielectric layer with partial thickness by taking the photoresist layer and the mask layer as masks, and forming a contact hole in the dielectric layer; and after removing the photoresist layer and the flat layer, etching the dielectric layer by taking the mask layer as a mask until the surface of the bottom metal layer is exposed, and forming a groove in the dielectric layer. The method can avoid the phenomenon that the width of the contact hole is reduced due to the fact that the contact hole and the groove are not aligned, and the phenomenon of open circuit is avoided.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device.
Background
As semiconductor integrated circuit process technology continues to advance, high performance, high density connections between semiconductor devices require connections between interconnect structures as the semiconductor devices shrink to the deep sub-micron range. Parasitic effect is easy to occur between parasitic resistance and parasitic capacitance in an interconnection structure, so that time delay of metal connection line transmission is caused, and how to overcome the problem that RC (R refers to resistance and C refers to capacitance) delay is obviously increased due to rapid increase of connection length.
In order to overcome the parasitic effect in the interconnection, in the integrated process of the large scale integrated circuit back end process interconnection, on one hand, the parasitic capacitance is proportional to the relative dielectric constant K of the insulating medium of the interconnection layer, so that the conventional SiO is replaced by a low-K material, especially an Ultra-low dielectric constant (ULK) material2Dielectric materials have become a requirement for the development of high speed chips, and on the other hand, copper has a lower resistivity, superior electromigration resistance and high reliability, which can lower the interconnect resistance of the metal and thus reduce the overall interconnectThe delay effect has now changed from conventional aluminum interconnects to low resistance copper interconnects.
However, the electrical performance of the semiconductor devices formed by the prior art still remains to be improved.
Disclosure of Invention
The invention solves the problem of avoiding the width reduction of the contact hole caused by the position misalignment of the contact hole and the groove, thereby avoiding the phenomenon of circuit breaking of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate and a dielectric layer positioned on the substrate, wherein a bottom metal layer is formed in the substrate; forming a mask layer on the dielectric layer, wherein the mask layer is provided with a plurality of separately arranged groove pattern openings; carrying out oxygen plasma treatment on the mask layer on the side wall of the groove pattern opening to form a flat layer covering the mask layer and the groove pattern opening; forming a photoresist layer with contact hole pattern openings on the flat layer, wherein at least one groove pattern opening is provided with a corresponding contact hole pattern opening; etching a dielectric layer with partial thickness by taking the photoresist layer and the mask layer as masks, and forming a contact hole in the dielectric layer; and after removing the photoresist layer and the flat layer, etching the dielectric layer by taking the mask layer as a mask until the surface of the bottom metal layer is exposed, and forming a groove in the dielectric layer.
Optionally, the parameters of the oxygen plasma treatment are as follows: the adopted gas is oxygen, the flow of the oxygen is 10 sccm-1000 sccm, the high-frequency radio frequency power is 100W-1500W, the low-frequency radio frequency power is 0W-100W, the pressure of the chamber is 5 mtorr-200 mtorr, and the temperature is 0 ℃ to 100 ℃.
Optionally, the mask layer is made of titanium nitride or tantalum nitride.
Optionally, the process of etching the dielectric layer by using the mask layer as a mask is an anisotropic dry etching process.
Optionally, a process of etching the dielectric layer with a certain thickness by using the photoresist layer and the mask layer as masks is an anisotropic dry etching process.
Optionally, the anisotropic dry etching process is an anisotropic plasma etching process, and the parameters are as follows: the etching gas comprises C4F8、CF4And N2，C4F8The flow rate of (1) is 5sccm to 100sccm, CF4The flow rate of (1) is 5-500 sccm, N2The flow rate of the gas source is 0sccm to 1000sccm, the source radio frequency power is 100 watts to 1000 watts, the bias power is 50 watts to 500 watts, and the chamber pressure is 20mtorr to 200 mtorr.
Optionally, the dielectric layer is made of a low-K dielectric material or an ultra-low-K dielectric material.
Optionally, the material of the planarization layer is an organic coating, an anti-reflection coating or amorphous carbon.
Optionally, the bottom metal layer is made of copper or copper-aluminum alloy.
Optionally, the method further includes: and filling a conductive layer in the groove and the contact hole.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the mask layer on the side wall of the trench pattern opening is subjected to oxygen plasma treatment, so that an oxide layer is formed on the surface of the mask layer on the side wall of the trench pattern opening, and in the process of etching to form the trench and the contact hole, the oxide layer can protect the mask layer on the side wall of the trench pattern opening and reduce etching loss of the mask layer, so that the difference between the width of the finally formed trench and the initial width of the trench pattern opening is smaller, and particularly the difference between the initial widths of the trench and the trench pattern opening which are not overlapped with the contact hole is smaller. Therefore, in the process design, the process window of the trench pattern opening in the mask layer can be further enlarged, even when the center of the contact hole pattern opening is deviated relative to the central axis of the trench pattern opening, the width of the contact hole formed in the dielectric layer cannot be too small, so that after the conductive layer is filled in the contact hole and the trench in the follow-up process, the conductive layer is not difficult to fill due to the too small width of the contact hole, the phenomenon of open circuit between the conductive layer formed in the follow-up process and the bottom layer gold layer is avoided, and the performance of the semiconductor device is improved.
Drawings
Fig. 1 to 8 are schematic structural views illustrating a semiconductor device forming process in the prior art;
fig. 9 to 17 are schematic structural views illustrating a process of forming a semiconductor device according to an embodiment of the present invention;
Detailed Description
As described in the background, the electrical performance of semiconductor devices formed in the prior art is still to be improved.
Fig. 1 to 8 are schematic structural views illustrating a semiconductor device forming process in the prior art.
Referring to fig. 1, a substrate 100 and a dielectric layer 130 on the substrate are provided, wherein an underlying metal layer 110 is formed within the substrate 100. An etch stop layer 120 is also provided between the substrate 100 and the dielectric layer 130.
Referring to fig. 2, a mask layer 140 is formed on the dielectric layer 130, and the mask layer 140 has a plurality of separately arranged trench pattern openings 141 therein. Fig. 3 is a schematic perspective view of the mask layer 140. The mask layer 140 is made of titanium nitride.
Referring to fig. 4, a planarization layer 150 is formed to cover the mask layer 140 and the trench pattern opening 141 (refer to fig. 2); a photoresist layer 160 having a contact hole pattern opening 161 is formed on the planarization layer 150, and at least one trench pattern opening 141 has a corresponding contact hole pattern opening 161 thereon. Fig. 5 is a perspective view of the photoresist layer 160.
Referring to fig. 6, the photoresist layer 160 and the mask layer 140 are used as masks to etch a partial thickness of the dielectric layer 130, and a contact hole 170 is formed in the dielectric layer 130.
Referring to fig. 7, after the contact holes 170 are formed, the photoresist layer 160 (refer to fig. 6) and the planarization layer 150 (refer to fig. 6) are removed.
Referring to fig. 8, after the photoresist layer 160 and the planarization layer 150 are removed, the mask layer 140 is used as a mask to etch the dielectric layer 130 until the surface of the bottom metal layer 110 is exposed, and a trench 180 is formed in the dielectric layer 130.
Research shows that the above semiconductor device forming method can cause the width of the contact hole to be reduced due to the position of the contact hole and the position of the groove being misaligned, thereby causing the phenomenon of opening of the semiconductor device, and the reason is that:
in the process of etching a partial-thickness dielectric layer by taking the photoresist layer and the mask layer as masks and etching the dielectric layer by taking the mask layer as a mask, the mask layer is subjected to etching damage, particularly the etching damage to the mask layer on the side wall of the opening of the trench pattern increases the width of the opening of the trench pattern, so that the width of the finally formed trench is larger than the initial width of the opening of the trench pattern. I.e., the initial width of the trench pattern opening is small relative to the target width of the trench. Under the condition, when the center of the contact hole pattern opening is deviated relative to the central axis of the groove pattern opening due to the fluctuation of the process, the width of the overlapping part of the groove pattern opening and the contact hole pattern opening is smaller, so that the formed contact hole is too small in width, the difficulty of filling the conductive layer in the contact hole subsequently is higher, and the open circuit between the conductive layer and the bottom metal layer is easy to occur.
On the basis, the invention provides a method for forming a semiconductor device, wherein the mask layer on the side wall of the trench pattern opening is subjected to oxygen plasma treatment after the mask layer is formed, so that the process window of the trench pattern opening in the mask layer can be further enlarged, even when the center of the contact hole pattern opening deviates relative to the central axis of the trench pattern opening, the width of a contact hole formed in a dielectric layer is not too small, so that after a conductive layer is filled in the contact hole and the trench subsequently, the conductive layer is not difficult to fill due to the too small width of the contact hole, the phenomenon of circuit break between the subsequently formed conductive layer and a bottom layer gold layer is avoided, and the performance of the semiconductor device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 9 to 17 are schematic structural views illustrating a process of forming a semiconductor device according to an embodiment of the present invention.
Referring to fig. 9, a substrate 200 having an underlying metal layer 210 formed therein and a dielectric layer 230 on the substrate 200 are provided.
The base 200 includes a semiconductor substrate and a metal dielectric layer (not shown) on the semiconductor substrate, and the bottom metal layer 210 is located in the metal dielectric layer.
The semiconductor substrate can also be provided with a semiconductor structure, and the semiconductor structure is a PMOS transistor, an NMOS transistor, a CMOS transistor, a capacitor, a resistor or an inductor.
The bottom metal layer 210 is used to connect with the semiconductor structure in the semiconductor substrate and the conductive layer to be formed. The bottom metal layer 210 is made of a conductive material such as copper or copper-aluminum alloy.
The dielectric layer 230 is made of a low-K dielectric material (the low-K dielectric material refers to a dielectric material with a relative dielectric constant of 2.6 or more and less than 3.9) or an ultra-low-K dielectric material (the ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant of less than 2.6). When the dielectric layer 230 is made of a low-K dielectric material or an ultra-low-K dielectric material, the dielectric layer 230 is made of SiOH, SiCOH, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), BPSG (boron-doped silicon dioxide), hydrogen silsesquioxane (HSQ, (HSiO) or a mixture thereof1.5)n) Or methylsilsesquioxane (MSQ, (CH)3SiO1.5)n). In this embodiment, the dielectric layer 230 is made of an ultra-low K dielectric material, and the ultra-low K dielectric material is SiCOH.
In this embodiment, an etching stop layer 220 is further formed between the substrate 200 and the dielectric layer 230, and the etching rate of the etching stop layer 220 in the subsequent etching process is much lower than that of the dielectric layer 230, so as to stop etching and prevent the substrate 200 from being over-etched by the etching process.
Referring to fig. 10, a mask layer 240 is formed on the dielectric layer 230, and the mask layer 240 has a plurality of trench pattern openings 241 arranged separately therein.
Fig. 11 is a schematic perspective view of the mask layer 240, where the mask layer 240 has a single-layer structure or a stacked-layer structure, and the mask layer 240 is made of titanium nitride or tantalum nitride. The mask layer 240 has a plurality of separately arranged trench pattern openings 241, and the trench pattern openings 241 define the position and shape of a subsequently formed trench. In this embodiment, the number of the trench pattern openings 241 is two as an example, and in an actual process, the number of the trench pattern openings 241 may be designed according to specific situations.
Referring to fig. 12, the mask layer 240 at the sidewall of the trench pattern opening 241 is subjected to oxygen plasma treatment.
The gas adopted by the oxygen plasma treatment comprises oxygen, the oxygen is converted into oxygen plasma by plasma in the oxygen plasma treatment process, the oxygen plasma bombards the side wall and the bottom of the trench pattern opening 241 at a certain temperature, so that the surface of the mask layer 240 on the side wall of the trench pattern opening 241 is oxidized, an oxide layer (not shown) is formed on the surface of the mask layer 240 on the side wall of the trench pattern opening 241, and specifically, when the mask layer 240 is made of titanium nitride, the oxide layer formed on the surface of the mask layer 240 on the side wall of the trench pattern opening 241 by the oxygen plasma treatment is made of titanium oxide; when the material of the mask layer 240 is tantalum nitride, the material of the oxide layer formed on the surface of the mask layer 240 on the sidewall of the trench pattern opening 241 after the oxygen plasma treatment is tantalum oxide. The oxide layer may protect the mask layer 240 and reduce etching damage to the mask layer 240 on the sidewall of the trench pattern opening 241 in a subsequent etching process.
If the flow rate of the oxygen is less than 10sccm, the density of the oxygen plasma is reduced, which results in too low efficiency of the oxygen plasma treatment, and if the flow rate of the oxygen is greater than 1000sccm, the process is wasted. Therefore, in this embodiment, the flow rate of the oxygen plasma treatment is 10sccm to 1000 sccm.
If the temperature of the oxygen plasma treatment is lower than 0 ℃, the energy of the oxygen plasma is low, the oxygen plasma has weak bombardment on the surface of the mask layer 240 on the side wall of the trench pattern opening 241, so that titanium atoms or tantalum atoms and oxygen atoms on the surface of the mask layer 240 on the side wall of the trench pattern opening 241 are difficult to combine, and if the temperature of the oxygen plasma treatment is higher than 100 ℃, the semiconductor structure in the substrate 200 is easily damaged. Therefore, in this embodiment, the temperature of the oxygen plasma treatment is selected to be 0 to 100 ℃.
The high-frequency radio frequency power of the oxygen plasma treatment enables the oxygen to be in a plasma state, if the high-frequency radio frequency power is lower than 100 watts, the oxygen cannot be in the plasma state, and if the high-frequency radio frequency power is higher than 1500 watts, the manufacturing cost is increased and the process condition is limited. Therefore, in this embodiment, the high frequency rf power used for the oxygen plasma treatment is 100 w to 1500 w.
The low-frequency rf power of the oxygen plasma processing generates a bias voltage, so that the oxygen plasma has a certain speed and moves to the surface of the mask layer 240 on the sidewall of the trench pattern opening 241, and under a low-frequency rf power which is relatively low, even 0, the oxygen plasma can move to each surface of the mask layer 240 by diffusion to react, and if the low-frequency rf power is higher than 100 w, the surface reaction efficiency of the mask layer 240 on the sidewall of the mask layer opening 241 is reduced, so in this embodiment, the low-frequency rf power is 0 w to 100 w.
The chamber pressure adopted in the oxygen plasma treatment is 5-200 mtorr.
Referring to fig. 13, after the oxygen plasma treatment is performed, a planarization layer 250 is formed to cover the mask layer 240 and the trench pattern opening 241 (refer to fig. 12); a photoresist layer 260 having a contact hole pattern opening 261 is formed on the planarization layer 250, and at least one trench pattern opening 241 has a corresponding contact hole pattern opening 261 thereon.
The planarization layer 250 is an organic layer made of an organic coating, an anti-reflective coating, or amorphous carbon. The process of forming the planarization layer 250 is a spin-on process or a chemical vapor deposition process.
Fig. 14 is a schematic perspective view of the photoresist layer 260, and the material of the photoresist layer 260 is photoresist. The photoresist layer 260 has a contact hole pattern opening 261 therein, and the contact hole pattern opening 261 defines the position and shape of a subsequently formed contact hole. In this embodiment, taking the number of the contact hole pattern openings 261 as an example, in an actual process, the number of the contact hole pattern openings 261 may be designed according to specific situations.
At least one of the trench pattern openings 241 has a corresponding contact hole pattern opening 261, which may be: one contact hole pattern opening 261 is located on one trench pattern opening 241, a plurality of contact hole pattern openings 261 are located on one trench pattern opening 241, and a plurality of contact hole pattern openings 261 are located on a plurality of trench pattern openings 241, each contact hole pattern opening 261 exposing a partial region of the planarization layer 250 directly above one trench pattern opening 241 for each of the above cases. In this embodiment, one contact hole pattern opening 261 is located on one trench pattern opening 241 as an example.
With the continuous decrease of the feature size, the width of the trench to be formed is smaller and smaller, and the width of the corresponding trench pattern opening 241 is smaller and smaller, and the aperture of the contact hole pattern opening 261 is generally larger than the width of the trench pattern opening 241, so that the width of the contact hole to be formed subsequently can be determined by the width of the trench pattern opening 241, the width refers to the dimension parallel to the width direction of the trench pattern opening 241, the length of the contact hole to be formed subsequently can be determined by the aperture of the contact hole pattern opening 261, the length is the dimension parallel to the surface of the substrate 200 and perpendicular to the width direction of the trench pattern opening 241, that is, the width of the contact hole to be formed subsequently utilizes the width dimension of the trench pattern opening 241 to the maximum extent, which is beneficial for filling the conductive layer in the contact hole. In other embodiments, the aperture of the contact hole pattern opening 261 may be smaller than the width of the trench pattern opening 241.
Referring to fig. 15, a partial thickness of the dielectric layer 230 is etched using the photoresist layer 260 and the mask layer 240 as masks, and a contact hole 270 is formed in the dielectric layer 230.
In this embodiment, before etching the dielectric layer 230 with a certain thickness, the method further includes the steps of: the planarization layer 250 is etched along the contact hole pattern opening 261 such that the top surface of the dielectric layer 230 is exposed.
Specifically, the dielectric layer 230 is etched to a partial thickness by an anisotropic dry etching process to form the contact hole 270, such as an anisotropic plasma etching process or a reactive ion etching process.
In this embodiment, the anisotropic plasma etching process is used to etch a portion of the dielectric layer 230 to form the contact hole 270, specifically, the etching gas includes C4F8、CF4And N2，C4F8The flow rate of (1) is 5sccm to 100sccm, CF4The flow rate of (1) is 5-500 sccm, N2The flow rate of the gas source is 0sccm to 1000sccm, the source radio frequency power is 100 watts to 1000 watts, the bias power is 50 watts to 500 watts, and the chamber pressure is 20mtorr to 200 mtorr.
After the mask layer 240 on the sidewall of the trench pattern opening 241 is subjected to oxygen plasma treatment, an oxide layer is formed on the surface of the mask layer 240 on the sidewall of the trench pattern opening 241, and the protection effect of the oxide layer on the mask layer 240 is enhanced.
Referring to fig. 16, after forming the contact hole 270, the photoresist layer 260 (refer to fig. 15) and the planarization layer 250 (refer to fig. 15) are removed.
The process of removing the photoresist layer 260 and the planarization layer 250 is a wet etching process or a dry etching process.
In the etching process for forming the contact hole 270, a part of the photoresist layer 260 is consumed, and the photoresist layer 260 and the planarization layer 250 need to be removed after the contact hole 270 is formed. In other embodiments, if the photoresist layer 260 over the dielectric layer 230 is consumed during the etching process for forming the contact hole 270, only the planarization layer 250 needs to be removed after forming the contact hole 270.
Referring to fig. 17, after removing the photoresist layer 260 and the planarization layer 250, the mask layer 240 is used as a mask to etch the dielectric layer 230 until the surface of the bottom metal layer 210 is exposed, and a trench 280 is formed in the dielectric layer 230.
Specifically, the dielectric layer 230 is etched by an anisotropic dry etching process to form the trench 280, such as an anisotropic plasma etching process or a reactive ion etching process.
In this embodiment, the dielectric layer 230 is etched using an anisotropic plasma etching process to form the trench 280, specifically, the etching gas comprises C4F8、O2And N2，C4F8The flow rate of (A) is 5sccm to 100sccm, O2The flow rate of (1) is 5sccm to 100sccm, N2The flow rate of the gas source is 0sccm to 1000sccm, the source radio frequency power is 100 watts to 1000 watts, the bias power is 50 watts to 500 watts, and the chamber pressure is 20mtorr to 200 mtorr.
In the process of forming the trench 280, the depth of the contact hole 270 is also increased, and the dielectric layer 230 and the etch stop layer 220 are etched until the surface of the underlying metal layer 210 is exposed.
Since the oxygen plasma treatment is performed on the mask layer 240 on the sidewall of the trench pattern opening 241, an oxide layer is formed on the surface of the mask layer 240 on the sidewall of the trench pattern opening 241, and the protection effect of the oxide layer on the mask layer 240 is enhanced, so that the etching damage to the mask layer 240 on the sidewall of the trench pattern opening 241 can be reduced in the process of forming the trench 280.
After the trench 280 is formed, a conductive layer (not shown) is filled in the contact hole 270 and the trench 280. The conducting layer is made of conducting materials such as copper, aluminum or tungsten. In this embodiment, the conductive layer is made of copper.
In one embodiment, the process step of forming the conductive layer comprises: forming a conductive film which fills the contact hole 270 and the trench 280 and covers the surface of the mask layer 240; the conductive film above the top surface of the dielectric layer 230 is removed to form a conductive layer filling the contact hole 270 and the trench 280, the top surface of the conductive layer being flush with the surface of the dielectric layer 230.
The trench 280 is divided into two types, one is a trench 280 having an overlapping portion with the contact hole 270 and referred to as a first trench for convenience of description, and the other is a trench 280 having no overlapping portion with the contact hole 270 and referred to as a second trench for convenience of description. The conductive layers formed in the first and second trenches are used to constitute circuit wirings, and the conductive layer formed in the contact hole 270 is used to connect the circuit wirings with the underlying metal layer 210.
In an actual process, the number of the second trenches is far greater than that of the first trenches, that is, the circuit wiring is mainly composed of the second trenches, and as the feature size is continuously reduced, the control of the width of the second trenches has an increasingly greater influence on the circuit wiring, which is represented as: if the width of the second trench formed in the process is too large with respect to the target width, short-circuiting of the circuit wiring is easily caused. It is necessary to ensure that the difference between the width of the second trench and the target width is small.
In this embodiment, since the mask layer 240 on the sidewall of the trench pattern opening 241 is subjected to the oxygen plasma treatment, in the process of forming the contact hole 270 and the trench 280, the etching damage to the mask layer 240 on the sidewall of the trench pattern opening 241 can be reduced, so that the difference between the width of the finally formed trench 280 and the initial width of the trench pattern opening 241 is small, and especially the difference between the initial widths of the second trench and the trench pattern opening 241 is small. Based on this, in the process design, in the case of ensuring that the difference between the width of the second trench and the target width is small, the process window of the trench pattern opening 241 may be further increased, that is, the initial width of the trench pattern opening 241 is small relative to the target width of the trench 280. Even when the center of the contact hole pattern opening 261 is offset with respect to the central axis of the trench pattern opening 241, the width of the contact hole 270 formed in the dielectric layer 230 is not too small, so that after the conductive layer is filled in the contact hole 270 and the trench 280, the conductive layer is not difficult to fill due to the too small width of the contact hole 270, and the phenomenon of open circuit between the subsequently formed conductive layer and the bottom metal layer 210 is avoided.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A method of forming a semiconductor device, comprising:
providing a substrate and a dielectric layer positioned on the substrate, wherein a bottom metal layer is formed in the substrate;
forming a mask layer on the dielectric layer, wherein the mask layer is provided with a plurality of separately arranged groove pattern openings;
carrying out oxygen plasma treatment on the mask layer on the side wall of the groove pattern opening to form an oxide layer on the surface of the mask layer;
forming a flat layer covering the mask layer, the oxidation layer and the groove pattern opening;
forming a photoresist layer with contact hole pattern openings on the flat layer, wherein at least one groove pattern opening is provided with a corresponding contact hole pattern opening;
etching a dielectric layer with partial thickness by taking the photoresist layer and the mask layer as masks, and forming a contact hole in the dielectric layer;
after removing the photoresist layer and the flat layer, etching the dielectric layer by taking the mask layer as a mask until the surface of the bottom metal layer is exposed, and forming a groove in the dielectric layer; the width of the overlapping part of the groove and the contact hole is the same as the width of the groove pattern opening;
when the mask layer is made of titanium nitride, the oxide layer is titanium oxide after oxygen plasma treatment; or the mask layer is made of tantalum nitride, and the oxide layer is made of tantalum oxide after oxygen plasma treatment.
2. The method of claim 1, wherein the oxygen plasma treatment parameters are: the adopted gas is oxygen, the flow of the oxygen is 10 sccm-1000 sccm, the high-frequency radio frequency power is 100W-1500W, the low-frequency radio frequency power is 0W-100W, the pressure of the chamber is 5 mtorr-200 mtorr, and the temperature is 0 ℃ to 100 ℃.
3. The method for forming a semiconductor device according to claim 1, wherein a process of etching the dielectric layer using the mask layer as a mask is an anisotropic dry etching process.
4. The method for forming a semiconductor device according to claim 1, wherein the process of etching the dielectric layer with a partial thickness by using the photoresist layer and the mask layer as masks is an anisotropic dry etching process.
5. The method of claim 4, wherein the anisotropic dry etching process is an anisotropic plasma etching process, and the parameters are as follows: the etching gas comprises C4F8、CF4And N2，C4F8The flow rate of (1) is 5sccm to 100sccm, CF4The flow rate of (1) is 5-500 sccm, N2The flow rate of the gas source is 0sccm to 1000sccm, the source radio frequency power is 100 watts to 1000 watts, the bias power is 50 watts to 500 watts, and the chamber pressure is 20mtorr to 200 mtorr.
6. The method of claim 1, wherein the dielectric layer is made of a low-K dielectric material or an ultra-low-K dielectric material.
7. The method of claim 1, wherein the material of the planarization layer is an organic coating, an anti-reflective coating, or amorphous carbon.
8. The method as claimed in claim 1, wherein the material of the bottom metal layer is copper or copper-aluminum alloy.
9. The method for forming a semiconductor device according to claim 1, further comprising: and filling a conductive layer in the groove and the contact hole.
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| CN109599359B (en) * | 2017-09-30 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN111640668B (en) * | 2019-03-01 | 2023-07-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN112885774B (en) * | 2019-11-29 | 2022-09-02 | 长鑫存储技术有限公司 | Method for forming contact hole with high depth-to-width ratio |
| CN111799179B (en) * | 2020-07-31 | 2022-03-18 | 武汉新芯集成电路制造有限公司 | Method for forming semiconductor device |
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| CN102820254A (en) * | 2011-06-07 | 2012-12-12 | 联华电子股份有限公司 | Method for manufacturing semiconductor integrated circuit |
| CN103943551A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| US8987133B2 (en) * | 2013-01-15 | 2015-03-24 | International Business Machines Corporation | Titanium oxynitride hard mask for lithographic patterning |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102820254A (en) * | 2011-06-07 | 2012-12-12 | 联华电子股份有限公司 | Method for manufacturing semiconductor integrated circuit |
| CN103943551A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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