CN113130384A - Method for forming semiconductor structure - Google Patents
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- CN113130384A CN113130384A CN202010048630.1A CN202010048630A CN113130384A CN 113130384 A CN113130384 A CN 113130384A CN 202010048630 A CN202010048630 A CN 202010048630A CN 113130384 A CN113130384 A CN 113130384A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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Abstract
A method of forming a semiconductor structure, comprising: providing a semiconductor substrate, and sequentially forming a first dielectric layer and a covering layer on the semiconductor substrate; forming a plurality of discrete first metal layers in the first dielectric layer and the covering layer, wherein the top of each first metal layer is flush with the surface of the top of the covering layer; forming a first material layer on the covering layer and the surface of the first metal layer; forming a second dielectric layer on the surface of the first material layer; etching the second dielectric layer until the surface of the first material layer is exposed to form a through hole; and carrying out chemical treatment on the exposed first material layer to form a second material layer. The forming method provided by the invention can improve the quality of the formed through hole, thereby improving the performance of the semiconductor structure.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
As the fabrication of integrated circuits advances to ultra large scale integrated circuits (ULSI), the density of the circuits inside the integrated circuits increases, and the number of devices included in the integrated circuits increases, so that the surface of the integrated circuits cannot provide enough area to fabricate the required interconnection (Interconnect). In order to meet the increased demand of interconnection lines after the shrinking of devices, the design of multi-layer metal interconnection lines with more than two layers by using through holes becomes a necessary method for the super-large-scale integrated circuit technology.
With the continuous reduction of semiconductor process nodes, metal interconnection lines in semiconductor devices are more and more dense, and the Critical Dimension (CD) of the interconnection lines is also less and less, and in order to enlarge the process window of photolithography, a self-aligned via (SAV) process may be used when forming the through holes. The quality of the via formation has a significant impact on the performance of the semiconductor device and, in the severe cases, may affect the normal operation of the semiconductor device.
However, current processes for forming vias adversely affect the performance of the semiconductor structure.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which improves the quality of a formed through hole so as to improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, and sequentially forming a first dielectric layer and a covering layer on the semiconductor substrate; forming a plurality of discrete first metal layers in the first dielectric layer and the covering layer, wherein the top of each first metal layer is flush with the surface of the top of the covering layer; forming a first material layer on the covering layer and the surface of the first metal layer; forming a second dielectric layer on the surface of the first material layer; etching the second dielectric layer until the surface of the first material layer is exposed to form a through hole; and carrying out chemical treatment on the exposed first material layer to form a second material layer.
Optionally, the chemical treatment comprises an oxidation treatment or a reduction treatment.
Optionally, when the chemical treatment is an oxidation treatment, the first material layer is boron carbide, and the second material layer is diboron trioxide.
Optionally, when the chemical treatment is a reduction treatment, the first material layer includes copper nitride or aluminum nitride.
Optionally, after forming the second material layer, the method further includes: and filling a second metal layer in the through hole to form a conductive plug connected with the first metal layer.
Optionally, after forming the second material layer, the method further includes: removing the second material layer; and filling a second metal layer in the through hole to form a conductive plug connected with the first metal layer.
Optionally, the second material layer is removed by wet cleaning, and a solution of the wet cleaning includes deionized water or a hydrofluoric acid solution.
Optionally, a protective layer is formed on the sidewall of the via prior to the oxidation treatment.
Optionally, before forming the first material layer, etching a part of the thickness of the first metal layer to make the top of the first metal layer lower than the top surface of the covering layer.
Optionally, the method for etching the second dielectric layer includes: forming a hard mask layer on the surface of the second dielectric layer; patterning the hard mask layer to form an opening, wherein the second dielectric layer on the top of the first material layer is exposed out of the opening; and etching the second dielectric layer along the opening until the surface of the first material layer is exposed.
Optionally, the material of the hard mask layer includes one or more of titanium nitride, aluminum nitride, boron nitride, or tantalum nitride.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
on one hand, when the second medium layer is etched to form a through hole, the covering layer can be protected from being damaged, so that the covering layer can keep a stable shape in the whole forming process of the through hole, and the covering layer is positioned on two sides of the first metal layer, the shape of the covering layer is fixed, so that the distance between two sides of the first metal layer can be limited, the bottom size of a subsequently formed conductive plug connected with the first metal layer is limited, and the short circuit is avoided; on the other hand, the exposed first material layer is chemically processed to form a second material layer, the first material layer is not removed by adopting a dry etching process, the damage to the first metal layer and the covering layer in the dry etching process is avoided, the quality of the interconnection structure is improved, and the performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 4 are schematic structural views illustrating a method for forming a semiconductor structure according to an embodiment;
fig. 5 to 11 are schematic structural diagrams corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention.
Detailed Description
Fig. 1 to 4 are schematic structural views illustrating a method for forming a semiconductor structure according to an embodiment.
Referring to fig. 1, a semiconductor structure is provided, which includes a first interlayer dielectric layer 100, a capping layer 110 on a surface of the first interlayer dielectric layer 100, and a first metal layer 120 in the first interlayer dielectric layer 100 and the capping layer 110, wherein a top of the first metal layer 120 is lower than a top surface of the first interlayer dielectric layer 100.
Referring to fig. 2, a barrier layer 121 and an etch stop layer 122 are sequentially formed on the surface of the first metal layer 120, and the barrier layer 121 and the etch stop layer 122 also cover the surface of the capping layer 110.
Referring to fig. 3, a second interlayer dielectric layer 130 is formed on the etching blocking layer 122, a patterned hard mask layer 140 is formed on the second interlayer dielectric layer 130, the second interlayer dielectric layer 130 is etched to the etching stop layer 122 by using the patterned hard mask layer 140 as a mask, and then the etching stop layer 122 and the blocking layer 121 are continuously etched until the surface of the first metal layer 120 is exposed, so that a through hole 150 is formed.
Referring to fig. 4, the patterned hard mask layer 140 is removed, and a second metal layer 160 is formed in the via hole 150, wherein the second metal layer 160 is connected to the first metal layer 120.
The inventor finds that, when the through hole is formed by the above method, if the opening of the patterned hard mask layer 140 is too large, the second dielectric layer 130, the etching stop layer 122 and the barrier layer 122 below the second dielectric layer 130 are easily etched too much, and even the cover layer 110 and the first metal layer 120 are damaged, on one hand, the size of the through hole formed by etching is too large, and the metal layer adjacent to the connected metal layer is easily bridged; on the other hand, damage to the capping layer 110 and the first metal layer 120 easily causes punch-through of the metal layers, which adversely affects reliability of the semiconductor structure.
In order to solve the above problems, the inventors have studied and provided a method for forming a semiconductor structure, in which a first material layer is formed on a capping layer and a first metal layer, and the capping layer and the first metal layer can be protected from damage when a via hole is formed by etching a second dielectric layer by using a high etching selectivity ratio of the first material layer to the second dielectric layer; in addition, the size of the bottom of the formed through hole can be limited, the size of the through hole is prevented from being enlarged, and the short circuit is avoided; in addition, the first material layer is chemically processed to generate the second material layer, and the first material layer is not removed by adopting a dry etching process, so that the damage of the first metal layer in the dry etching process is avoided, the first metal layer is prevented from being penetrated, and the reliability of the formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 11 are schematic structural diagrams corresponding to steps in a semiconductor structure forming method according to an embodiment of the invention.
Referring to fig. 5, a semiconductor substrate (not shown) is provided, and a first dielectric layer 200 and a capping layer 210 are sequentially formed on the semiconductor substrate.
The material of the first dielectric layer 200 is an ultra-low K dielectric material (the ultra-low K dielectric material refers to a dielectric material with a relative dielectric constant less than 2.5) or a low K dielectric material (the low K dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.5 and less than 3.9). When the first dielectric layer 200 is made of a low-K dielectric material or an ultra-low-K dielectric material, the first dielectric layer 200 is made of SiOH, SiCOH, or FSG (fluorine-doped dielectric material)Silicon dioxide), BSG (boron doped silicon dioxide), PSG (phosphorus doped silicon dioxide), BPSG (boron phosphorus doped silicon dioxide), hydrogen silsesquioxane (HSQ, (HSiO)1.5)n) Or methylsilsesquioxane (MSQ, (CH3 SiO)1.5)n)。
In this embodiment, the first dielectric layer 200 is made of an ultra-low K dielectric material, and the ultra-low K dielectric material is SiCOH. The ultra-low K dielectric material is adopted as the dielectric layer, so that the RC delay of the metal interconnection structure can be reduced.
In this embodiment, the capping layer 210 is silicon carbide; in other embodiments, the capping layer 210 may also be an oxide layer with a high K value, such as an oxide with a relative dielectric constant of about 4.
The cover layer 210 is made of an insulating material and is located between adjacent first metal layers 300 to isolate finally formed adjacent conductive plugs and prevent short circuit.
With continued reference to fig. 5, a plurality of discrete first metal layers 300 are formed within the first dielectric layer 200 and the capping layer 210, the top of the first metal layers 300 being flush with the top surface of the capping layer 210.
In this embodiment, the method for forming the first metal layer 300 includes: forming a plurality of grooves which are arranged in parallel in the covering layer 210 and the first medium layer 200 by utilizing photoetching and etching processes; the trench is then filled with a first metal material to form a first metal layer 300.
The material of the first metal layer 300 includes copper, cobalt, tungsten, or platinum. In this embodiment, the material of the first metal layer 300 is copper.
Referring to fig. 6, after the first metal layer 300 is formed, a portion of the thickness of the first metal layer 300 is etched, such that the top of the first metal layer 300 is lower than the top surface of the capping layer 210.
Since the parasitic capacitance of the metal interconnection line is inversely proportional to the distance between the two metal layers, the first metal layer 300 with a certain thickness is etched, the distance between the two interconnection metal layers is increased, the parasitic capacitance of the metal interconnection line is favorably reduced, and the RC delay is reduced.
In this embodiment, the method for etching the first metal layer 300 is dry etching.
With continued reference to fig. 6, a first material layer 400 is formed on the surface of the cap layer 210 and the first metal layer 300.
In this embodiment, the method of forming the first material layer 400 is an atomic layer deposition process.
The first material layer 400 includes boron carbide, copper nitride, or aluminum nitride.
In this embodiment, the first material layer 400 is formed to have a thickness of
In the present embodiment, the reason why the first material layer 400 is formed is that: because the first material layer 400 and the second dielectric layer have high etching selectivity, the first material layer 400 is not damaged when the second dielectric layer is etched subsequently, and because the first material layer 400 covers the surfaces of the covering layer 210 and the first metal layer 300, the covering layer 210 and the first metal layer 300 can be protected from being damaged, so that the quality of the formed metal interconnection structure is improved. Meanwhile, the covering layers 210 are prevented from being damaged, the distance between every two adjacent covering layers 210 determines the bottom size of the through hole formed subsequently, and the distance between every two adjacent covering layers 210 is kept unchanged, so that the bottom size of the through hole is limited, the through hole is prevented from being enlarged, and the possibility of short circuit is reduced.
Referring to fig. 7, a second dielectric layer 500 is formed on the surface of the first material layer 400.
In this embodiment, the method for forming the second dielectric layer 500 is a chemical vapor deposition method.
In this embodiment, the second dielectric layer 500 is an ultra-low K dielectric material.
In this embodiment, the second dielectric layer 500 is etched to form a through hole.
In this embodiment, the step of specifically forming the through hole includes:
with continued reference to fig. 7, a hard mask layer 510 is formed on the surface of the second dielectric layer 500; the hard mask layer 510 is patterned to form an opening 511, which exposes the second dielectric layer 500 on top of the first material layer 400.
In this embodiment, the position corresponding to the opening 511 is a position where a via hole is formed subsequently, and the opening 511 exposes the second dielectric layer 500 corresponding to the first metal layer 300.
In this embodiment, the hard mask layer 510 is formed by a chemical vapor deposition method; in other embodiments, the hard mask layer 510 may be formed by a physical vapor deposition method or an atomic layer deposition method.
In this embodiment, the hard mask layer 510 is made of titanium nitride; in other embodiments, the material of the hard mask layer 510 may also be one or more of aluminum nitride, boron nitride, or tantalum nitride.
Referring to fig. 8, the second dielectric layer 500 is etched along the opening 511 until the surface of the first material layer 400 is exposed, so as to form a via hole 600.
In this embodiment, the method for etching the second dielectric layer 500 is dry etching, and the process parameters of the dry etching include: the gas used comprises CHF3、C4F6、O2、Ar、C4F2And H2Wherein CHF3The gas flow rate is 10-300 sccm, C4F6The gas flow rate is 10-300 sccm and O2The gas flow rate of (A) is 0 to 100sccm, the gas flow rate of Ar is 50 to 500sccm, and C4F2The gas flow rate is 20-100 sccm and H2The gas flow of the gas is 0-100 sccm, the pressure of the chamber is 5-100 mTorr, and the radio frequency power is 100-1000 watts.
Since the first material layer 400 is made of a non-conductive material, a conductive plug connected to the first metal layer 300 cannot be directly formed on the first material layer 400.
Referring to fig. 9, the exposed first material layer 400 is chemically treated to form a second material layer 410.
The first material layer 400 is chemically treated, so that the first material layer 400 is prevented from being directly removed by adopting dry etching and other processes, the covering layer 210 and the first metal layer 300 are not damaged, the quality of the formed interconnection structure is ensured, the first metal layer 300 is not penetrated, and the reliability of the semiconductor structure is improved.
In this embodiment, the chemical treatment is an oxidation treatment, and the first material layer 400 is boron carbide. In particular, the exposed first material layer 400 is directionally oxidized to form the second material layer 410. In this embodiment, the second material layer 410 is boron trioxide.
In this embodiment, the gas used for the oxidation treatment includes oxygen and argon.
With reference to fig. 9, in this embodiment, before the first material layer 400 is oxidized, a protection layer 610 is further formed on the sidewall of the through hole 600.
In this embodiment, the protection layer 610 is a low-K dielectric layer, has waterproof and anti-oxidation functions, and can protect the second dielectric layer 500 from being damaged during the oxidation process.
In this embodiment, referring to fig. 10, after the second material layer 410 is generated, the second material layer 410 is removed.
In this embodiment, the second material layer 410 is removed by wet cleaning, the solution of the wet cleaning is a diluted hydrofluoric acid solution, and a volume ratio of hydrofluoric acid to water is 1: 2000-1: 3000.
in other embodiments, the solution for wet cleaning may also be deionized water.
When a diluted hydrofluoric acid solution is used as a solution for wet cleaning, the protective layer 610 is removed together with the second material layer 410; when the second material layer 410 is removed using deionized water as a solution for wet cleaning, the protective layer 610 remains.
In this embodiment, the removal of the first material layer 400 is converted into the removal of the second material layer 410, because the direct removal of the first material layer 400 easily causes the first metal layer 300 to penetrate, thereby reducing the reliability of the generated semiconductor structure, and after the removal of the first material layer 400 is converted into the second material layer 410, the second material layer is removed by a wet cleaning method, so that the cover layer 210 and the first metal layer 300 are not damaged by deionized water or a diluted hydrofluoric acid solution, thereby improving the performance of the semiconductor structure.
With reference to fig. 10, after the second material layer 410 is removed, the via 600 is filled with a second metal layer 620, so as to form a conductive plug connected to the first metal layer 300.
In this embodiment, the method of forming the conductive plug includes: filling a second metal material layer in the through hole 600, wherein the second metal material layer covers the side wall and the bottom of the through hole 600 and the surface of the second dielectric layer 500; and performing chemical mechanical polishing on the second metal material layer to make the top of the second metal material layer flush with the surface of the top of the second dielectric layer 500, so as to form the second metal layer 620, wherein the second metal layer 620 is in contact connection with the first metal layer 300.
In this embodiment, the second metal material layer is filled in the through hole 600 by an electrochemical plating method.
The material of the second metal layer 620 may be copper, cobalt, tungsten, or platinum. In this embodiment, the second metal layer 620 is copper.
In this embodiment, in the process of forming the conductive plug, the shape of the covering layer 210 is kept stable, and the distance between adjacent covering layers 210 is also fixed, so that the size of the bottom of the finally formed conductive plug is also fixed and cannot be enlarged, so as to avoid the occurrence of a short circuit.
In another embodiment, the chemical treatment is a reduction treatment, and the first material layer 400 is copper nitride or aluminum nitride.
The technological parameters of the reduction treatment comprise: hydrogen is used as the reducing gas.
When the first material layer 400 is copper nitride, the second material layer can be generated by adopting a thermal decomposition method, wherein the temperature of the thermal decomposition is 300-400 ℃.
Referring to fig. 11, when the first material layer 400 is copper nitride, the second material layer 410 formed after the reduction process is copper. Since the first metal layer 300 is copper in this embodiment, the second metal layer 620 may be directly formed on the second material layer 410 without removing the second material layer 410, and the second metal layer 620 and the first metal layer 300 are connected to each other through the copper.
The method for forming the second metal layer 620 is the same as the method disclosed in the foregoing embodiments, and is not repeated herein.
The copper nitride is used as the material of the first material layer 400, so that the requirement of improving the performance of the semiconductor structure can be met, the process steps can be reduced, and the process flow can be simplified.
When the first material layer 400 is aluminum nitride, the second material layer 410 formed after the reduction process is aluminum. In this embodiment, since the material of the first metal layer 300 is copper, for better interconnection effect, after forming aluminum, the aluminum is removed, and then the second metal layer 620 is formed in the via.
In other embodiments, if the material of the first metal layer 300 is aluminum, the second metal layer 620 may be formed directly on the aluminum without removing the aluminum after forming the aluminum.
The method for removing aluminum is wet etching, and the etching solution of the wet etching comprises nitric acid solution or phosphoric acid solution or diluted sodium hydroxide solution and the like.
It should be noted that, when the first material layer 400 is aluminum nitride, before the first material layer 400 is formed, the covering layers 210 with a partial width are further etched, so that the distance between adjacent covering layers 210 is increased. This is done to completely expose the first metal layer 300 after the aluminum layer is subsequently removed, so that the first metal layer 300 and the second metal layer 620 are fully contacted, thereby improving the quality of the via hole.
In the technical scheme provided by the invention, on one hand, the covering layer and the first metal layer can be protected from being damaged in the forming process of the through hole by depositing the first material layer on the covering layer and the first metal layer, the quality of the through hole is improved, the bottom size of the through hole is limited, and short circuit is avoided; on the other hand, the second material layer is formed by carrying out chemical treatment on the first material layer, and the first material layer is not directly removed, so that the possibility of punch-through of the first metal layer can be reduced, and the reliability of the formed semiconductor structure can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, and sequentially forming a first dielectric layer and a covering layer on the semiconductor substrate;
forming a plurality of discrete first metal layers in the first dielectric layer and the covering layer, wherein the top of each first metal layer is flush with the surface of the top of the covering layer;
forming a first material layer on the covering layer and the surface of the first metal layer;
forming a second dielectric layer on the surface of the first material layer;
etching the second dielectric layer until the surface of the first material layer is exposed to form a through hole;
and carrying out chemical treatment on the exposed first material layer to form a second material layer.
2. The method of forming a semiconductor structure of claim 1, wherein the chemical treatment comprises an oxidation treatment or a reduction treatment.
3. The method of claim 2, wherein when the chemical treatment is an oxidation treatment, the first material layer is boron carbide and the second material layer is diboron trioxide.
4. The method of claim 2, wherein the first material layer comprises copper nitride or aluminum nitride when the chemical process is a reduction process.
5. The method of forming a semiconductor structure of claim 4, further comprising, after forming the second material layer: and filling a second metal layer in the through hole to form a conductive plug connected with the first metal layer.
6. The method of forming a semiconductor structure of claim 3, further comprising, after forming the second material layer:
removing the second material layer;
and filling a second metal layer in the through hole to form a conductive plug connected with the first metal layer.
7. The method of claim 6, wherein the second material layer is removed by wet cleaning, and a solution of the wet cleaning comprises deionized water or a hydrofluoric acid solution.
8. The method of claim 3, wherein a protective layer is formed on the sidewall of the via prior to the oxidation process.
9. The method of claim 1, wherein a portion of the thickness of the first metal layer is etched to a level below a top surface of the cap layer prior to forming the first material layer.
10. The method of forming a semiconductor structure of claim 1, wherein etching the second dielectric layer comprises:
forming a hard mask layer on the surface of the second dielectric layer;
patterning the hard mask layer to form an opening, wherein the second dielectric layer on the top of the first material layer is exposed out of the opening;
and etching the second dielectric layer along the opening until the surface of the first material layer is exposed.
11. The method of claim 10, wherein the hard mask layer comprises one or more of titanium nitride, aluminum nitride, boron nitride, or tantalum nitride.
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| CN116130414A (en) * | 2023-04-20 | 2023-05-16 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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| US20160305024A1 (en) * | 2013-12-24 | 2016-10-20 | Up Chemical Co., Ltd. | Copper metal film, method for preparing the same, and method for forming copper interconnect for semiconductor device using the same |
| CN105448805A (en) * | 2014-08-26 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US20180350621A1 (en) * | 2017-06-02 | 2018-12-06 | Applied Materials, Inc. | Dry stripping of boron carbide hardmask |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116130414A (en) * | 2023-04-20 | 2023-05-16 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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