CN103928389A - Forming method of semiconductor structure - Google Patents
Forming method of semiconductor structure Download PDFInfo
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- CN103928389A CN103928389A CN201310009273.8A CN201310009273A CN103928389A CN 103928389 A CN103928389 A CN 103928389A CN 201310009273 A CN201310009273 A CN 201310009273A CN 103928389 A CN103928389 A CN 103928389A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
- H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
Abstract
Disclosed is a forming method of a semiconductor structure. The method comprises: providing a semiconductor substrate; successively forming an interlayer dielectric layer and a mask layer on the semiconductor substrate from the bottom to the top; forming a through hole penetrating the thicknesses of the interlayer dielectric layer and the mask layer; forming a copper metal layer in the through hole, the upper surface of the copper metal layer being lower than the upper surface of the interlayer dielectric layer; forming an aluminum nitride adhesive layer on the upper surfaces of the copper metal layer and the mask layer and the side wall of the through hole above the copper metal layer; forming a first barrier layer on the aluminum nitride adhesive layer, the upper surface of the first barrier layer disposed above the metal copper layer being not lower than the upper surface of the interlayer dielectric layer; and performing a planarization technology until the interlayer dielectric layer is exposed. According to the utility model, the aluminum nitride adhesive layer is formed between the copper metal layer and the first barrier layer, so that the combination degree of the copper metal layer and the first barrier layer is improved, and the formed semiconductor structure is good in performance and high in yield.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of formation method of semiconductor structure.
Background technology
Along with the development of semiconductor integrated circuit technology, dimensions of semiconductor devices and interconnection structure size constantly reduce, thereby cause the spacing between metal connecting line dwindling gradually, interlayer dielectric layer for isolating metal line also thins down, and can cause like this may crosstalking between metal connecting line.Now, by reducing the dielectric constant of interlayer dielectric layer between metal connecting line, can effectively reduce this crosstalking, and low k(dielectric constant) interlayer dielectric layer can effectively reduce resistance capacitance between metal connecting line and postpone (RC delay), therefore low-k materials and super low-k materials are applied in the interlayer dielectric layer of interconnection process more and more widely.
Because air is the material (k=1.0) that current obtainable k value is minimum, in interlayer dielectric layer, form air-gap or hole, can effectively reduce the k value of interlayer dielectric layer.Therefore,, in order further to reduce k value, interlayer dielectric layer adopts porous material more.
In addition, in semiconductor circuit, the transmission of signal between semiconductor device needs highdensity metal interconnecting wires, utilizes process for copper to make RC that metal interconnecting wires can reduce interconnection line and postpones, improves the integrity problem that electromigration etc. causes, therefore the application of copper interconnection structure is more and more extensive.
In the Chinese patent application that is CN101996924A at publication number, can find more formation methods about interconnection structure.
Prior art is after copper interconnection structure forms, need to above copper interconnecting line, form barrier layer, to stop the diffusion of copper interconnecting line material, avoid dielectric breakdown (the time dependent dielectric breakdown of the semiconductor device generation with the time correlation that comprise copper interconnection structure, be called for short TDDB), the reliability of raising semiconductor device.
But, in the time that the semiconductor device that adopts technique scheme to obtain is detected, the poor adhesion in discovery semiconductor device between copper interconnecting line and barrier layer, easily peel off on copper interconnecting line and barrier layer, has a strong impact on the performance of formed semiconductor device.And, in last part technology, at least in semiconductor device, form more than 7 layers copper interconnecting line, the package failure that very easily causes semiconductor device is peeled off on copper interconnecting line and barrier layer, and the rate of finished products of the semiconductor device that forms is low.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, improves the adhesiveness between barrier layer and copper metal layer in semiconductor structure, finally improves performance and the rate of finished products of semiconductor structure.
For addressing the above problem, the invention provides a kind of formation method of semiconductor structure, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form successively from the bottom to top interlayer dielectric layer and mask layer;
Formation runs through the through hole of interlayer dielectric layer and mask layer thickness;
In described through hole, form copper metal layer, the upper surface of described copper metal layer is lower than the upper surface of described interlayer dielectric layer;
On the sidewall of through hole above the upper surface of described copper metal layer and mask layer and copper metal layer, form aluminium nitride adhesion layer;
On described aluminium nitride adhesion layer, form the first barrier layer, the upper surface that is positioned at the first barrier layer, copper metal layer top is not less than the upper surface of interlayer dielectric layer;
Carry out flatening process, to exposing described interlayer dielectric layer.
Optionally, forming aluminium nitride adhesion layer comprises:
On the sidewall of through hole above the upper surface of described copper metal layer and mask layer and copper metal layer, form aluminum metal layer;
Described aluminum metal layer is carried out to nitrogen plasma treatment, form aluminium nitride adhesion layer.
Compared with prior art, technical solution of the present invention has the following advantages:
Form the first barrier layer on copper metal layer before, form aluminium nitride adhesion layer at copper metal layer upper surface, because the adhesiveness on aluminium nitride adhesion layer and copper metal layer and the first barrier layer is good, can effectively improve the conjugation on copper metal layer and the first barrier layer, avoid copper metal layer and the first barrier layer to peel off, improved performance and the rate of finished products of the semiconductor structure that forms.
Further, the material on described the first barrier layer is nitrogenous carborundum or silicon nitride, because the adhesiveness of nitrogenous carborundum and silicon nitride and aluminium nitride is good, and the adhesiveness of aluminium nitride and copper metal layer is good, aluminium nitride adhesion layer between copper metal layer and the first barrier layer can effectively improve the conjugation on copper metal layer and the first barrier layer, and then improves performance and the rate of finished products of the semiconductor structure that forms.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of formation method one execution mode of semiconductor structure of the present invention;
Fig. 2 ~ Fig. 8 is the schematic diagram of formation method one embodiment of semiconductor structure of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implemented but the present invention can also adopt other to be different from alternate manner described here, therefore the present invention is not subject to the restriction of following public specific embodiment.
Just as described in the background section, the poor adhesion in the semiconductor device that existing technique forms between copper interconnecting line and barrier layer, easily peel off on copper interconnecting line and barrier layer, has had a strong impact on the performance of the semiconductor device that forms.And, in existing semiconductor device, at least comprising more than 7 layers copper interconnecting line, the package failure that very easily causes semiconductor device is peeled off on copper interconnecting line and barrier layer, and the rate of finished products of the semiconductor device that forms is low.
For above-mentioned defect, the invention provides a kind of formation method of semiconductor structure, before forming the first barrier layer, first at the formation of copper metal layer upper surface and copper metal layer and the good aluminium nitride adhesion layer of the first barrier layer adhesiveness, to improve the conjugation on copper metal layer and the first barrier layer, avoid copper metal layer and the first barrier layer to peel off, and then avoid semiconductor structure to lose efficacy in encapsulation process, improve semi-conductive performance and the rate of finished products of forming.
Be elaborated below in conjunction with accompanying drawing.
With reference to figure 1, be the schematic flow sheet of formation method one execution mode of semiconductor structure of the present invention, comprising:
Step S1, provides Semiconductor substrate, and forms successively from the bottom to top stop-layer, interlayer dielectric layer and mask layer in described Semiconductor substrate;
Step S2, forms the through hole that runs through described stop-layer, interlayer dielectric layer and mask layer;
Step S3, forms copper metal material in described through hole and on the mask layer of through hole both sides;
Step S4, carries out flatening process to described copper metal material, to the copper metal material that remains predetermined thickness on mask layer;
Step S5, removes the copper metal material of predetermined thickness on mask layer and the copper metal material of the interior segment thickness of through hole, forms copper metal layer, and the upper surface of described copper metal layer is lower than the upper surface of described interlayer dielectric layer;
Step S6 forms aluminum metal layer on the sidewall of through hole above the upper surface of described copper metal layer and mask layer and copper metal layer;
Step S7, carries out nitrogen plasma treatment to described aluminum metal layer, forms aluminium nitride adhesion layer;
Step S8 forms the first barrier layer on described aluminium nitride adhesion layer, and the upper surface that is positioned at the first barrier layer, copper metal layer top is not less than the upper surface of interlayer dielectric layer;
Step S9, carries out flatening process, to exposing described interlayer dielectric layer;
Step S10 forms the second barrier layer on interlayer dielectric layer, aluminium nitride adhesion layer and the first barrier layer.
With reference to figure 2 ~ Fig. 8, by specific embodiment, the formation method of semiconductor structure of the present invention is described further.
With reference to figure 2, provide Semiconductor substrate 100.
The material of described Semiconductor substrate 100 can be monocrystalline silicon or single-crystal silicon Germanium, or monocrystalline carbon doped silicon; Or the material that can also comprise other, the present invention does not limit this.In the present embodiment, the material of described Semiconductor substrate 100 is monocrystalline silicon.
In described Semiconductor substrate 100, can be formed with device architecture (not shown), described device architecture can be the device architecture forming in semiconductor FEOL, such as MOS transistor etc.
Continue with reference to figure 2, in described Semiconductor substrate 100, form successively from the bottom to top stop-layer 102, interlayer dielectric layer 104 and mask layer 106, and form the through hole 107 that runs through stop-layer 102, interlayer dielectric layer 104 and mask layer 106.
In the present embodiment, the material of described stop-layer 102 is silicon nitride, and for preventing that the follow-up copper metal layer material being formed in through hole 107 from diffusing to Semiconductor substrate 100, the method that forms stop-layer 102 is chemical vapor deposition method.
In other embodiments, also can in Semiconductor substrate 100, directly form interlayer dielectric layer 104 and mask layer 106, be omitted in the step that forms stop-layer 102 in Semiconductor substrate 100.Accordingly, after interlayer dielectric layer 104 and mask layer 106 formation, form the through hole that runs through interlayer dielectric layer 104 and mask layer 106.
The material of described interlayer dielectric layer 104 can be low-k materials (scope of dielectric coefficient k is 3.9 ~ 2.8), as SiO
2, one or more in SiOF, SiCOH, SiO, SiCO, SiCON.The material of described interlayer dielectric layer 104 also can be super low-k materials (scope of dielectric coefficient k is 2.2 ~ 2.8), as carbonado (Black Diamond, BD) etc.The method that forms described interlayer dielectric layer 104 can be chemical vapor deposition method.
Preferably, after forming interlayer dielectric layer 104, before forming mask layer 106, also comprise: in described interlayer dielectric layer 104, form air-gap or hole (not shown), further to reduce the k value of interlayer dielectric layer 104, improve the isolation effect of interlayer dielectric layer 104, and reduce resistance capacitance delay.Concrete, can be by interlayer dielectric layer 104 is carried out to UV treatment, or with methyldiethoxysilane (Diethoxymethylsilane-C
5h
14o
2si, referred to as DEMS) form described hole as presoma (precursor), using terpinene (alpha-terpinene, ATRP) as pore former, its concrete technology is known those skilled in the art, does not repeat them here.
Described mask layer 106 can be single layer structure, as titanium nitride single layer structure; Also can be sandwich construction, as comprised successively from the bottom to top the sandwich construction of silica hard mask layer and titanium nitride mask layer.The present invention does not limit the material of mask layer 106.In the present embodiment, described mask layer 106 is titanium nitride single layer structure.
In the present embodiment, in described Semiconductor substrate 100, form successively from the bottom to top after stop-layer 102, interlayer dielectric layer 104 and mask layer 106, while forming the through hole 107 that runs through stop-layer 102, interlayer dielectric layer 104 and mask layer 106, can comprise the steps:
On described mask layer 106, form photoresist layer (not shown), in described photoresist layer, be formed with the litho pattern corresponding with through hole 107 shapes and position;
Taking described photoresist layer as mask, along mask layer 106, interlayer dielectric layer 104 and stop-layer 102 described in litho pattern successively etching, to exposing Semiconductor substrate 100, form through hole 107;
Remove described photoresist layer.
Concrete, taking described photoresist layer as mask, can be dry etching along the method for mask layer 106, interlayer dielectric layer 104 and stop-layer 102 described in litho pattern successively etching, its concrete technology is well known to those skilled in the art, and does not repeat them here.
It should be noted that, after forming through hole 107, also can comprise: carry out cleaning, form residual accessory substance in through hole 107 processes to remove dry etching.
With reference to figure 3, in through hole 107 described in Fig. 2 and on the mask layer 106 of through hole 107 both sides, form copper metal material 108a, described copper metal material 108a fills up described through hole 107.
In the present embodiment, form copper metal material 108a and can be copper electroplating technology (electro-coppering plating, referred to as ECP), its concrete technology is well known to those skilled in the art, and does not repeat them here.The thickness of described copper metal material 108a is 5000 dust ~ 7000 dusts.
In the present embodiment, before forming copper metal material 108a, also comprise: on the bottom of through hole 107 and the mask layer 106 of sidewall and through hole 107 both sides, form successively the 3rd barrier layer (not shown) and be positioned at the inculating crystal layer (not shown) on the 3rd barrier layer.The material on described the 3rd barrier layer can be tantalum nitride, for improving the copper metal material 108a of follow-up formation and the conjugation of interlayer dielectric layer 104, improves the electric property of the semiconductor structure that forms.The formation technique on described the 3rd barrier layer can be physical vapour deposition (PVD), and it,, as those skilled in the art's known technology, does not repeat at this.The material of described inculating crystal layer can be copper, and it is as the negative electrode in subsequent copper electroplating technology, with at the interior formation copper of described through hole 107 metal material 108a.Meanwhile, described inculating crystal layer also can improve the adhesiveness between follow-up formation copper metal material 108a and the 3rd barrier layer, and then improves the performance of the semiconductor structure that forms.The formation technique of described inculating crystal layer can be physical vapour deposition (PVD), and its concrete formation technique, as those skilled in the art's known technology, does not repeat at this.
With reference to figure 4, copper metal material 108a in Fig. 3 is carried out to flatening process, to the copper metal material 108b that remains predetermined thickness in through hole 107 and on mask layer 106.
In the present embodiment, the method for carrying out flatening process is chemical mechanical milling tech.By remain predetermined thickness copper metal material 108b on mask layer 106, can avoid chemical mechanical milling tech to cause damage to mask layer 106.
With reference to figure 5, remove in Fig. 4 the copper metal material 108b of segment thickness in the copper metal material 108b of predetermined thickness on mask layer 106 and through hole, form copper metal layer 108c, the upper surface of described copper metal layer 108c is lower than the upper surface of described interlayer dielectric layer 104.
In the present embodiment, the method of removing in Fig. 4 the copper metal material 108b of segment thickness in the copper metal material 108b of predetermined thickness on mask layer 106 and through hole is wet etching, and the solution of described wet etching can be the mixed solution of sulfuric acid, sodium chloride and hydrogen peroxide.Because the mixed solution of sulfuric acid, sodium chloride and hydrogen peroxide is low to the etch rate of mask layer 106, mask layer 106 can effectively protect the interlayer dielectric layer 104 being positioned at below it to avoid damage in wet etching process.
In other embodiments, also can select according to the material of mask layer 106 solution of wet etching, do not damaging under the prerequisite of interlayer dielectric layer 104, removing the copper metal material 108b of predetermined thickness on mask layer 106 and the copper metal material 108b of the interior segment thickness of through hole.
Because the most copper metal material 108a being arranged on Fig. 3 mask layer 106 removes by flatening process, be arranged in copper metal layer 108b thinner thickness on Fig. 4 mask layer 106, the time of required wet etching is shorter, has effectively saved the time that forms semiconductor structure.
Continue with reference to figure 5, on the sidewall of through hole above the upper surface of described copper metal layer 108c and mask layer 106 and copper metal layer, form aluminum metal layer 110.
In the present embodiment, the method that forms aluminum metal layer 110 can be physical gas-phase deposition, and the thickness of described aluminum metal layer 110 is 50 dust ~ 500 dusts.
With reference to figure 6, aluminum metal layer 110 described in Fig. 5 is carried out to nitrogen plasma treatment, form aluminium nitride adhesion layer 112a.
In the present embodiment, while carrying out nitrogen plasma treatment, the flow of nitrogen is 100sccm ~ 5000sccm, and radio-frequency power supply power is 100W ~ 1500W.When in to Fig. 5, aluminum metal layer 110 carries out nitrogen plasma treatment, in aluminum metal layer 110, aluminium atom is combined with nitrogen-atoms and is formed aluminium nitride adhesion layer 112a, the thickness of aluminium nitride adhesion layer 112a that forms and the consistency of thickness of aluminum metal layer 110, also be 50 dust ~ 500 dusts, be positioned at the upper surface of the upper aluminium nitride adhesion layer 112a of copper metal layer 108c lower than the upper surface of described interlayer dielectric layer 104.
With reference to figure 7, on the adhesion layer of aluminium nitride described in Fig. 6 112a, form the first barrier layer 114a.
In the present embodiment, the material of described the first barrier layer 114a is nitrogenous carborundum or silicon nitride, and the method that forms the first barrier layer 114a can be chemical vapor deposition method, and it specifically forms technique and is well known to those skilled in the art, and does not repeat them here.
Because aluminium nitride adhesion layer 112a and copper metal layer 108c, material are that the first barrier layer 114a adhesiveness of nitrogenous carborundum or silicon nitride is good, make the conjugation of copper metal layer 108c and the first barrier layer 114a good, avoid the first barrier layer 114a and copper metal layer 108c to peel off, improved performance and the rate of finished products of the semiconductor structure that forms.
In the present embodiment, described the first barrier layer 114a fills up the through hole 107 of copper metal layer 108c top.In other embodiments, also can make to be positioned at the copper metal layer 108c top upper surface of the first barrier layer 114a and the upper surface flush of interlayer dielectric layer 104, or make to be positioned at the upper surface of copper metal layer 108c top the first barrier layer 114a a little more than the upper surface of interlayer dielectric layer 104, after guarantee planarization, remain under the prerequisite of the upper surface on the first barrier layer and the upper surface flush of interlayer dielectric layer 104, saved the time and the cost that form semiconductor structure.
With reference to figure 8, the first barrier layer 114a, aluminium nitride adhesion layer 112a described in Fig. 7 and mask layer 106 are carried out to flatening process, to exposing described interlayer dielectric layer 104, residue is positioned at aluminium nitride adhesion layer 112b and the first barrier layer 114b of interlayer dielectric layer 104.
Continue with reference to figure 8, on interlayer dielectric layer 104, aluminium nitride adhesion layer 112b and the first barrier layer 114b, form the second barrier layer 116.
In the present embodiment, described the second barrier layer 116 is identical with the material of the first barrier layer 114b, also can be nitrogenous carborundum or silicon nitride; The method that forms the second barrier layer 116 can be chemical vapor deposition method, and described the second barrier layer 116 thickness are 500 dust ~ 2000 dusts.Described the second barrier layer 116 diffuses to the follow-up semiconductor structure that is formed at interlayer dielectric layer 104 tops for preventing copper metal layer 108c material.
It should be noted that, in the present embodiment, described copper metal layer 108c can be interconnection line, can be also metal plug, does not limit at this.
In above embodiment, by form aluminium nitride adhesion layer 112b between the first barrier layer 114b and copper metal layer 108c, improve the conjugation of the first barrier layer 114b and copper metal layer 108c, avoid semiconductor structure to lose efficacy in encapsulation process, and then improved form semi-conductive performance and rate of finished products.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (13)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form successively from the bottom to top interlayer dielectric layer and mask layer;
Formation runs through the through hole of interlayer dielectric layer and mask layer thickness;
In described through hole, form copper metal layer, the upper surface of described copper metal layer is lower than the upper surface of described interlayer dielectric layer;
On the sidewall of through hole above the upper surface of described copper metal layer and mask layer and copper metal layer, form aluminium nitride adhesion layer;
On described aluminium nitride adhesion layer, form the first barrier layer, the upper surface that is positioned at the first barrier layer, copper metal layer top is not less than the upper surface of interlayer dielectric layer;
Carry out flatening process, to exposing described interlayer dielectric layer.
2. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, forms aluminium nitride adhesion layer and comprises:
On the sidewall of through hole above the upper surface of described copper metal layer and mask layer and copper metal layer, form aluminum metal layer;
Described aluminum metal layer is carried out to nitrogen plasma treatment, form aluminium nitride adhesion layer.
3. the formation method of semiconductor structure as claimed in claim 2, is characterized in that, the method that forms aluminum metal layer is physical gas-phase deposition.
4. the formation method of semiconductor structure as claimed in claim 2, is characterized in that, while carrying out nitrogen plasma treatment, the flow of nitrogen is 100sccm ~ 5000sccm, and radio-frequency power supply power is 100W ~ 1500W.
5. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the thickness of described aluminium nitride adhesion layer is 50 dust ~ 500 dusts.
6. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the material on described the first barrier layer is nitrogenous carborundum or silicon nitride.
7. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, is carrying out flatening process, after exposing described interlayer dielectric layer, also comprises: on interlayer dielectric layer, aluminium nitride adhesion layer and the first barrier layer, form the second barrier layer.
8. the formation method of semiconductor structure as claimed in claim 7, is characterized in that, the material on described the second barrier layer is nitrogenous carborundum or silicon nitride.
9. the formation method of semiconductor structure as claimed in claim 7, is characterized in that, the thickness on described the second barrier layer is 500 dust ~ 2000 dusts.
10. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, forms copper metal layer and comprise in described through hole:
In described through hole and on the mask layer of through hole both sides, form copper metal material;
Described copper metal material is carried out to flatening process, to the copper metal material that remains predetermined thickness on mask layer;
Remove the copper metal material of predetermined thickness on mask layer and the copper metal material of the interior segment thickness of through hole, form copper metal layer.
The formation method of 11. semiconductor structures as claimed in claim 10, is characterized in that, the method for removing the copper metal material of predetermined thickness on mask layer and the copper metal material of the interior segment thickness of through hole is wet etching.
The formation method of 12. semiconductor structures as claimed in claim 11, is characterized in that, the material of described mask layer is titanium nitride.
The formation method of 13. semiconductor structures as claimed in claim 12, is characterized in that, the solution of described wet etching is the mixed solution of sulfuric acid, sodium chloride and hydrogen peroxide.
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| CN106409757A (en) * | 2015-07-31 | 2017-02-15 | 三星电子株式会社 | Methods of fabricating a semiconductor device |
| CN106409757B (en) * | 2015-07-31 | 2022-02-01 | 三星电子株式会社 | Method for manufacturing semiconductor device |
| CN113130738A (en) * | 2019-12-30 | 2021-07-16 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN113130384A (en) * | 2020-01-16 | 2021-07-16 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor structure |
| CN111725133A (en) * | 2020-07-03 | 2020-09-29 | 华虹半导体(无锡)有限公司 | Method for manufacturing copper-aluminum interconnection structure |
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