TW460960B - A method to create a copper dual damascene structure with less dishing and erosion - Google Patents

Abstract

A dual damascene structure is created in a dielectric layer, the structure contains a barrier layer while a cap layer may or may not be provided over the layer of dielectric for further protection of the dual damascene structure. The surface of the copper in the dual damascene structure is recessed, a thin film is deposited and planarized/partially removed by either CMP or a plasma etch thereby providing a sturdy surface above the copper of the dual damascene structure that prevents dishing and erosion of this surface.

Description

460960 The research on the resistance to electromigration which is not related to other parts is easy to have basic application research gold which has copper in the standard circuit mounted chemical mechanical method. Device characteristics Metal interface rate material, the technology, the metal interconnect device, such as copper and gold, the formation of the centroid of the substitution alloy other than the resistivity of the formation of the centroid makes it applied to eliminate the undesired formation of low temperature and low temperature formation Process V. Description of Invention (υ [Background of the Invention] (1) Technical Field of the Invention The present invention relates to a description of a method for concave and corroded surfaces on copper and copper surfaces. (2) Description of the know-how As semiconductor devices and the interconnect used in these devices focus on finding low-resistance manufacturing, the use of these materials has been used by the semiconductor industry. However, it is extremely small, so electromigration is a minor disadvantage. Therefore, in addition to low electromigration. So far it has been studied to hope that the recombination of the South-South diffusion rate in the intermetallic metal and the use of copper belong to it. Although copper will oxidize on the interconnect interconnects Manufacturing; and more and more during and after the reduction of micro-miniaturization, the conductivity becomes more and more important ^ # and expertise in semiconductors is here. Since The most widely used material is that aluminum has a line width and the use of substitution metals such as silver in the manufacture of meter-limiting devices and silver is actively used. These metals will provide better metals. It is also more difficult to form and / or these metals in semiconductor devices and parts. Copper has the advantage of being a secondary method in recent years and has the advantage of being large and easy to process, except for the additional effects. Period and in Required Interconnect Guide 460960 V. Description of the Invention (2) Photoresist is used to define the pattern during the etching of the line pattern. After the etching of the line and the photoresist is completed, the photoresist must be removed, which is a high oxidation line It is carried out in a pattern environment, thus exposing copper to an oxidation process. For example, the soil-retaining ring is removed with an oxygen plasma, which breaks down the photoresist into ash that can be easily removed. J makes two kinds of metal interconnects Widely used methods and the use of dual embedded structures. Especially the copper metallization of 1 embedded based on embedded plugs into very small, sub-micron, ultra-large integrated electrical Dry meal Difficulty of application 'of the insert-process is not set

Greater acceptance. Recent applications have successfully used copper to obtain metal wires, most notably in the structure of a complementary metal oxide body, a six-layer copper metal device. In the formation of a CMOS embedded structure, a metal plug is first shaped ... In most cases, this surface is the surface of a semiconductor substrate. An intermediate dielectric layer is deposited on the surface, β r ^ t, and is removed (using, for example, plasma-assisted chemical rolling phase deposition techniques, and trenches for metal wires using silicon dioxide as a dielectric) are formed in the surface. Γ * ^ ^ > &, T (using techniques such as active ion etching). The trench is covered on the metal plug and is formed by the lithography + ancient + deposition method or the metal reflow method). The metal to Biscon (planarization using a chemical vapor phase surface will complete the embedded structure. Although the top surface of the mature eight dielectric layers is etched using active ion etching to the planarization system =: two early embedded structure systems The legal system is currently the only one used. Also know that, but the extension of the chemical-mechanical polishing-embedding process is a double-embedding system. ^ Insulating or dielectric materials such as silicon will be characterized. Conductive wire

4 6 0 9 6 0 V. Description of the invention (3), the grooves are formed to be double-embedded as well as grooves, and the tops with three as a one-touch etch resistance are used to prevent the via hole from being etched. A method to guide the silicon nitride is to form the first layer using the nitrogen. The dream layer is formed by passing through the nitride stone. The first layer of the dioxygen pattern can be deposited; the conductive line is etched (except for filling .Diamond and metal filling process, in which π is also formed to form a etched dielectric barrier layer which can be oxidized. The etched through the three formations are formed into a pattern for conducting on the surface of the substrate to the etched barrier. Conductive circuit and first dielectric flash deposition § silicon dioxide etching resistance. Top layer; etched and etched has been etched into the road and via hole process, among which conductive lines. A buried recessed method The central layer is used as the three-layer structure to allow the top layer to be first formed by light, and a barrier layer to be formed. The other layer is the first layer, whereby the first layer is formed, and the vias are characterized and formed. The interlayer is then blocked by a sinker and the system is simultaneously deposited with gold in a multi-layer interconnect dielectric layer in the insulating layer. The bottom layer can be a via hole and etch the electrical pattern. Can be connected to the middle layer will still use the shape The formed conductive line is again used as an etched via hole pattern and the etch stop layer is exposed and etched with two steps of silicon and nitrogen, and the etching path is buried at this time by the via hole opening to form an interconnection charge. The setting is based on this. It should be a nitride stone, a three-layer dielectric layer dielectric, and the top dielectric hole of the three-layer dielectric on the pattern of the dielectric can be pattern-aligned. The dielectric layer and the insulation layer are etched in the rest of the time. The oxide dielectric is oxidized here. The nitride is in the middle of it.) (Dual embedding is an improvement on single embedding, because it allows conductive grooves and dielectric holes. It is filled with metal at the same time, so the process steps are omitted. Based on the fact that copper is extremely difficult to reactive ion etching treatment,

460960 contains most groups of sharp and stubborn barrier layers. Similar barrier layers use compounds in combination with highly selective channels and micro-systems. Compared to this group of substrates, the stress and disadvantages of a copper diffusion preference will be silicon and disadvantages. The amines and polyisocyanates and pores are often invented by the group of titanium nitride pieces or their chemical inventions (in terms of construction, the mechanical mechanism will become superficial (due to pure (metal, oxygen-containing polymerization caused by diffusion) The holes and requirements of sulfonamide. First, combined with tungsten. In the category of this compound, it is a barrier and is based on excess polishing. Therefore, it is necessary to use chemical mechanical polishing. In order to form a buried type at high speed The wire has no scratches, and the copper is included in the slurry. The amount of the composition responsible for copper etching is used in an increased amount. In short, the etching is to remove the embedded copper and form holes based on it. Compounds such as the barrier layer or nitrided invention layer of the heavily corroded element, the barrier layer 5. The invention description is that the wire must be semi-polished, the copper rate must be improved, and it will be isotropic. The appearance of this material is high, and it is highly resistant to the processing of the worms in the imidamine. It will cause (4), and make it increase. If this group of land occurs. In the line. It is pointed out The disadvantage of copper electromigration is the oxygen-bonded element of copper with high expansion period, a type such as copper can also be used as copper. Such as the diffusivity of oxidation. The loss of copper caused by the entry into the poly, and the barrier layer is formed by the concave soft surface such as the titanium and or more elements containing tungsten or titanium. With chemically low resistivity, however, copper is generally aramide and copper and poly I. Sudden failure of this rot typically can be cranes, cranes, and other types of layers and / or groups of copper pairs. After the process of the base material, the large trench has a high selective polishing rate with a high polishing rate) and a low polishing rate

Page 8 460960

Fifth, the description of the invention (5)). The copper between the copper of the interconnect metal and the button of the barrier layer is removed at a faster rate than tantalum or tantalum-based materials, so the difference will cause a concave effect and corrosion on the surface of the copper interconnect metal. This results in serious formation of highly reliable copper large integrated circuit wires. It is difficult to reduce the size of the device, the aluminum via metallization of the via plug and / or the wiring will encounter high resistivity S metal conductivity migration problems. Copper films provide low resistivity and are shown to be extremely electromechanical. Therefore, it is quite attractive for the anti-electricity of super-large integrated circuit guide cars, especially when the device size is close to deep sub-micron materials. However, the dry etching process of copper film has not been successfully developed in size yet. One of the main reasons for this application has not been widely considered. It is a copper non-volatile copper halide compound 'wet etching and sputtering. Based on this, it cannot be engraved with copper. --- Concave Effect Copper in the Device The present invention teaches a method for reducing corrosion of copper surfaces used in interconnect metals and thus improving the surface flatness and surface uniformity of semiconductor surfaces. —Double copper inlay. US Patent No. 5,741,62 (Jain) indicates the buried process.

U.S. Patent No. 5,8 1 8,11 0 (C r ο n i η) discloses a process A P to the machine: mechanical polishing, an etch stop layer formed on the copper plug. Read line 5 leisure, line 3 5. , US Patent No. 5,814,55 7 (¥ 6111 ^ 1: "311 ^ 11 et al." Discloses a metal layer 16 on a copper plug in a dual embedding process. US Patent No. 5,674,787 (Zhao et al.) Revealed in—Steel Exchange

460960 V. Description of the invention (6) Connect one to cover / I1 and barrier 24. U.S. Patent No. 5, 7 2 3, 38 7 (Chen) discloses a cover layer formed on a copper plug after chemical mechanical polishing. U.S. Patent No. 5,744,376 (Chan et al.) Discloses a silicon nitride coating formed on a copper plug after chemical mechanical polishing. [Summary of the invention] One of the main objects of the present invention is to reduce the concave anticorrosion of the double-buried copper surface. Another object of the present invention is to improve the flatness and uniformity of the double-buried copper surface. According to the object of the present invention, a method for forming a copper double-buried interconnect structure is provided. An intermetal dielectric layer is deposited on the substrate. In a first embodiment of the present invention, a capping layer is deposited on the intermetal dielectric layer, and the dual embedded structure is formed through the capping layer and is embedded in the intermetal dielectric layer. A barrier layer is blanket-deposited on the double silver buried structure including the surface of the surrounding cover layer '. The copper for the double buried structure is deposited and polished. The polishing is performed on the surface of the barrier layer, and secondly, the surface of the copper longitudinal section of the double-embedded structure is reduced (peeled off) by a wet etching technique. The surface of copper is now lower than the surface of the barrier, and a thin film is blanket-deposited on the copper and the barrier layer. The film was removed by chemical mechanical polishing to form the surface of the copper longitudinal section of the dual embedded structure. The surface above the copper (including the remaining deposited film) was hard enough to make the copper surface concave. And corrosion can be avoided. The second embodiment of the present invention does not deposit a cover layer as shown above,

Page 10 4 6 0 9 6 0 V. Description of the invention (7) However, the other steps follow the same steps as in the first embodiment of the present invention. The steps are as follows: deposit an intermetal dielectric layer on the substrate to form A dual embedded structure is deposited in the intermetal dielectric layer, and a barrier layer is deposited on the dual embedded structure. Copper for the dual embedded structure is deposited and polished to the surface of the barrier layer. The surface of the dual-embedded structure is lowered (stripped) below the surface of the barrier layer, and a thin film is deposited on the copper and the barrier layer. The film is removed to form the surface of the copper longitudinal section of the double-embedded structure. The surface above the copper (including the remaining deposited film) is hard enough so that the concaveness and corrosion of the copper surface can be avoided. The third embodiment of the present invention is substantially completely according to the same procedure as the first embodiment of the present invention, and includes the deposition of a thin film layer. In a third embodiment of the present invention, the film is removed by plasma etching and provides the same results as those obtained in the previous two embodiments of the present invention. The fourth embodiment of the present invention is substantially completely according to the same procedure as the second embodiment of the present invention, and includes the deposition of a thin film layer. In a fourth embodiment of the present invention, the thin film is removed by plasma etching and provides the same results as those obtained in the previous three embodiments of the present invention. [Brief description of the drawing number] 10 Metal surface 12 Interlayer hole portion 14 Interconnecting conductor portion 16 Intermetallic dielectric layer 18 Cover layer 20 Barrier layer

Page 11 460960 V. Description of the invention (8) 22 Copper layer 24 Copper 26 Copper longitudinal section 28 Groove 3 0 Thin film 3 4 Thin film layer 4 0 Intermetal dielectric layer 42 Barrier layer 4 4 Copper layer [preferred implementation Explanation of Examples] Referring now particularly to Fig. 1, there is shown a cross-sectional view of a double-embedded structure that has been fabricated on the top end of a metal surface 10. The dual embedded structure includes a via hole portion 12 (which is in direct contact with the underlying metal layer 10), and an interconnect wire portion 14 (which is located above the via hole structure 12). The dual embedded structure has been formed in an intermetal dielectric layer 16. A cover layer 18 has been deposited on the surface of the intermetal dielectric layer before the longitudinal section of the double-re-buried structure is formed in the intermetal dielectric layer. The requirements for the cover layer must be the same as for a typical copper barrier layer, which can be easily removed from the intermetal dielectric surface by etching or chemical mechanical polishing. For the aforementioned materials that can be used in the barrier layer, silicon nitride meets the application requirements of this specification. A further requirement is that the cover layer is deposited to a suitable thickness, such as between about 100 and 300 angstroms, which allows for slight over-polishing into the cover layer in subsequent processes, leaving behind Appropriate part of this overlay. The remaining cover layer can be used as a copper oxidation / diffusion protective layer

Page 12 4 6 096 Ο 5. Description of the invention (9), so no separate processing step is required to deposit the layer. After the capping layer 18 is deposited, the double-embedded profile is formed through the capping layer 18 and into the dielectric layer 16. Figure 2 shows how the double-buried wall surface and the cover layer surface on the intermetal dielectric opening are lined with a tantalum-based barrier layer 20, and blanket-deposited over the barrier layer 20 A copper layer 22 that will fill the longitudinal section of the dual embedded structure and cover the surface of the barrier layer 20. Other barrier layers such as tungsten or tungsten compounds and titanium or titanium compounds can also be used. As described above, the present invention is not limited to the use of a giant-based barrier layer, and a barrier layer containing crane or titanium or other compounds may also be used. Fig. 3 is a cross-sectional view showing the removal of excess copper from above the surface of the intermetal dielectric 16; the removal of the copper can be accomplished using a chemical mechanical polishing process. During this process, the barrier layer 20, which is located under the copper and above the intermetal dielectric surface, can be used as a barrier layer. Copper 2 4 now has a longitudinal section of a typical double embedded structure. Figure _4 shows a new copper profile 2 6 after the copper (as shown in profile 24, figure 3) has been lowered or partially stripped by the double-buried opening. Cross-section view in the opening. Copper stripping can be accomplished using wet chemicals such as using CH3C00H / NH4F or CC1 4 / DMS0 as the etching substance. Fig. 4 shows that a groove 28 is formed in the longitudinal section of the double embedded structure. The height of the grooves shown is about 18. The depth of the over-polished layer 28 must be equal to or less than the height of the cover layer 18 between 100 and 300 Angstroms. This move provides that appropriate margin of coverage.

Page 13 460960 V. Description of the invention (10) It must be noted that, with regard to the second and fourth embodiments of the present invention ', no cover layer 18 is deposited. For these embodiments, the cross-section of the formed copper groove layer and the surrounding area is a longitudinal section as shown in FIG. 4 except that it does not have a cover layer 18. In addition, the surface of the copper embedded structure will be lowered below the surface of the intermetal dielectric, which can be used to illustrate the second embodiment and the fourth embodiment of the present invention in detail (FIGS. 7 and 8) ) Clearly understand. Fig. 5 shows a cross section after a thin film 30 has been blanket-deposited on the tantalum-based barrier layer and the double-embedded longitudinal groove. The film 30 may include nitride nitride or any other suitable dielectric, such as shed silicate glass, phosphosilicate glass, borophosphosilicate glass, and plasma-assisted silicon nitride. The purpose of the film 30 is to prevent copper oxidation and protect the copper surface from chemical or mechanical damage. During the removal of the tantalum-based barrier layer 20 using chemical mechanical polishing, this film 30 on the trench provides adequate corrosion resistance to copper. Figure 6 shows a cross section in which the film 30 and the barrier layer 20 on the surface of the intermetal dielectric layer 16 have been partially removed by chemical mechanical polishing. It must be emphasized that a thin film layer 30 is appropriately left above the double-embedded longitudinal section 26 and is shaped to be sufficiently hard to resist the concave or corroded surface. The thin layers 18 and 30 will form a composite layer and prevent the diffusion and oxidation of the copper surface of the buried structure. It is necessary to pay attention to the re-inlaying. If the surface of the film 30 (Figure 5) is polished and extended to the cover layer, the cover layer on the surface of the chemical mechanical intermetal dielectric in the layer 8 will benefit; On how the layers have not been removed because the Xiao (indwelling) barrier layer is used; the work is oxidized or diffused

V. Description of the Invention (11) FIG. 7 shows a second embodiment of the present invention. Fig. 7 is mainly achieved according to the same steps as previously emphasized in Figs. 1 to 5, but the obvious difference is that the cover layer is not deposited in the longitudinal section of the cross section shown in Fig. 7. A comparison between Figure 5 of the first embodiment and Figure 7 of the second embodiment will make it obvious. The steps for forming the double-embedded structure of FIG. 7 are as follows:-deposit an intermetallic dielectric layer 40 on a metal surface 10-form a double-embedded longitudinal section on the deposited intermetallic dielectric layer 40 Medium—deposit a barrier layer 42 in the double-buried structure and on the surface of the intermetal dielectric layer 40— blanket deposit a copper layer 4 4 over the barrier layer 42—downward In addition to the excess copper, a top surface of the barrier layer 42 is formed to form a groove in the copper contained in the double-embedded longitudinal section, thereby forming a copper fill 44 in the double-embedded longitudinal section. Figure 7 shows the deposition of a thin film layer 34 on the surface of the barrier layer 42 and on the surface of the recessed copper 44 in the double buried opening. All previous explanations of the thin film layer 30 (Fig. 5) apply equally to the thin film layer 34 of Fig. 7. During the use of chemical mechanical polishing to remove the tantalum-based barrier layer 4 2, the thin film 3 4 located above the trench will provide proper corrosion resistance to copper. Fig. 8 shows a cross-sectional view of the double-embedded structure after the thin film 34 (Fig. 7) and the barrier metal 42 have been polished on the surface of the intermetal dielectric layer 40 by a chemical mechanical polishing method. The thin film layer 34 above the double-embedded longitudinal section will form a surface that is sufficiently hard to withstand the effects of concave or corroded surfaces. Because the second embodiment does not provide copper oxidation and diffusion protection (the protection system

Page 15 460960 V. Description of the invention (12) is provided in the first implementation) The third difference between the copper accumulated in the structure table and the subsequent embedded structure lies in this, which can reduce the number of examples), And get the first result. Compared to nitriding; etched the base material of the button (after the material is removed, the dielectric is thin. The fourth real difference lies in this, which can reduce the number of cases), and the polishing results can be obtained. Compared with silicon nitride etched group-based materials (after the material is removed, the dielectric is on the dielectric. In this example, the remaining of the cover layer is not completely removed, so the layer is completed by the polishing of the thin film 34 It is then deposited on the surface. This layer is not shown in Figure 7. The thin layer of thin layer 34 will form a composite layer, which can make the dual surface resistant to diffusion and oxidation. The processing procedure of the example and The first embodiment (fig. 5) After deposition, the thin film 30 was removed using a plasma etching process—a chemical mechanical polishing process (compared to the first-best comprehensive flatness of the first embodiment). In terms of chemical machinery, in terms of etching, both chlorine and fluorine plasma etching can be used. (Included in the thin film layer). Chlorine plasma etching will provide a high degree of selectivity in etching. In the button base An over-etch can be completed on the cover layer or the degree of over-etch of the metal depends on the thickness of the film 30 in the dual-embedded structure. The processing sequence of this embodiment is the same as that of the second embodiment (Figure 7). 4 After deposition, a plasma etching process is used to remove a chemical Mechanical polishing process (compared to the second implementation of the excellent overall flatness is the first chemical mechanical. For etching, both chlorine and fluorine plasma etching can be used. (Included in the film layer), Chlorine plasma etching will provide a high degree of selectivity in the cover layer. Over-etching on the button base can be done on the cover layer or the degree of over-etching of the metal depends on the dual embedded structure.

Sixteenth I 460960 V. Description of the invention (13) The thickness of the thin film 34 above the copper. Although the present invention has been described and exemplified with reference to specific examples thereof, the present invention is not intended to be limited to these exemplary embodiments. Those skilled in the art will understand that changes and improvements can be made without departing from the invention. Therefore, he hopes that the present invention includes all such improvements and changes that fall within the scope of the appended patent applications and their equivalents.

Page 17 43 09 6 〇 Brief Description of Drawings Figure 1 shows a cross-sectional view of a double-embedded longitudinal profile including a cover layer. Figure 2 shows a blanket after deposition of a barrier layer and a copper layer. A cross-sectional view of the dual embedded structure after overlying deposition. Figure 3 is a cross-sectional view of the dual embedded structure after excess copper is removed. FIG. 4 is a cross-sectional view of the double-embedded structure after copper has been recessed in the double-embedded longitudinal section. Fig. 5 is a cross-sectional view showing the dual embedded structure of the first and third embodiments of the present invention after a thin film layer is deposited. FIG. 6 is a cross-sectional view of the dual-embedded structure of the first and third embodiments of the present invention after the thin-film layer deposition has been partially removed. , A cross-sectional view of the dual embedded structure of the second and fourth embodiments of the present invention. FIG. 8 is a cross-sectional view of the dual embedded structure of the second and fourth embodiments of the present invention after the film layer deposition is partially removed.

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Claims (1)

The structure of Λθ 096 0 is structured with heavy double copper. The upper surface of the base plate is half-guided. 1 *-" The treatment a uses four kinds of special methods ^ · Please apply for it. Six L is the step λ ^ ο. The side of the base plate of the cladding plate is used to lift the upper surface of the table; the structure of the surface of the surface is Qul Qul. The inlay is inlaid with two 8 · 1-^-^ 1. Shape the top surface of the structure and bury the surface of the double-sided digging structure attached to the surface. The structure is buried in the double-layered thin film, the cover, the culvert, and the double-layered structure. Table method; thin film, thin film, and thin film are accumulated in the first layer of the sinking layer. This branch has been separated from the resistance. ♦ The branch extension department, please remove the product Shen Ru, or the conductance of the route, and β— The bottom or pore layer contains a package.The structure is designed to tie the / -N C part of the semi-junction on the upper surface of the surface resist surface engraving plate etching base ^ ,, θα_Γ layer to block the silicon nitrogen This is the first layer of the first layer. The second layer is the mouth-end package. The top layer of an electrical layer blocks the pore resistance. The first dielectric is the intermediary M Μ Μ electro-formed dielectric one-the first layer of the first layer of the dielectric 'shen-silicon of the oxygen •, _, a layer containing the insulation Yu Zhe used the second series of layered silicon to vaporize and accumulate nitrogen to deposit the phase. The gas end is topped with a thin layer. The auxiliary layer of the auxiliary plasma is the first layer of the dielectric layer. The division of β- 咅 line conducts the structure of the structure. The double layer is below the layer & the second layer is made on the shoulder of the case layer tV. Quality, the second dielectric layer of the second layer of the electrical circuit breaks the dielectric interlinking with a nitrogen exchange should be the book's moment by borrowing its Page 19 46 096 0 VI. Apply for a patent and etch through the second dielectric layer, etch through the second silicon nitride barrier layer, touch through the first dielectric layer, and etch through Pass through the first barrier layer, thereby forming the interstitial hole pattern; remove the first barrier layer from the bottom of the interstitial hole pattern; form a conductive circuit pattern by engraving the day and etching the second A dielectric layer, using the second silicon nitride barrier layer as an etch barrier layer, thereby forming a conductive circuit pattern; depositing a barrier layer over the inside of the dual embedded structure, which covers the surface around the dual embedded structure A blanket depositing a metal layer on the surface of the second dielectric layer which includes the deposition of the metal inside the dual embedded structure; and removing excess metal from the surface of the second dielectric layer to the Barrier layer surface. 3. The method of claim 2 in which the metal comprises copper. 4. The method of claim 2 in which the barrier layer is selected from the group consisting of tantalum, tungsten, and titanium and their compound-based materials. 5. The method according to item 2 of the patent application, wherein the removal of excess metal from the surface of the second dielectric layer can be continued and the removal continues below the surface of the barrier layer, and thus the barrier The barrier layer is partially removed from the surface of the second dielectric layer in a planarized manner. 6. The method according to item 1 of the scope of patent application, wherein the excavation of the double-embedded structure surface is to etch the copper surface of the conductive circuit of the double-embedded structure, and the etching is to use CH3C00H / NF or CC1 4 / DMS0 as Wet chemical etching of the etched substance, or any other suitable wet Page 20 460960 ___ __ 6 7 8 9 · Scope of patent application — _________ Etching technology and process parameters, so the surface of the longitudinal section of the steel in the double embedded structure can be estimated in an estimable amount. It is included in the method of item i of the scope of patent application, wherein the surface of the double-embedded structure excavated by the excavation (thus, the membrane is on the surrounding surface of the buried structure) is a sedimentary product containing nitriding = double-embedded A thin film of a suitable material that provides protection from any copper or chemical or mechanical damage. Anti-oxidation effect and / or the method of Shen Qing patent scope item 1, the 嗲 2 film in the basin is a chemical mechanical polishing process, the surface of u: on the side of the square: This provides anti-concavity: : Film and = 4 a on the copper surface of the double-embedded structure, so that the sound of the far-distance barrier can be solved by hunting the electrical layer a & ^ learning mechanical polishing process and the first person Rugao surface is completely removed. / 弟 一介 Shen ί :: The method of enclosing item 1, in which the use of the removed part is etched; the electro-etching system can be obtained by using 1 ^ chlorine or fluorine plasma. π atmosphere fossils or similar materials have a high level of post-etch barrier layer = the method of the first item in the patent scope, 1 Φ ~ 嗦 is also layered on the surface of the film is /, medium-thickness deposition-diffusion resistance material, Can provide two or two products-a silicon nitride layer or other, quotient, damage protection. Surface oxidation resistance and / or chemistry; a method for processing a semiconductor top surface, comprising the steps of double-embedded steel structure Page 21 460960 6. The scope of the patent application provides a semiconductor substrate; forming a double embedded structure on the surface of the substrate; digging the surface of the double embedded structure; depositing a thin film on the surface of the excavated double embedded structure , Which covers the surface near the dual embedded structure; and a portion of the deposited film is removed. 1 2 · The method according to item 11 of the scope of patent application, wherein forming a double embedded structure (the structure includes a via hole or bottom and a conductive line or upper half) is: depositing a first silicon nitride resist Layer on the surface of the substrate, the first barrier layer is used as a remaining barrier for the opening of the dielectric layer; a first dielectric layer is deposited on top of the first barrier layer, the first dielectric layer will An interlayer dielectric layer is formed. The first layer includes silicon dioxide, and the first dielectric layer serves as a dielectric for the interlayer pores. A second barrier layer of plasma-assisted chemical vapor deposition of silicon nitride is deposited on the first dielectric layer. On top of a dielectric layer, the silicon nitride layer is used as a second etch stop layer for the conductive circuit portion of the dual embedded structure; a second dielectric layer is deposited on the second portion of the silicon nitride On the top of the barrier layer, the second dielectric layer is used as an interconnect dielectric; a cover layer is deposited on the surface of the second dielectric; a dielectric hole pattern is formed in the first dielectric layer. By etched through the cover layer and etched through the first layer, A dielectric layer, the silicon nitride more second resist layer was etched through, through the second etched through more Page 22 46 096 0 6. The scope of the patent application is a dielectric layer, so the hole pattern of the interlayer is formed; the first barrier layer is removed from the bottom of the hole pattern of the interlayer; a conductive circuit pattern is formed, which is borrowed The second dielectric layer is etched by etching through the cover layer, and the second dielectric layer is etched. The second barrier layer of silicon nitride is used as an etch barrier layer, thereby forming a conductive circuit pattern. A barrier layer is deposited on the dual damascene. Above the interior of the buried structure, it covers the surface surrounding the dual embedded structure; blanket depositing a metal layer on the surface of the second dielectric layer, which includes the deposition of metal inside the dual embedded structure; and Excess metal is removed from the surface of the second dielectric layer to the surface of the barrier layer. 1 3. The method of claim 12, wherein the metal comprises copper. 14. The method according to item 12 of the scope of patent application, wherein the barrier layer is selected from the group consisting of a button and tungsten and titanium and a compound-based material thereof. 15 · The method according to item 12 of the patent application range, wherein the cover layer contains silicon nitride or other appropriate dielectric material, which has the property that it can be easily removed using etching or chemical mechanical polishing techniques. The cover layer is deposited to a thickness between 100 and 300 Angstroms. 16 · The method of claim 11 in which the removal of excess metal from the surface of the second dielectric layer can be continued and the removal continues below the surface of the barrier layer, and thus the The barrier layer is partially removed from the surrounding surface of the dual embedded structure in a planarized manner. 17. The method according to item 11 of the scope of patent application, wherein the surface of the excavated dual-embedded structure is an etched copper surface of the dual-embedded structure, and the etching Page 23 4 6 096 0 6 18 19 20 Applicable patent scope ~~-The engraving is the use of ch3cooh / nf or CC1 4 / dmso as an etching substance and it is therefore included in the double i buried with an estimable amount. The surface of the steel profile in the structure. Re-mounting as described in the scope of patent application Jg > t ^ The excavated double burial m: 7: 4 deposition-the thin film on the surrounding surface of the buried structure is m 2 and covers the thin lining of the appropriate material of the double burial This product contains silicon nitride or any of its 4 I; Η / 臈, which can provide protection against oxidation and / or chemical or mechanical damage to the steel surface. / The method of item 1 in the rabbit circle, in which the diagnosis of the removed part is placed on a copper surface, and the photoresistive layer is left on the protective layer, thereby providing an anti-concavity and corrosion film. And the barrier watch is composed of the copper watch ® constructed by υ ::, so that the surface of the patent application :: layer is completely removed. You use the silver engraving process for electrical equipment, so that chlorine or electrical equipment can be similar. The material and the substrate are relatively etchable with two degrees of selectivity relative to the gaseous rock.