CN113130738A

CN113130738A - Semiconductor structure and forming method thereof

Info

Publication number: CN113130738A
Application number: CN201911391568.XA
Authority: CN
Inventors: 蔡巧明; 杨菁国
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2021-07-16

Abstract

The application discloses a semiconductor structure and a forming method thereof, wherein the method comprises the following steps: providing a substrate; forming a first barrier layer on the surface of the substrate; forming a first opening in the first barrier layer; forming a first electrode layer in the first opening; sequentially forming a variable resistance dielectric layer, a second electrode layer and a mask layer on the surface of the first electrode layer, wherein the variable resistance dielectric layer extends to the surface of the first barrier layer; and forming a second barrier layer on the surface of the first barrier layer, the sidewall of the variable resistance dielectric layer, the sidewall of the second electrode layer, the sidewall of the mask layer, and the surface of the mask layer. The semiconductor structure and the forming method thereof can form the side wall of the RRAM unit under the condition of not introducing new materials and new processes, and do not need to carry out adaptive adjustment on the manufacturing processes of other logic units except the RRAM unit.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to the field of semiconductor manufacturing technologies, and more particularly, to a semiconductor structure and a method for forming the same.

Background

Resistive Random Access Memory (RRAM) is an emerging next generation non-volatile Memory device. RRAM cells use resistance values rather than charge to store data. RRAM cells operate by conducting a filament or conductive path formed upon application of a sufficiently high voltage to a normally insulating variable resistance dielectric material, also referred to as a variable resistance dielectric layer, disposed between a top electrode layer and a bottom electrode layer. In particular, each RRAM cell includes a variable resistance dielectric layer whose resistance can be adjusted to represent a logic "0" or a logic "1".

In order to prevent free oxygen from diffusing from the dielectric layer to the variable resistance dielectric layer during the formation of the RRAM cell, thereby affecting the characteristics of the filament, it is generally necessary to add spacers (spacers) to the variable resistance dielectric layer or the RRAM cell. In the prior art, the spacers are obtained by depositing and etching a silicon nitride layer. However, since the etching selectivity between the silicon nitride layer and the etching stop layer thereunder is low, it is difficult to etch the silicon nitride layer while ensuring the thickness of the etching stop layer to be stable. To solve this problem, an auxiliary oxide layer is usually added between the etch stop layer and the silicon nitride layer. However, either the addition of the auxiliary oxide layer or the deposition and etching of the silicon nitride layer results in an increase in materials and process steps, and the newly introduced materials and processes affect compatibility with standard CMOS processes.

Therefore, a method of forming the sidewall spacers of RRAM cells compatible with standard CMOS processes is needed.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, it is an object of the present application to provide a semiconductor structure and a method for forming the same, which can form the sidewall of a RRAM cell without introducing new materials and new processes, and without adapting the manufacturing process of other logic cells than the RRAM cell.

One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a substrate; forming a first barrier layer on the surface of the substrate; forming a first opening in the first barrier layer; forming a first electrode layer in the first opening; sequentially forming a variable resistance dielectric layer, a second electrode layer and a mask layer on the surface of the first electrode layer, wherein the variable resistance dielectric layer extends to the surface of the first barrier layer; and forming a second barrier layer on the surface of the first barrier layer, the sidewall of the variable resistance dielectric layer, the sidewall of the second electrode layer, the sidewall of the mask layer, and the surface of the mask layer.

In some embodiments, the first barrier layer and the second barrier layer are comprised of the same material.

In some embodiments, the same material is carbon-doped silicon nitride or silicon carbide.

In some embodiments, the substrate comprises: the first dielectric layer is internally provided with a second opening; and a first interconnect layer formed within the second opening and in contact with the first electrode layer.

In some embodiments, the method of forming a semiconductor structure further comprises: forming a second dielectric layer on the surface of the second barrier layer; forming a third opening penetrating through the second dielectric layer, the second barrier layer and the mask layer, wherein the bottom of the third opening exposes the second electrode layer; and forming a second interconnect layer within the third opening.

In some embodiments, the semiconductor structure further comprises a non-RRAM logic cell, and a sum of a thickness of the first blocking layer and a thickness of the second blocking layer is equal to a thickness of a blocking layer in the non-RRAM logic cell.

In some embodiments, the first barrier layer has a thickness of 95 to 105 angstroms, the second barrier layer has a thickness of about 45 to 55 angstroms, and the barrier layer in the non-RRAM logic cell has a thickness of 140 to 160 angstroms.

Another aspect of the present application provides a semiconductor structure comprising: a substrate; a first barrier layer formed on the substrate and having a first opening; a first electrode layer formed in the first opening; the variable resistance dielectric layer is formed on the surface of the first barrier layer and extends to the surface of the first electrode layer; a second electrode layer formed on the surface of the variable resistance dielectric layer; the mask layer is formed on the surface of the second electrode layer; and a second barrier layer formed on the surface of the first barrier layer, the sidewall of the variable resistance dielectric layer, the sidewall of the second electrode layer, the sidewall of the mask layer, and the surface of the mask layer.

In some embodiments, the semiconductor structure further includes a second dielectric layer formed on a surface of the second barrier layer, and a second interconnect layer formed in a third opening and in contact with the second electrode layer, wherein the third opening penetrates through the second dielectric layer, the second barrier layer, and the mask layer.

The semiconductor structure and the forming method thereof provided by the application have the following advantages:

firstly, in the application, the second barrier layer and the first barrier layer form a dielectric layer structure which completely covers the RRAM unit together, so that the RRAM unit is well protected, and the side wall of the RRAM unit in the prior art is perfectly replaced.

Secondly, in the present application, it is not necessary to form a sidewall spacer through an etching process, nor to form an additional oxide layer, but only the same material and process as those of the first barrier layer are used to form the second barrier layer, and no new material and process are introduced, so that the method has good compatibility with a standard CMOS process.

Furthermore, in the present application, the sum of the thicknesses of the first blocking layer and the second blocking layer may be designed to be equal to a predetermined thickness of the blocking layer in the non-RRAM logic unit, and the material of the sum is also the same as the material of the blocking layer in the non-RRAM logic unit, so that there is no need to adaptively adjust the forming process of the non-RRAM logic unit.

Drawings

The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present disclosure, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:

FIG. 1 is a schematic diagram of a semiconductor structure;

FIG. 2 is a flow chart of a method of forming a semiconductor structure according to an embodiment of the present application;

fig. 3 to 20 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various local modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is not to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

Unless otherwise indicated, or as may be apparent from the context of use, any terms, abbreviations, acronyms, or scientific symbols and notations used herein are to be given their ordinary meaning in the technical disciplines to which the invention most closely pertains. The following terms, abbreviations and acronyms may be used throughout the description presented herein and shall generally be given the following meanings unless otherwise contradicted or elaborated upon by the description set forth herein.

The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the invention. Further, forming the first feature over or on the second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present application may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Additionally, spatially relative positional terms, such as "below …," "below …," "below," "above …," "on," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. Spatially relative positional terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Moreover, for ease of description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding elements.

The technical solution of the present application will be described in detail below with reference to the embodiments and the accompanying drawings.

As shown in fig. 1, a semiconductor structure comprises: a first dielectric layer 10, a first metal interconnection layer 20 formed in an opening of the first dielectric layer 10, a barrier layer 30 formed on the first dielectric layer 10 and the first metal interconnection layer 20, a second dielectric layer 80 formed on the barrier layer 30, a second metal interconnection layer 90 formed in an opening penetrating the barrier layer 30 and the second dielectric layer 80 and exposing the first metal interconnection layer 20, a bottom electrode layer 41 formed on the second dielectric layer 80 and the second metal interconnection layer 90, a resistance material layer 42 formed on the bottom electrode layer 41, a top electrode layer 43 formed on the resistive material layer 42, a hard mask layer 44 formed on the top electrode layer 43, a sidewall 70 formed on the sidewall of the bottom electrode layer 41, the resistive material layer 42, the top electrode layer 43 and the hard mask layer 44, a third dielectric layer 60 formed on the second dielectric layer 80 and the sidewall 70, and a third metal interconnect layer 50 formed in an opening of the third dielectric layer 60 exposing the hard mask layer 44.

In such a semiconductor structure, additional steps such as depositing the second dielectric layer 80, depositing a sidewall layer, and etching the sidewall layer are required to form the sidewall spacers 70, which not only increases the process cost, but also affects the compatibility with the standard CMOS process.

In order to solve the above problem, an embodiment of the present invention provides a method for forming a semiconductor structure, as shown in fig. 2, including the following steps:

step S101: providing a substrate;

step S102: forming a first barrier layer on the surface of the substrate;

step S103: forming a first opening in the first barrier layer;

step S104: forming a first electrode layer in the first opening;

step S105: sequentially forming a variable resistance dielectric layer, a second electrode layer and a mask layer on the surface of the first electrode layer, wherein the variable resistance dielectric layer extends to the surface of the first barrier layer;

step S106: and forming a second barrier layer on the surface of the first barrier layer, the side wall of the variable resistance dielectric layer, the side wall of the second electrode layer, the side wall of the mask layer and the surface of the mask layer.

The above steps will be described in detail with reference to fig. 3 to 20. It should be noted that methods that perform the above and below steps in other orders also fall within the scope of the present disclosure.

Embodiments of the present application relate to the RRAM region 1000, but in order to illustrate that the technical solution of the present application does not affect the non-RRAM manufacturing process, fig. 3 to 20 also show the non-RRAM region as a comparison.

As shown in fig. 3, a first dielectric layer 100 is provided.

The first dielectric layer 100 may be formed on a semiconductor substrate (not shown), and the material of the first dielectric layer 100 may be silicon oxide (e.g., SiO2), a low-K or very low-K dielectric (e.g., a dielectric having a dielectric constant K less than about 2). For example, the deposition may be formed by physical vapor deposition, chemical vapor deposition, or atomic layer deposition on a semiconductor substrate (not shown).

In the embodiments of the present application, the semiconductor substrate is defined as a RRAM region 1000 and a non-RRAM region, the RRAM region 1000 includes a RRAM cell, and the non-RRAM region includes a logic cell, such as a CMOS device. The semiconductor substrate may further include an interlayer interconnection structure and the like.

As shown in fig. 4, a second opening 230 is formed on the first dielectric layer 100.

The second opening 230 may be formed by spin-coating a photoresist on the surface of the first dielectric layer 100, forming an opening pattern in the photoresist after an exposure and development process, etching the first dielectric layer 100 to form the second opening 230, introducing oxygen plasma after etching, and ashing to remove the remaining photoresist.

Alternatively, in a non-RRAM region, a fourth opening 240 may be formed on the first dielectric layer 100, and the fourth opening 240 may be formed simultaneously with the second opening 230.

As shown in fig. 5, the first interconnect layer 210 is formed within the second opening 230. The first interconnect layer 210 may be any inter-level interconnect structure in the semiconductor structure, such as an inter-level interconnect structure electrically connected to M4.

The material of the first interconnect layer 210 may be a metal material such as copper (Cu), aluminum (Al), tantalum (Ta), tungsten (W), cobalt (Co), etc., or may be a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof. The first interconnect layer 210 may be formed in the second opening 230 by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating process, or other suitable process. When the first interconnect layer 210 is formed through the above process, the material deposited on the surface of the first dielectric layer 100 may be removed through a chemical mechanical polishing process.

The first dielectric layer 100 and the first interconnect layer 210 located in the first dielectric layer 100 together constitute a substrate.

Optionally, in a non-RRAM region, the third interconnect layer 220 may be formed within the fourth opening 240. The material and formation process of the third interconnect layer 220 may be the same as the first interconnect layer 210, and the third interconnect layer 220 may be formed simultaneously with the first interconnect layer 210.

As shown in fig. 6, a first barrier layer 310 is formed on the substrate. More specifically, the first barrier layer 310 is formed on the surface of the first dielectric layer 100 and the surface of the first interconnect layer 210.

The first barrier layer 310 is an etch stop layer, and may be made of silicon Carbide (SiC), silicon nitride (SiN), carbon-Doped silicon Nitride (NDC), or some other suitable dielectric, or any combination thereof. The first barrier layer 310 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, sputtering, or other suitable process. In one aspect, the first barrier layer 310 serves as a protection layer to prevent damage to the first dielectric layer 100 and the interconnect layers (e.g., the first interconnect layer 210 and the third interconnect layer 220) and other possible devices located in the first dielectric layer 100 by subsequent processes (e.g., etching processes). On the other hand, the first barrier layer 310 may provide a process basis for forming a first electrode layer 410 (to be described in detail later), forming the first electrode layer 410 electrically connected to the first interconnect layer 210. Optionally, in a non-RRAM region, the first barrier layer 310 may cover the third interconnect layer 220.

As shown in fig. 7, a first opening 400 is formed in the first barrier layer 310. The first opening 400 is located on the first interconnect layer 210 corresponding to the location of the first interconnect layer 210, and exposes only a portion of the first interconnect layer 210.

The first opening 400 may be formed by spin-coating a photoresist on the surface of the first barrier layer 310, forming an opening pattern in the photoresist after an exposure and development process, then etching the first barrier layer 310 to form the first opening 400, introducing oxygen plasma after etching, and ashing to remove the remaining photoresist.

As shown in fig. 8, a first electrode layer 410 is formed on the surface of the first barrier layer 310 and within the first opening 400. The first electrode layer 410 fills the first opening 400.

The first electrode layer 410 is a bottom electrode layer of the RRAM cell, and the material thereof may be a metal material such as tantalum (Ta), titanium (Ti), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten (W), etc., or a conductive material such as tantalum nitride (TaN), titanium nitride (TiN), etc., or any combination thereof. The first electrode layer 410 may also be a composite structure film layer including a plurality of layers of the above materials. The first electrode layer 410 can be formed by physical vapor deposition, chemical vapor deposition (e.g., metal organic chemical vapor deposition), atomic layer deposition, plating, sputtering, or other suitable process. The first electrode layer 410 functions to prevent metal ions in the first interconnection layer 210 from diffusing into a subsequently formed variable resistance dielectric layer 420 (to be described in detail later), so that the subsequently formed variable resistance dielectric layer 420 maintains good performance, thereby improving electrical performance of the formed RRAM device.

As shown in fig. 9, the first electrode layer 410 is planarized, and the first electrode layer 410 on the surface of the first barrier layer 310 is removed, such that the top of the first electrode layer 410 is flush with the top of the first barrier layer 310.

The Planarization process may be Chemical Mechanical Polishing (CMP) or other Planarization process.

As shown in fig. 10, a variable resistance dielectric layer 420 is formed on the surface of the first barrier layer 310 and the surface of the first electrode layer 410. It can also be considered that the variable resistance dielectric layer 420 extends continuously over the first electrode layer 410.

The variable resistance dielectric layer 420 is a resistance material layer of the RRAM cell, and the variable resistance dielectric layer 420 is used to form a "filament" that is considered to be an operational mechanism of the RRAM device. Meanwhile, the variable resistance dielectric layer 420 also functions as an insulating dielectric layer between the first electrode layer 410 and a subsequently formed second electrode layer 430 (to be described in detail later). The variable resistance dielectric layer 420 is made of a material having resistance change property of electrical induction, wherein the electrical induction means that the resistance of the material changes under a specific external signal, and the resistance value of the material does not recover due to the removal of an electrical signal after being changed; the resistance of the material is reversible, the resistance of the material can be reduced by applying an electric signal in one form, and the resistance can be restored to high resistance by applying an electric signal in another form.

The material of the variable resistance dielectric layer 420 may be amorphous silicon, polysilicon, copper oxide, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide, or any combination thereof. The variable resistance dielectric layer 420 may be formed using a chemical vapor deposition, physical vapor deposition, or atomic layer deposition process.

As shown in fig. 11, a second electrode layer 430 is formed on the surface of the variable resistance dielectric layer 420.

The second electrode layer 430 is a top electrode layer of the RRAM cell, and the material thereof may be a metal material such as silver (Ag), copper (Au), platinum (Pt), tungsten (W), etc., or a conductive material such as tantalum nitride (TaN), titanium nitride (TiN), etc., or any combination thereof. The second electrode layer 430 may also be a composite structure film layer including a plurality of layers of the above materials. The second electrode layer 430 can be formed by physical vapor deposition, chemical vapor deposition (e.g., metal organic chemical vapor deposition), atomic layer deposition, plating, sputtering, or other suitable process.

As shown in fig. 12, a mask layer 440 is formed on the surface of the second electrode layer 430. The mask layer 440 is a protective layer for the second electrode layer 430 in a subsequent etching process. In the subsequent etching process, the mask layer 440 may be thinned to some extent, but will not be completely removed by etching.

The mask layer 440 may be a hard mask layer having a single-layer structure or a stacked-layer structure. The material of the mask layer 440 may be silicon carbide (SiC), silicon nitride (SiN), NDC, or any combination thereof.

As shown in fig. 13, mask layer 440 is etched by an etching process to remove all mask layer 44 in the non-RRAM region and a portion of mask layer 440 in the RRAM region.

The etching process may be spin-coating a photoresist on the surface of the mask layer 440, forming an opening pattern in the photoresist after the exposure and development process, then etching the mask layer 440 to remove all the mask layer 44 located in the non-RRAM region and a part of the mask layer 440 in the RRAM region, introducing oxygen plasma after etching, and ashing to remove the remaining photoresist.

As shown in fig. 14, the second electrode layer 430 is etched by an etching process, and all the second electrode layer 430 in the non-RRAM region and a portion of the second electrode layer 430 in the RRAM region are removed.

The etching process may be performed by using the mask layer 440 as a mask to etch the second electrode layer 430 to remove all of the second electrode layer 430 located in the non-RRAM region and a portion of the second electrode layer 430 located in the RRAM region.

As shown in fig. 15, the variable resistance dielectric layer 420 is etched by an etching process, and all the variable resistance dielectric layer 420 located in the non-RRAM region and a portion of the variable resistance dielectric layer 420 of the RRAM region are removed.

The etching process may be performed by using the mask layer 440 and the second electrode layer 430 as masks, and etching the variable resistance dielectric layer 420 to remove all of the variable resistance dielectric layer 420 located in the non-RRAM region and a portion of the variable resistance dielectric layer 420 located in the RRAM region.

The second electrode layer 430, the variable resistance dielectric layer 420 and the first electrode layer 410 remaining after the etching process constitute a basic RRAM cell, and the device size thereof is set as required.

As shown in fig. 16, the second barrier layer 320 is formed on the surface of the first barrier layer 310, the sidewall of the variable resistance dielectric layer 420, the sidewall of the second electrode layer 430, the sidewall of the mask layer 440, and the surface of the mask layer 440.

The material of the second barrier layer 320 may be silicon carbide (SiC), silicon nitride (SiN), NDC, or some other suitable dielectric, or any combination of the above. Second barrier layer 320 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, sputtering, or other suitable process.

In some embodiments, the second barrier layer 320 and the first barrier layer 310 together form a dielectric layer structure that completely covers the RRAM cell, so as to protect the RRAM cell and exert the function of the sidewall of the RRAM cell in the prior art. Therefore, the deposition and etching processes which are required to be performed for forming the side wall in the prior art are omitted, and an additional oxide layer is not required to be formed under the etching stop layer (for example, the second barrier layer 320 in the present application), so that the process steps and the cost are saved.

Further, the second barrier layer 320 is formed using only the same material and process as the first barrier layer 310 without introducing any new material and process, and thus has good compatibility with a standard CMOS process. In the non-RRAM region, second barrier layer 320 and first barrier layer 310 correspond to barrier layers in a non-RRAM logic cell.

The thickness of the second barrier layer 320 may be less than or equal to the thickness of the first barrier layer 310. In the embodiment of the present invention, the sum H of the thicknesses of the first blocking layer 310 and the second blocking layer 320 may be designed to be equal to a predetermined thickness of the blocking layer in the non-RRAM logic cell in the non-RRAM region, and the material thereof is also the same as the material of the blocking layer in the non-RRAM logic cell, so that there is no need to adaptively adjust the forming process of the non-RRAM logic cell. Accordingly, the subsequent processes of forming the fourth interconnect layer 910 (shown in fig. 20) and the fifth interconnect layer 520 (shown in fig. 20) in the non-RRAM region also need not be adjusted. In some embodiments, the first barrier layer 310 has a thickness of 95 to 105 angstroms, the second barrier layer 320 has a thickness of about 45 to 55 angstroms, and the predetermined thickness of the barrier layer in the non-RRAM logic cell is 140 to 160 angstroms. For example, the thickness of the first barrier layer 310 is 100 angstroms, the thickness of the second barrier layer 320 is about 50 angstroms, and the predetermined thickness of the barrier layer in the non-RRAM logic cell is 150 angstroms.

As shown in fig. 17, a second dielectric layer 600 is formed on the second barrier layer 320. The second dielectric layer 600 is an interlayer dielectric layer (IMD), and thus, the thickness of the second dielectric layer 600 is greater than the sum of the thicknesses of the mask layer 440, the second electrode layer 430, the variable resistance dielectric layer 420, and the second barrier layer 320 at a portion outside the stack structure formed by the mask layer 440, the second electrode layer 430, and the variable resistance dielectric layer 420.

The material of the second dielectric layer 600 may be silicon oxide (e.g., SiO2), a low-K or very low-K dielectric (e.g., a dielectric having a dielectric constant K of less than about 2). The process for forming the second dielectric layer 600 includes depositing the second dielectric layer 600 on the second barrier layer 320 and performing chemical mechanical polishing on the second dielectric layer 600 to planarize the top thereof, after which a certain thickness of the second dielectric layer 600 still remains on the stacked structure formed by the mask layer 440, the second electrode layer 430 and the variable resistance dielectric layer 420 for forming therein a second interconnect layer 510 (shown in fig. 20) electrically connected to the second electrode layer 430. The second dielectric layer 600 may be deposited on the second barrier layer 320 by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

As shown in fig. 18, a third opening 530 is formed through the second dielectric layer 600, the second barrier layer 320 and the mask layer 440, and the bottom of the third opening 530 exposes the second electrode layer 430.

The third opening 530 may be formed by dry etching or wet etching.

As shown in fig. 19, in some embodiments, a fifth opening 920 and a sixth opening 540 may be formed in the non-RRAM region, the fifth opening 920 is penetrated with the sixth opening 540 and the bottom of the fifth opening 920 exposes the third interconnect layer 220. The fifth opening 920 and the sixth opening 540 may be formed by dry etching or wet etching.

As shown in fig. 20, a second interconnect layer 510 is formed within the third opening 530.

The material of the second interconnect layer 510 may be a metal material such as copper (Cu), aluminum (a1), tantalum (Ta), tungsten (W), cobalt (Co), etc., or may be a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof. The second interconnection layer 510 may be formed in the third opening 530 by physical vapor deposition, chemical vapor deposition, atomic layer deposition, plating process, or other suitable process.

Optionally, in a non-RRAM region, a fourth interconnect layer 910 may be formed in the fifth opening 920 and a fifth interconnect layer 520 may be formed in the sixth opening 540, and the fourth interconnect layer 910 and the fifth interconnect layer 520 may form a damascene interconnect structure. The material of the fourth interconnect layer 910 may be a metal material such as copper (Cu), aluminum (a1), tantalum (Ta), tungsten (W), cobalt (Co), etc., or may be a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof. The fourth interconnection layer 910 may be formed in the third opening 530 by physical vapor deposition, chemical vapor deposition, atomic layer deposition, plating process, or other suitable process. The material and formation process of the fifth interconnect layer 520 may be the same as those of the second interconnect layer 510.

Embodiments of the present application also provide a semiconductor structure, referring to fig. 3 to 20, including: a substrate, a first barrier layer 310, a first electrode layer 410, a variable resistance dielectric layer 420, a second electrode layer 430, a mask layer 440, and a second barrier layer 320. The substrate includes a first dielectric layer 100 and a first interconnect layer 210, the first dielectric layer 100 having a second opening 230 therein, the first interconnect layer 210 being formed within the second opening 230 and in contact with the first electrode layer 410. The first barrier layer 310 is formed on the substrate and has a first opening 400, and the bottom of the first opening 400 exposes the first interconnect layer 210. The first electrode layer 410 is formed in the first opening 400. The variable resistance dielectric layer 420 is formed on the surface of the first barrier layer 310 and extends to the surface of the first electrode layer 410. The second electrode layer 430 is formed on the surface of the variable resistance dielectric layer 420. The mask layer 440 is formed on the surface of the second electrode layer 430. The second barrier layer 320 is formed on the surface of the first barrier layer 310, the sidewall of the variable resistance dielectric layer 420, the sidewall of the second electrode layer 430, the sidewall of the mask layer 440, and the surface of the mask layer 440.

In some embodiments, the semiconductor structure further comprises a second dielectric layer 600 and a second interconnect layer 510. A second dielectric layer 600 is formed on the surface of the second barrier layer 320. The second interconnection layer 510 is formed in the third opening 530 and contacts the second electrode layer 430, and the third opening 530 penetrates the second dielectric layer 600, the second barrier layer 320, and the mask layer 440.

In conclusion, upon reading the present detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure can be presented by way of example only, and not limitation. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be suggested by this disclosure, and are within the spirit and scope of the exemplary embodiments of this disclosure.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate;

forming a first barrier layer on the surface of the substrate;

forming a first opening in the first barrier layer;

forming a first electrode layer in the first opening;

sequentially forming a variable resistance dielectric layer, a second electrode layer and a mask layer on the surface of the first electrode layer, wherein the variable resistance dielectric layer extends to the surface of the first barrier layer; and

and forming a second barrier layer on the surface of the first barrier layer, the side wall of the variable resistance dielectric layer, the side wall of the second electrode layer, the side wall of the mask layer and the surface of the mask layer.

2. The method of claim 1, wherein the first barrier layer and the second barrier layer are comprised of the same material.

3. The method of claim 2, wherein the same material is carbon-doped silicon nitride or silicon carbide.

4. The method of claim 1, wherein the substrate comprises:

the first dielectric layer is internally provided with a second opening; and

a first interconnect layer formed within the second opening and in contact with the first electrode layer.

5. The method of claim 4, further comprising:

forming a second dielectric layer on the surface of the second barrier layer;

forming a third opening penetrating through the second dielectric layer, the second barrier layer and the mask layer, wherein the bottom of the third opening exposes the second electrode layer; and

a second interconnect layer is formed within the third opening.

6. The method of claim 1, wherein the semiconductor structure further comprises a non-RRAM logic cell, and wherein a sum of the thickness of the first blocking layer and the thickness of the second blocking layer is equal to a thickness of a blocking layer in the non-RRAM logic cell.

7. The method of claim 6, wherein the first barrier layer has a thickness of 95 to 105 angstroms, the second barrier layer has a thickness of about 45 to 55 angstroms, and the barrier layer in the non-RRAM logic cell has a thickness of 140 to 160 angstroms.

8. A semiconductor structure, comprising:

a substrate;

a first barrier layer formed on the substrate and having a first opening;

a first electrode layer formed in the first opening;

the variable resistance dielectric layer is formed on the surface of the first barrier layer and extends to the surface of the first electrode layer;

a second electrode layer formed on the surface of the variable resistance dielectric layer;

the mask layer is formed on the surface of the second electrode layer; and

and the second barrier layer is formed on the surface of the first barrier layer, the side wall of the variable resistance dielectric layer, the side wall of the second electrode layer, the side wall of the mask layer and the surface of the mask layer.

9. The semiconductor structure of claim 8, wherein the first barrier layer and the second barrier layer are comprised of the same material.

10. The semiconductor structure of claim 9, wherein the same material is carbon-doped silicon nitride or silicon carbide.

11. The semiconductor structure of claim 8, wherein the substrate comprises:

the first dielectric layer is internally provided with a second opening; and

12. The semiconductor structure of claim 8, further comprising:

the second dielectric layer is formed on the surface of the second barrier layer; and

and the second interconnection layer is formed in a third opening and is in contact with the second electrode layer, and the third opening penetrates through the second dielectric layer, the second barrier layer and the mask layer.

13. The semiconductor structure of claim 8, further comprising a non-RRAM logic cell, wherein a sum of the thickness of the first blocking layer and the thickness of the second blocking layer is equal to a thickness of a blocking layer in the non-RRAM logic cell.

14. The semiconductor structure of claim 13, wherein the first barrier layer has a thickness of 95 to 105 angstroms, the second barrier layer has a thickness of about 45 to 55 angstroms, and the barrier layer in the non-RRAM logic cell has a thickness of 140 to 160 angstroms.