CN113497183A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN113497183A CN113497183A CN202010261486.XA CN202010261486A CN113497183A CN 113497183 A CN113497183 A CN 113497183A CN 202010261486 A CN202010261486 A CN 202010261486A CN 113497183 A CN113497183 A CN 113497183A
- Authority
- CN
- China
- Prior art keywords
- layer
- barrier layer
- side wall
- barrier
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 69
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 230000004888 barrier function Effects 0.000 claims abstract description 201
- 238000003860 storage Methods 0.000 claims abstract description 52
- 230000008859 change Effects 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 24
- 230000000149 penetrating effect Effects 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 590
- 239000000463 material Substances 0.000 claims description 92
- 229910052751 metal Inorganic materials 0.000 claims description 83
- 239000002184 metal Substances 0.000 claims description 83
- 125000006850 spacer group Chemical group 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 description 39
- 239000010949 copper Substances 0.000 description 14
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 239000004020 conductor Substances 0.000 description 10
- 239000007769 metal material Substances 0.000 description 10
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 10
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 10
- 229910052721 tungsten Inorganic materials 0.000 description 10
- 239000010937 tungsten Substances 0.000 description 10
- 238000000231 atomic layer deposition Methods 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 9
- 238000005240 physical vapour deposition Methods 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000007772 electrode material Substances 0.000 description 8
- 229910052715 tantalum Inorganic materials 0.000 description 8
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910017052 cobalt Inorganic materials 0.000 description 6
- 239000010941 cobalt Substances 0.000 description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 5
- 239000002131 composite material Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- 239000005751 Copper oxide Substances 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 229910000431 copper oxide Inorganic materials 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/023—Formation of switching materials, e.g. deposition of layers by chemical vapor deposition, e.g. MOCVD, ALD
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present application provides a semiconductor structure and a method of forming the same, the semiconductor structure comprising: a substrate comprising a storage region and a non-storage region; the first barrier layer is positioned on the surface of the substrate; the second barrier layer is positioned on the surface of the first barrier layer; a first electrode layer penetrating the first barrier layer and the second barrier layer of the storage region; the resistance change layer is positioned on the surface of the first electrode layer and extends to the surface of part of the second barrier layer of the storage region; the second electrode layer is positioned on the surface of the resistance change layer; and the side wall covers the side wall of the resistance change layer and the side wall of the second electrode layer and is positioned on the second barrier layer of the storage region. The silicon nitride layer forming the side wall and the second barrier layer have higher etching selectivity, so that the silicon nitride layer can be etched under the condition of ensuring the thickness of the second barrier layer to be stable.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Resistive Random Access Memory (RRAM) is an emerging next generation non-volatile Memory device. RRAM cells use resistance values rather than charge to store data. RRAM cells operate by conducting a filament or conductive path formed upon application of a sufficiently high voltage to a normally insulating variable resistance dielectric material, which may be referred to as a resistive layer, disposed between a top electrode layer and a bottom electrode layer. In particular, each RRAM cell includes a resistive layer whose resistance can be adjusted to represent a logic "0" or a logic "1".
In order to prevent free oxygen from diffusing from the dielectric layer to the resistive layer during the formation of the RRAM cell, thereby affecting the characteristics of the filament, it is often necessary to add spacers (spacers) to the resistive layer or RRAM cell. In the prior art, the spacers are obtained by depositing and etching a silicon nitride layer. However, since the etching selectivity of the silicon nitride layer and the barrier layer therebelow is low, it is difficult to etch the silicon nitride layer while ensuring the thickness of the barrier layer to be stable.
Therefore, it is necessary to develop a method for forming the side wall of the RRAM cell compatible with the standard CMOS process, which can etch the silicon nitride layer while ensuring the thickness of the barrier layer to be stable.
Disclosure of Invention
Aiming at the problem that the silicon nitride layer is difficult to etch under the condition of ensuring the thickness stability of the barrier layer when the RRAM unit side wall is formed at present, the application provides a semiconductor structure and a forming method thereof.
One aspect of the present application provides a semiconductor structure comprising: a substrate comprising a storage region and a non-storage region; the first barrier layer is positioned on the surface of the substrate; the second barrier layer is positioned on the surface of the first barrier layer; a first electrode layer penetrating the first barrier layer and the second barrier layer of the storage region; the resistance change layer is positioned on the surface of the first electrode layer and extends to the surface of part of the second barrier layer of the storage region; the second electrode layer is positioned on the surface of the resistance change layer; and the side wall covers the side wall of the resistance change layer and the side wall of the second electrode layer and is positioned on the second barrier layer of the storage region.
In some embodiments of the present application, the substrate comprises: a first dielectric layer; the first metal layer is positioned in the first medium layer of the storage area and is in contact with the first electrode layer; the first barrier layer is also positioned on the surface of the first medium layer and the surface of part of the first metal layer.
In some embodiments of the present application, the semiconductor structure further comprises: the mask protection layer is positioned on the surface of the second electrode layer, and the material of the mask protection layer is different from that of the second barrier layer; the side wall is also positioned on the side wall of the mask protection layer.
In some embodiments of the present application, the semiconductor structure further comprises: the second dielectric layer covers the second barrier layer, the side wall and the mask protective layer; and the second metal layer penetrates through the second dielectric layer on the second electrode layer and the mask protection layer and is electrically contacted with the second electrode layer.
In some embodiments of the present application, the material of the mask protection layer includes silicon nitride.
In some embodiments of the present application, the material of the first barrier layer comprises nitrogen-doped silicon carbide.
In some embodiments of the present application, the second barrier layer is made of silicon oxide, and the sidewall spacer is made of silicon nitride.
In some embodiments of the present application, the first barrier layer has a thickness of 200 to 600 angstroms and the second barrier layer has a thickness of about 150 to 250 angstroms.
In some embodiments of the present application, the substrate has a third metal layer in a non-storage region; the first barrier layer is also positioned on the surface of the third metal layer; the semiconductor structure further includes: a plug extending through the first barrier layer and the second barrier layer over the non-storage region; a fourth metal layer on top of the plug.
In some embodiments of the present application, the thickness of the second barrier layer at the bottom of the resistive layer is greater than the thickness of the second barrier layer at the bottom of the sidewall, and is greater than the thickness of the second barrier layer on the non-storage region; the side wall also extends to the surface of the side part of the second barrier layer at the bottom of the resistive random access layer.
Another aspect of the present application also provides a method of forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a storage region and a non-storage region; sequentially forming a first barrier layer and a second barrier layer on the first barrier layer on the surfaces of the storage region and the non-storage region of the substrate; forming a first electrode layer on the storage region, wherein the first electrode layer penetrates through the first barrier layer and the second barrier layer; after the first electrode layer is formed, a resistance change layer and a second electrode layer located on the surface of the resistance change layer are formed, wherein the resistance change layer is located on the surface of the first electrode layer and extends to the surface of a part of the second barrier layer of the storage region; and after forming the second barrier layer, forming side walls on the side walls of the resistance change layer and the side walls of the mask protection layer on the side walls of the second electrode layer.
In some embodiments of the present application, a method for forming the sidewall spacer includes: forming a side wall material layer on the side wall of the resistance change layer, the side wall of the second electrode layer, the surface of the second barrier layer and the second electrode layer; and etching the side wall material layer back until the surface of the second barrier layer is exposed to form the side wall.
In some embodiments of the present application, the substrate comprises: a first dielectric layer; the first metal layer is positioned on the first medium layer of the storage area; after the first barrier layer is formed and before the first electrode layer is formed, the first barrier layer is also positioned on the surface of the first dielectric layer and the surface of part of the first metal layer.
In some embodiments of the present application, the method of forming a semiconductor structure further comprises: before forming the side walls, forming a mask protection layer positioned on the top surface of the second electrode layer, wherein the material of the mask protection layer is different from that of the second barrier layer; after the side wall is formed, the side wall also covers the side wall of the mask protection layer; forming a second dielectric layer on the surface of the second barrier layer, the surface of the side wall and the surface of the mask protection layer; and forming a second metal layer penetrating through the second dielectric layer and the mask protection layer.
In some embodiments of the present application, the material of the mask protection layer includes silicon nitride.
In some embodiments of the present application, the material of the first barrier layer comprises nitrogen-doped silicon carbide.
In some embodiments of the present application, the material of the second barrier layer includes silicon oxide, and the material of the sidewall spacer includes silicon nitride.
In some embodiments of the present application, the process for forming the second barrier layer is TEOS deposition.
In some embodiments of the present application, the first barrier layer has a thickness of 200 to 600 angstroms and the second barrier layer has a thickness of about 150 to 250 angstroms.
According to the semiconductor structure and the forming method thereof, the second barrier layer is formed on the surface of the first barrier layer, and in the process of forming the side wall, the material of the side wall can be higher than the etching selection ratio of the second barrier layer, so that the etching loss of the first barrier layer is avoided, and the etching loss of the first barrier layer is smaller. In addition, the sum of the thicknesses of the first barrier layer and the second barrier layer can be designed to be equal to the preset thickness of the barrier layer in the non-RRAM logic unit, and the material of the sum is correspondingly the same as that of the barrier layer in the non-RRAM logic unit, so that the forming process of the non-RRAM logic unit does not need to be adaptively adjusted.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
figure 1 is a flow chart of a method of forming a semiconductor structure provided in accordance with some embodiments of the present application;
fig. 2-12 are schematic structural views of steps in a method of forming a semiconductor structure according to some embodiments of the present application.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
Figure 1 is a flow chart of a method of forming a semiconductor structure provided in accordance with some embodiments of the present application. Referring to fig. 1, a method for forming a semiconductor structure according to an embodiment of the present disclosure includes:
step S110: providing a substrate, wherein the substrate comprises a storage area and a non-storage area substrate;
step S120: sequentially forming a first barrier layer and a second barrier layer substrate on the first barrier layer on the surfaces of the storage region and the non-storage region of the substrate;
step S130: forming a first electrode layer on the storage region, the first electrode layer penetrating through the first barrier layer and the second barrier layer;
step S140: after the first electrode layer is formed, a resistance change layer and a second electrode layer located on the surface of the resistance change layer are formed, wherein the resistance change layer is located on the surface of the first electrode layer and extends to the surface of a part of the second barrier layer of the storage region;
step S150: and forming side walls on the side walls of the resistance change layer and the side walls of the second electrode layer after forming the second barrier layer.
Fig. 2-12 are schematic structural views of steps in a method of forming a semiconductor structure according to some embodiments of the present application. The above steps will be described in detail with reference to fig. 2 to 12. It should be noted that methods that perform the above and below steps in other orders also fall within the scope of the present disclosure.
The embodiment of the present application relates to the RRAM region (memory region) 10, but in order to explain that the technical solution of the present application does not affect the manufacturing process of the non-RRAM, the non-RRAM region (non-memory region) is also shown in fig. 2 to 12 as a comparison.
Referring to fig. 2, a substrate including a first dielectric layer 200, which includes a memory region 10 and a non-memory region substrate, is provided, step S110. It should be noted that the first dielectric layer 200 is a part of the substrate, and for the sake of brevity, the entire structure of the substrate is not shown in the drawings.
In some embodiments of the present application, the material of the first dielectric layer 200 may be silicon oxide (e.g., SiO)2) Low K or ultra low K dielectrics (e.g., dielectrics having a dielectric constant K less than 2). In some embodiments of the present application, the first dielectric layer 200 may be deposited on the substrate (not shown) by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
In an embodiment of the present application, the substrate is defined as a RRAM region 10 and a non-RRAM region, the RRAM region 10 including RRAM cells and the non-RRAM region including logic cells, such as CMOS devices. The substrate may also include inter-level metal structures and the like.
Referring to fig. 3, a second opening 202 is formed in the first dielectric layer 200.
In some embodiments of the present application, the second opening 202 may be formed by spin-coating a photoresist on the surface of the first dielectric layer 200, forming an opening pattern in the photoresist after an exposure and development process, etching the first dielectric layer 200 to form the second opening 202, introducing oxygen plasma after etching, and ashing to remove the remaining photoresist.
In some embodiments of the present application, a fourth opening 204 may be formed on the first dielectric layer 200 in the non-RRAM region, and the fourth opening 204 may be formed simultaneously with the second opening 202.
Referring to fig. 4, a first metal layer 210 is formed within the second opening 202. In some embodiments of the present application, the first metal layer 210 may be any interlayer metal structure in the semiconductor structure.
In some embodiments of the present application, the material of the first metal layer 210 may be a metal material such as copper (Cu), aluminum (Al), tantalum (Ta), tungsten (W), cobalt (Co), etc., or may be a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof.
In some embodiments of the present application, the first metal layer 210 may be formed in the second opening 202 by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating process, or other suitable process. When the first metal layer 210 is formed through the above process, the material deposited on the surface of the first dielectric layer 200 may be removed through a chemical mechanical polishing process.
In some embodiments of the present application, a third metal layer 211 may be formed within the fourth opening 204 in a non-RRAM region. The material and the formation process of the third metal layer 211 may be the same as those of the first metal layer 210, and the third metal layer 211 may be formed simultaneously with the first metal layer 210.
Referring to fig. 5, in step S120, a first barrier layer 220 and a second barrier layer 230 on the first barrier layer 220 are sequentially formed on the storage region and the non-storage region surface of the substrate. More specifically, a first barrier layer 220 is formed on the surface of the first dielectric layer 200 and the surfaces of the first metal layer 210 and the third metal layer 211, and then a second barrier layer 230 is formed on the surface of the first barrier layer 220.
In some embodiments of the present application, the material of the first barrier layer 220 includes Nitrogen-Doped silicon Carbide (NDC). In some embodiments of the present application, the first barrier layer 220 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, sputtering, or other suitable process. In one aspect, the first barrier layer 220 serves as a protection layer to prevent subsequent processes (e.g., etching processes) from damaging the first dielectric layer 200, the metal layers (e.g., the first metal layer 210 and the third metal layer 211) in the first dielectric layer 200, and other possible devices. On the other hand, the first barrier layer 220 may provide a process basis for forming a first electrode layer 240 (to be described in detail later), forming the first electrode layer 240 electrically connected to the first metal layer 210. In some embodiments of the present application, the first barrier layer 220 may cover the third metal layer 211 in a non-RRAM region. The first barrier layer 220 may also block the metal atoms in the first metal layer 210 from diffusing to the subsequently formed first dielectric layer, and block the metal atoms in the third metal layer 211 from diffusing to the subsequently formed first dielectric layer. The adhesion between the first barrier layer 220 and the first metal layer 210 and between the first barrier layer 220 and the third metal layer 211 is good.
In a conventional RRAM unit forming process, a first barrier layer is formed first, after the first barrier layer is formed on a resistance change layer, a second electrode layer and a mask protection layer, a side wall covering the side walls of the resistance change layer, the second electrode layer and the mask protection layer is formed, a second barrier layer is formed after the side wall is formed, and the second barrier layer is located on the surface of the first barrier layer in a non-RRAM area, on the resistance change layer in the RRAM area, on the second electrode layer, on the mask protection layer and the side wall and on the surface of the first barrier layer in the RRAM area. However, in the process of forming the side wall, the etching selection ratio of the material silicon nitride of the side wall and the material NDC of the first barrier layer is low, and the material of the side wall cannot be etched under the condition that the thickness of the first barrier layer is stable, which easily causes the first barrier layer to be greatly damaged, and may affect the function of the device.
Therefore, in the embodiment of the present application, before forming the sidewall spacer, the second barrier layer 230 is formed on the first barrier layer 220, and in the process of forming the sidewall spacer, the etching selectivity of the material of the sidewall spacer and the second barrier layer 230 is higher, so that the thickness stability of the second barrier layer 230 can be ensured.
In some embodiments of the present application, the second blocking layer 230 is made of silicon oxide, the sidewall is made of silicon nitride, and the process of etching the silicon nitride layer includes dry etching. In some embodiments of the present application, the method of forming the second barrier layer 230 includes TEOS deposition.
In some embodiments of the present application, the first barrier layer 220 has a thickness of 200 to 600 angstroms and the second barrier layer 230 has a thickness of 150 to 250 angstroms. For example, the first barrier layer 220 has a thickness of 380 angstroms and the second barrier layer 230 has a thickness of 200 angstroms.
In some embodiments of the present application, the non-RRAM regions and the second blocking layer 230 of the RRAM regions can be formed simultaneously, so that no adaptation to the process of forming the non-RRAM logic cells is required. Accordingly, the subsequent process of forming the fourth metal layer 213 (shown in fig. 12) and the plug 214 (shown in fig. 12) in the non-RRAM region also does not need to be adjusted.
Referring to fig. 6, a first opening 201 is formed in the first barrier layer 220 and the second barrier layer 230 to penetrate the first barrier layer 220 and the second barrier layer 230. The first opening 201 is located on the first metal layer 210, corresponds to the position of the first metal layer 210, and exposes only a portion of the first metal layer 210.
In some embodiments of the present application, the first opening 201 may be formed by spin-coating a photoresist on the surface of the second barrier layer 230, forming an opening pattern in the photoresist after an exposure and development process, etching the first barrier layer 220 and the second barrier layer 230 to form the first opening 201, introducing oxygen plasma after etching, and ashing to remove the remaining photoresist.
Referring to fig. 7, in step S130, a first electrode layer 240 penetrating the first barrier layer 220 and the second barrier layer 230 is formed on the memory region. The first electrode layer 240 fills the first opening 201 and is flush with the surface of the second barrier layer 230. The first electrode layer 240 is a bottom electrode layer of the RRAM cell.
In some embodiments of the present application, the material of the first electrode layer 240 may be a metal material such as tantalum (Ta), titanium (Ti), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten (W), or the like, or may be a conductive material such as tantalum nitride (TaN), titanium nitride (TiN), or the like, or any combination thereof. The first electrode layer 240 may also be a composite structure film layer including a plurality of layers of the above materials.
In some embodiments of the present application, a method of forming the first electrode layer 240 includes: a first electrode material is deposited in the first opening 201 and on the surface of the second barrier layer 230, and the deposition process includes physical vapor deposition, Chemical vapor deposition, atomic layer deposition, etc. a Chemical Mechanical Polishing (CMP) process is used to remove the first electrode material above the surface of the second barrier layer 230.
Referring to fig. 9, after the first electrode layer 240 is formed in step S140, a resistance change layer 250, a second electrode layer 260 on the surface of the resistance change layer 250, and a mask protection layer 270 on the surface of the second electrode layer 260 are formed, wherein the resistance change layer 250 is on the surface of the first electrode layer 240 and extends to a portion of the surface of the second barrier layer 230 of the memory region. Specifically, referring to fig. 8, after forming the first electrode layer 240, a resistive material layer 250a is formed on the first electrode layer 240 and the second barrier layer 230; forming a second electrode material layer 260a on the resistive material layer 250 a; a mask protection material layer 270a is formed on the second electrode material layer 260 a.
Referring to fig. 9, the mask protection material layer 270a, the second electrode material layer 260a and the resistive material layer 250a are etched through an etching process, and all the mask protection material layer 270a, the second electrode material layer 260a and the resistive material layer 250a in the non-RRAM region, and part of the mask protection material layer 270a, the second electrode material layer 260a and the resistive material layer 250a in the RRAM region are removed until the surface of the second barrier layer 230 is exposed, so that the resistive layer 250, the second electrode layer 260 and the mask protection layer 270 are formed.
The second electrode layer 260, the resistance change layer 250 and the first electrode layer 240 left after the etching process constitute a basic RRAM cell, and the device size can be set as required.
The resistive layer 250 is a resistive material layer of the RRAM cell, and the resistive layer 250 is used to form a "filament" that is considered to be the operational mechanism of the RRAM device. Meanwhile, the resistance change layer 250 also functions as an insulating medium layer between the first electrode layer 240 and the second electrode layer 260.
The resistance change layer 250 is made of a material with resistance change characteristics induced by electricity, wherein the resistance of the material can change under a specific external signal, and the resistance of the material cannot be recovered due to the removal of an electric signal after the resistance value of the material changes; the resistance of the material is reversible, the resistance of the material can be reduced by applying an electric signal in one form, and the resistance can be restored to high resistance by applying an electric signal in another form.
In some embodiments of the present application, the material of the resistance change layer 250 may be amorphous silicon, polysilicon, copper oxide, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide, or any combination thereof.
In some embodiments of the present application, the resistive material layer 250a may be formed using a chemical vapor deposition, physical vapor deposition, or atomic layer deposition process.
The second electrode layer 260 is a top electrode layer of the RRAM cell. In some embodiments of the present application, the material of the second electrode layer 260 may be a metal material such as silver (Ag), copper (Au), platinum (Pt), tungsten (W), etc., or a conductive material such as tantalum nitride (TaN), titanium nitride (TiN), etc., or any combination thereof. The second electrode layer 430 may also be a composite structure film layer including a plurality of layers of the above materials.
In some embodiments of the present application, the second electrode material layer 260a may be formed by physical vapor deposition, chemical vapor deposition (e.g., metal organic chemical vapor deposition), atomic layer deposition, electroplating, sputtering, or other suitable processes.
The mask protection layer 270 is a protection layer of the second electrode layer 260 in a subsequent etching process. In the subsequent etching process, the mask protection layer 270 may be thinned to a certain extent, but is not completely removed by etching.
The mask protection layer 270 may be a hard mask protection layer having a single-layer structure or a stacked-layer structure. In some embodiments of the present application, the material of the mask protection layer 270 is different from the material of the second barrier layer 230, and the material of the mask protection layer 270 may be silicon carbide (SiC), silicon nitride (SiN), NDC, or any combination thereof.
Referring to fig. 10, in step S150, after forming the second barrier layer 230, a sidewall spacer 280 is formed on the sidewall of the resistance change layer 250 and the sidewall of the second electrode layer 260. The sidewall spacers 280 are used to protect the RRAM unit.
In this embodiment, the sidewall spacers 280 also cover the sidewalls of the mask protection layer 270.
In some embodiments of the present application, the material of the sidewall spacers 280 includes silicon nitride, silicon carbide, and the like.
In some embodiments of the present application, the method for forming the sidewall spacers 280 includes: forming a side wall material layer on the surface of the second barrier layer 230, the side wall of the resistance change layer 250, the side wall of the second electrode layer 260 and the second electrode layer; the spacer material layer is etched back until the surface of the second barrier layer 230 is exposed, thereby forming a spacer 280.
In the embodiment of the present application, the second barrier layer 230 is formed on the first barrier layer 220, and the etching selectivity of the material for forming the sidewall 280 and the material for forming the second barrier layer 230 is higher, so that the sidewall material layer can be etched under the condition that the thickness of the second barrier layer 230 is stable.
In this embodiment, during the formation of the sidewall spacers, a portion of the second barrier layer 230 is also etched, but the loss of the second barrier layer 230 is small.
In this embodiment, after the side wall is formed, the thickness of the second barrier layer located at the bottom of the resistive layer is greater than the thickness of the second barrier layer located at the bottom of the side wall and is greater than the thickness of the second barrier layer on the non-storage region, and the side wall also extends to the surface of the side portion of the second barrier layer at the bottom of the resistive layer.
Referring to fig. 11, a second dielectric layer 290 is formed on the surface of the second barrier layer 230, the surface of the sidewall spacer 280 and the surface of the mask protection layer 270. The second dielectric layer 290 is an interlayer dielectric layer (IMD).
In some embodiments of the present application, the material of the second dielectric layer 290 may be silicon oxide (e.g., SiO)2) Low K or ultra low K dielectrics (e.g., dielectrics having a dielectric constant K less than 2).
In some embodiments of the present application, the process of forming the second dielectric layer 290 includes: depositing a second dielectric layer 290 on the surface of the second barrier layer 230, the surface of the sidewall 280 and the surface of the mask protection layer 270, and performing chemical mechanical polishing on the second dielectric layer 290 to planarize the top of the second dielectric layer 290, wherein after planarization, the second dielectric layer 290 with a specific thickness still remains on the stacked structure formed by the mask protection layer 270, the second electrode layer 260 and the resistance change layer 250, and is used for forming a second metal layer 212 (shown in fig. 12) electrically connected to the second electrode layer 260 therein.
In some embodiments of the present disclosure, the second dielectric layer 290 may be deposited on the surfaces of the second barrier layer 230, the sidewalls 280 and the mask protection layer 270 by physical vapor deposition, chemical vapor deposition or atomic layer deposition.
Referring to fig. 12, a second metal layer 212 penetrating through the second dielectric layer 290 and the mask protection layer 270 is formed, and the second metal layer 212 is in contact with the second electrode layer 260.
In some embodiments of the present application, the material of the second metal layer 212 may be a metal material such as copper (Cu), aluminum (Al), tantalum (Ta), tungsten (W), cobalt (Co), etc., or a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof.
In some embodiments of the present application, a method of forming the second metal layer 212 includes: forming a third opening penetrating through the second dielectric layer 290 and the mask protection layer 270, wherein the bottom of the third opening exposes the second electrode layer 260; the second metal layer 212 is formed in the third opening by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating process, or other suitable process.
In some embodiments of the present application, a fifth opening and a sixth opening may be formed in a non-RRAM region, the fifth opening and the sixth opening penetrate and a bottom of the fifth opening exposes the third metal layer 211. In some embodiments of the present application, in a non-RRAM region, a plug 214 may be formed within the fifth opening and a fourth metal layer 213 may be formed within the sixth opening.
In some embodiments of the present application, the material of the plug 214 may be a metal material such as copper (Cu), aluminum (Al), tantalum (Ta), tungsten (W), cobalt (Co), etc., or a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof. The plug 214 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating process, or other suitable process. The material and the formation process of the fourth metal layer 213 may be the same as those of the second metal layer 212.
Embodiments of the present application also provide a semiconductor structure, comprising: a substrate comprising a storage region and a non-storage region; a first barrier layer 220 on the surface of the substrate; a second barrier layer 230 on the surface of the first barrier layer 220; a first electrode layer 240 penetrating the first barrier layer 220 and the second barrier layer 230 of the storage region; the resistance change layer 250 is positioned on the surface of the first electrode layer 240 and extends to part of the surface of the second barrier layer 230 of the storage region; the second electrode layer 260 is positioned on the surface of the resistance change layer 250; and a sidewall 280, wherein the sidewall 280 covers the sidewall of the resistance change layer 250 and the sidewall of the second electrode layer 260 and is located on the second barrier layer 230 of the storage region. .
Referring to fig. 12, the first dielectric layer 200 is a portion of a substrate, and the entire structure of the substrate is not shown in the drawings for the sake of brevity.
In some embodiments of the present application, the material of the first dielectric layer 200 may be silicon oxide (e.g., SiO)2) Low K or ultra low K dielectrics (e.g., dielectrics having a dielectric constant K less than 2).
In an embodiment of the present application, the substrate is defined as a RRAM region 10 and a non-RRAM region, the RRAM region 10 including RRAM cells and the non-RRAM region including logic cells, such as CMOS devices. The substrate may also include inter-level metal structures and the like.
Referring to fig. 12, a first metal layer 210 is formed on the surface of the first dielectric layer 200, and the first metal layer 210 is in contact with the first electrode layer 240. In some embodiments of the present application, the first metal layer 210 may be any interlayer metal structure in the semiconductor structure.
In some embodiments of the present application, the material of the first metal layer 210 may be a metal material such as copper (Cu), aluminum (Al), tantalum (Ta), tungsten (W), cobalt (Co), etc., or may be a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof.
In some embodiments of the present disclosure, a third metal layer 211 may be formed on the surface of the first dielectric layer 200 in the non-RRAM region. The material and the formation process of the third metal layer 211 may be the same as those of the first metal layer 210, and the third metal layer 211 may be formed simultaneously with the first metal layer 210.
In some embodiments of the present application, the material of the first barrier layer 220 includes Nitrogen-Doped silicon Carbide (NDC). In one aspect, the first barrier layer 220 serves as a protection layer to prevent subsequent processes (e.g., etching processes) from damaging the first dielectric layer 200, the metal layers (e.g., the first metal layer 210 and the third metal layer 211) in the first dielectric layer 200, and other possible devices. On the other hand, the first barrier layer 220 may provide a process basis for forming a first electrode layer 240 (to be described in detail later), forming the first electrode layer 240 electrically connected to the first metal layer 210. In some embodiments of the present application, the first barrier layer 220 may cover the third metal layer 211 in a non-RRAM region.
In this embodiment, the first barrier layer is further located on the surface of the first dielectric layer and a part of the surface of the first metal layer.
In some embodiments of the present disclosure, the second barrier layer 230 is made of silicon oxide, and the sidewall spacer is made of silicon nitride.
In some embodiments of the present application, the first barrier layer 220 has a thickness of 200 to 600 angstroms and the second barrier layer 230 has a thickness of 150 to 250 angstroms. For example, the first barrier layer 220 has a thickness of 380 angstroms and the second barrier layer 230 has a thickness of 200 angstroms.
The semiconductor structure further includes: the mask protection layer is positioned on the surface of the second electrode layer, and the material of the mask protection layer is different from that of the second barrier layer; the side wall is also positioned on the side wall of the mask protection layer.
In some embodiments of the present application, the thickness of the second barrier layer 230 at the bottom of the resistance change layer 250 is greater than the thickness of the second barrier layer 230 at the bottom of the sidewall spacers 280 and greater than the thickness of the second barrier layer 230 on the non-storage region; the sidewall spacers 280 also extend to the side surfaces of the second barrier layer 230 at the bottom of the resistance change layer 250. The sidewall spacers 280 may completely protect the resistive layer 250 and the second electrode layer 260.
In some embodiments of the present application, the material of the first electrode layer 240 may be a metal material such as tantalum (Ta), titanium (Ti), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten (W), or the like, or may be a conductive material such as tantalum nitride (TaN), titanium nitride (TiN), or the like, or any combination thereof. The first electrode layer 240 may also be a composite structure film layer including a plurality of layers of the above materials.
The resistive layer 250 is a resistive material layer of the RRAM cell, and the resistive layer 250 is used to form a "filament" that is considered to be the operational mechanism of the RRAM device. Meanwhile, the resistance change layer 250 also functions as an insulating medium layer between the first electrode layer 240 and the second electrode layer 260.
The resistance change layer 250 is made of a material with resistance change characteristics induced by electricity, wherein the resistance of the material can change under a specific external signal, and the resistance of the material cannot be recovered due to the removal of an electric signal after the resistance value of the material changes; the resistance of the material is reversible, the resistance of the material can be reduced by applying an electric signal in one form, and the resistance can be restored to high resistance by applying an electric signal in another form.
In some embodiments of the present application, the material of the resistance change layer 250 may be amorphous silicon, polysilicon, copper oxide, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide, or any combination thereof.
The second electrode layer 260 is a top electrode layer of the RRAM cell. In some embodiments of the present application, the material of the second electrode layer 260 may be a metal material such as silver (Ag), copper (Au), platinum (Pt), tungsten (W), etc., or a conductive material such as tantalum nitride (TaN), titanium nitride (TiN), etc., or any combination thereof. The second electrode layer 430 may also be a composite structure film layer including a plurality of layers of the above materials.
The second electrode layer 260, the resistance change layer 250 and the first electrode layer 240 constitute a basic RRAM cell, and the device size thereof may be set as desired.
In some embodiments of the present application, a mask protection layer 270 is further formed on the surface of the second electrode layer 260, and a material of the mask protection layer is different from a material of the second barrier layer; the side wall is also positioned on the side wall of the mask protection layer.
The mask protection layer 270 may be a hard mask protection layer having a single-layer structure or a stacked-layer structure. In some embodiments of the present application, the material of the mask protection layer 270 may be silicon carbide (SiC), silicon nitride (SiN), NDC, or any combination thereof.
The sidewall spacers 280 are used to protect the RRAM unit.
In some embodiments of the present application, the material of the sidewall spacers 280 includes silicon nitride, silicon carbide, and the like.
The semiconductor structure further includes: a second dielectric layer 290 covering the second barrier layer 230, the sidewall spacers 280 and the mask protection layer 270; and the second metal layer penetrates through the second dielectric layer on the second electrode layer and the mask protection layer and is electrically contacted with the second electrode layer.
The second dielectric layer 290 is an interlayer dielectric layer (IMD).
In some embodiments of the present application, the material of the second dielectric layer 290 may be silicon oxide (e.g., SiO)2) Low K or ultra low K dielectrics (e.g., dielectrics having a dielectric constant K less than 2).
The second metal layer 212 penetrates through the second dielectric layer 290 and the mask protection layer 270, and the second metal layer 212 is in contact with the second electrode layer 260.
In some embodiments of the present application, the material of the second metal layer 212 may be a metal material such as copper (Cu), aluminum (Al), tantalum (Ta), tungsten (W), cobalt (Co), etc., or a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof.
In some embodiments of the present application, in the non-RRAM region, a plug 214 is formed on a surface of the third metal layer 211, and a fourth metal layer 213 is formed on a surface of the plug 214.
In some embodiments of the present application, the material of the plug 214 may be a metal material such as copper (Cu), aluminum (Al), tantalum (Ta), tungsten (W), cobalt (Co), etc., or a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination thereof. The material and the formation process of the fourth metal layer 213 may be the same as those of the second metal layer 212.
In the semiconductor structure, the second barrier layer 230 is formed on the surface of the original first barrier layer 220, and the etching selectivity of the material of the side wall 280 and the second barrier layer 230 is higher, so that the silicon nitride layer can be etched under the condition of ensuring the stable thickness of the second barrier layer 230; in addition, the first barrier layer 220 and the second barrier layer 230 of the non-RRAM region and the RRAM region can be formed simultaneously, so that there is no need to adapt the forming process of the non-RRAM logic cell.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
Claims (19)
1. A semiconductor structure, comprising:
a substrate comprising a storage region and a non-storage region;
the first barrier layer is positioned on the surface of the substrate;
the second barrier layer is positioned on the surface of the first barrier layer;
a first electrode layer penetrating the first barrier layer and the second barrier layer of the storage region;
the resistance change layer is positioned on the surface of the first electrode layer and extends to the surface of part of the second barrier layer of the storage region;
the second electrode layer is positioned on the surface of the resistance change layer;
and the side wall covers the side wall of the resistance change layer and the side wall of the second electrode layer and is positioned on the second barrier layer of the storage region.
2. The semiconductor structure of claim 1, wherein the substrate comprises:
a first dielectric layer;
the first metal layer is positioned in the first medium layer of the storage area and is in contact with the first electrode layer;
the first barrier layer is also positioned on the surface of the first medium layer and the surface of part of the first metal layer.
3. The semiconductor structure of claim 1, further comprising: the mask protection layer is positioned on the surface of the second electrode layer, and the material of the mask protection layer is different from that of the second barrier layer; the side wall is also positioned on the side wall of the mask protection layer.
4. The semiconductor structure of claim 3, further comprising:
the second dielectric layer covers the second barrier layer, the side wall and the mask protective layer;
and the second metal layer penetrates through the second dielectric layer on the second electrode layer and the mask protection layer and is electrically contacted with the second electrode layer.
5. The semiconductor structure of claim 3, wherein a material of the mask protection layer comprises silicon nitride.
6. The semiconductor structure of claim 1, wherein the material of the first barrier layer comprises nitrogen-doped silicon carbide.
7. The semiconductor structure of claim 1, wherein the second barrier layer is made of silicon oxide and the sidewall spacers are made of silicon nitride.
8. The semiconductor structure of claim 1, wherein the first barrier layer has a thickness of 200 to 600 angstroms and the second barrier layer has a thickness of about 150 to 250 angstroms.
9. The semiconductor structure of claim 1, wherein the substrate has a third metal layer in a non-storage region; the first barrier layer is also positioned on the surface of the third metal layer; the semiconductor structure further includes: a plug extending through the first barrier layer and the second barrier layer over the non-storage region; a fourth metal layer on top of the plug.
10. The semiconductor structure according to claim 1, wherein the thickness of the second barrier layer at the bottom of the resistive layer is greater than the thickness of the second barrier layer at the bottom of the sidewall and greater than the thickness of the second barrier layer on the non-storage region; the side wall also extends to the surface of the side part of the second barrier layer at the bottom of the resistive random access layer.
11. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a storage region and a non-storage region;
sequentially forming a first barrier layer and a second barrier layer on the first barrier layer on the surfaces of the storage region and the non-storage region of the substrate;
forming a first electrode layer on the storage region, the first electrode layer penetrating through the first barrier layer and the second barrier layer;
after the first electrode layer is formed, a resistance change layer and a second electrode layer located on the surface of the resistance change layer are formed, wherein the resistance change layer is located on the surface of the first electrode layer and extends to the surface of a part of the second barrier layer of the storage region;
and forming side walls on the side walls of the resistance change layer and the side walls of the second electrode layer after forming the second barrier layer.
12. The method of claim 11, wherein the method of forming the sidewall spacers comprises: forming a side wall material layer on the side wall of the resistance change layer, the side wall of the second electrode layer, the surface of the second barrier layer and the second electrode layer; and etching the side wall material layer back until the surface of the second barrier layer is exposed to form the side wall.
13. The method of forming of claim 11, wherein the substrate comprises: a first dielectric layer; the first metal layer is positioned on the first medium layer of the storage area; after the first barrier layer is formed and before the first electrode layer is formed, the first barrier layer is also positioned on the surface of the first dielectric layer and the surface of part of the first metal layer.
14. The method of forming as claimed in claim 11, further comprising: before forming the side walls, forming a mask protection layer positioned on the top surface of the second electrode layer, wherein the material of the mask protection layer is different from that of the second barrier layer; after the side wall is formed, the side wall also covers the side wall of the mask protection layer; forming a second dielectric layer on the surface of the second barrier layer, the surface of the side wall and the surface of the mask protection layer; and forming a second metal layer penetrating through the second dielectric layer and the mask protection layer.
15. The method of forming in accordance with claim 14, wherein a material of said mask protection layer comprises silicon nitride.
16. The method of forming of claim 11, wherein a material of the first barrier layer comprises nitrogen-doped silicon carbide.
17. The method of claim 11, wherein the material of the second barrier layer comprises silicon oxide, and the material of the sidewall comprises silicon nitride.
18. The method of claim 11, wherein the second barrier layer is formed by TEOS deposition.
19. The method of claim 11 wherein said first barrier layer has a thickness of 200 a to 600 a and said second barrier layer has a thickness of about 150 a to 250 a.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010261486.XA CN113497183A (en) | 2020-04-03 | 2020-04-03 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010261486.XA CN113497183A (en) | 2020-04-03 | 2020-04-03 | Semiconductor structure and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113497183A true CN113497183A (en) | 2021-10-12 |
Family
ID=77995375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010261486.XA Pending CN113497183A (en) | 2020-04-03 | 2020-04-03 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113497183A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024113728A1 (en) * | 2022-11-28 | 2024-06-06 | 厦门半导体工业技术研发有限公司 | Semiconductor integrated circuit device and manufacturing method therefor |
| WO2024130965A1 (en) * | 2022-12-21 | 2024-06-27 | 厦门半导体工业技术研发有限公司 | Semiconductor device and manufacturing method therefor |
-
2020
- 2020-04-03 CN CN202010261486.XA patent/CN113497183A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024113728A1 (en) * | 2022-11-28 | 2024-06-06 | 厦门半导体工业技术研发有限公司 | Semiconductor integrated circuit device and manufacturing method therefor |
| WO2024130965A1 (en) * | 2022-12-21 | 2024-06-27 | 厦门半导体工业技术研发有限公司 | Semiconductor device and manufacturing method therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9825224B2 (en) | RRAM device | |
| US10158072B1 (en) | Step height reduction of memory element | |
| US10930845B2 (en) | Memory device and method of manufacturing the same | |
| US7566628B2 (en) | Process for making a resistive memory cell with separately patterned electrodes | |
| US20150364681A1 (en) | Nonvolatile storage device and method of producing the device | |
| CN111129292B (en) | Memory structure and method for forming the same | |
| US20190115531A1 (en) | Memory Cell Having Resistance Variable Film and Method of Making the Same | |
| US11737381B2 (en) | Resistive random access memory and method of forming the same | |
| US11678592B2 (en) | Step height mitigation in resistive random access memory structures | |
| US10651380B1 (en) | Memory devices and methods of forming the same | |
| US20210104666A1 (en) | Resistive random access memory array and manufacturing method thereof | |
| CN113497183A (en) | Semiconductor structure and forming method thereof | |
| KR20220000374A (en) | Memory device and method for fabricating the same | |
| JP2023500625A (en) | Low forming voltage non-volatile memory (NVM) | |
| CN113130738A (en) | Semiconductor structure and forming method thereof | |
| CN113557613A (en) | Nonvolatile memory device and method of manufacturing the same | |
| US11770987B2 (en) | Resistive random-access memory and method for fabricating the same | |
| JP2015146343A (en) | Nonvolatile storage device and manufacturing method of the same | |
| US11437436B2 (en) | Semiconductor device and method for forming the same | |
| US11751492B2 (en) | Embedded memory pillar | |
| US10833268B2 (en) | Resistive memory crossbar array with a multilayer hardmask | |
| US11430513B1 (en) | Non-volatile memory structure and method for low programming voltage for cross bar array | |
| US20230413582A1 (en) | Semiconductor device and method for fabricating the same | |
| US20210043836A1 (en) | Memory devices and methods for forming the same | |
| CN115472737A (en) | Memory device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |