CN102820254A - Method for manufacturing semiconductor integrated circuit - Google Patents
Method for manufacturing semiconductor integrated circuit Download PDFInfo
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- CN102820254A CN102820254A CN201110150356XA CN201110150356A CN102820254A CN 102820254 A CN102820254 A CN 102820254A CN 201110150356X A CN201110150356X A CN 201110150356XA CN 201110150356 A CN201110150356 A CN 201110150356A CN 102820254 A CN102820254 A CN 102820254A
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Abstract
The invention discloses a method for manufacturing a semiconductor integrated circuit. The method comprises the steps of firstly, providing a substrate, and forming at least one metal hard mask on the substrate; and conducting a patterning step on metal hard masks, patterning metal hard masks to form patterned metal hard masks, and then conducting water plasma treatment on patterned metal hard masks.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor integrated circuit, the manufacture method of the semiconductor integrated circuit of particularly a kind of employing metal hard mask (metal hard mask).
Background technology
In present semi-conductor industry, embedding technique has been the major technique of multi-metal intra-connection in the semiconductor integrated circuit (multi-level interconnects).Embedding technique can be sketched at first in dielectric materials layer, etching circuit pattern, then electric conducting material such as copper is inserted in this circuit pattern, and in addition planarization, and then is accomplished the making of metal interconnecting.Mode according to etched pattern in dielectric materials layer is distinguished, and embedding technique can be subdivided into preferential (trench-first) technology of groove, interlayer hole preferential (via-first), preferential (partial-via-first) technology of part interlayer hole again and aim at (self-aligned) technology etc. voluntarily.
In the substrate that comprises conductive layer, form dielectric layer structure and metal hard mask in the known embedding technique in regular turn; The hard mask of pattern metal forms opening subsequently; Carry out etch process again, the etching dielectric layer structure forms channel patterns or the interlayer hole pattern of inlaying lead through Open Side Down.It should be noted that and forming pollutants generations such as the opening or the particulate that in etch process, often drops.The particulate that drops attracts because of receiving the Van der Waals force (Van der Waals force) that produces between own and the metal hard mask, and is attached on the metal hard mask, or is attracted around metal hard mask.Even the particulate that drops that is attracted utilizes cleaning also can't easily the particulate that drops be removed, and the existence of the particulate that drops hindered the carrying out of subsequent etch technology, even causes groove opening pattern after the etching to dwindle or problem such as imperfect.More cause the follow-up metal that is formed in the groove opening that defectives such as broken string take place, reduced the reliability of metal interconnecting.
Summary of the invention
Therefore, the present invention provides a kind of manufacture method of semiconductor integrated circuit in this, is attached to metal hard mask and then causes problems such as etching is incomplete in order to solve particulate.
According to claim provided by the present invention, a kind of manufacture method of semiconductor integrated circuit is provided.This manufacture method at first provides substrate, and is formed with at least one metal hard mask in this substrate.Next this metal hard mask is carried out patterning step, this metal hard mask of patterning is to form the hard mask of pattern metal.Subsequently the hard mask of this pattern metal is carried out water plasma (H
2O plasma) handles.
According to the manufacture method of semiconductor integrated circuit provided by the present invention, after forming first opening, remove the positive charge that the hard mask of this pattern metal obtains in patterning step through the water Cement Composite Treated by Plasma.Therefore the particulate that drops that in patterning step, produces more is not vulnerable to the attraction of Van der Waals force and is attached on the hard mask of pattern metal, and is easy to be removed by cleaning.Therefore, in the follow-up etch process that carries out,, and reduce the possibility that broken string takes place the follow-up metal level of inserting no longer because the existence of the particulate that drops has influence on etching result.Briefly, the manufacture method of semiconductor integrated circuit provided by the present invention can improve the reliability of semiconductor integrated circuit effectively.
Description of drawings
Fig. 1 to Fig. 6 is the sketch map of preferred embodiment of the manufacture method of semiconductor integrated circuit provided by the present invention.
Description of reference numerals
100 substrates, 102 conductive layers
104 bottoms, 106 dielectric layers
108 cover layers, 110 metal hard masks
122 patterning photoresists, 124 openings
126 openings 128 particulate that drops
130 water Cement Composite Treated by Plasma, 140 anti-reflecting layers
142 patterning photoresists, 144 openings
146 openings, 150 groove opening
152 interlayer hole openings
Embodiment
See also Fig. 1 to Fig. 6, Fig. 1 to Fig. 6 is the sketch map of preferred embodiment of the manufacture method of semiconductor integrated circuit provided by the present invention.As shown in Figure 1, this preferred embodiment at first provides substrate 100, like silicon base, contain silicon base or silicon-coated insulated (silicon-on-insulator, SOI) substrate etc., and include conductive layer 102 and the bottom 104 that covers conductive layer 102 in the substrate 100.In this preferred embodiment, conductive layer 102 comprises metal material, and bottom 104 then comprises nitrogen doped silicon carbide (nitrogen-doped silicon carbide).In addition, substrate 100 also comprises dielectric layer 106, and as shown in Figure 1, and dielectric layer 106 covers bottom 104.Dielectric layer 106 can comprise low-k (dielectric constant; K) material (dielectric constant values is less than 3.9), ultralow dielectric (ultra low-k; Be designated hereinafter simply as ULK) material or porousness ultralow dielectric (porous ULK) material; Because advanced low-k materials, ULK material and porousness ULK material are all material not finer and close and that structural strength is lower, therefore, this preferred embodiment optionally forms fine and close cover layer 108 again on dielectric layer 106 surfaces.Cover layer 108 can be illustrated in figure 1 as and comprise silica (silicon oxide; SiO), silicon oxynitride (silicon oxynitride; SiON) or tetraethyl oxosilane (tetraethylorthosilicate, single layer structure TEOS), but also be not limited to the composite film structure.
Please continue to consult Fig. 1.Next, be in substrate 100, especially form metal hard mask 110 on the cover layer 108.Metal hard mask 110 can be single layer structure or composite film structure, and be selected from titanium (titanium, Ti), titanium nitride (titanium nitride, TiN), tantalum (tantalum, Ta), with tantalum nitride (tantalum nitride, the group that TaN) is formed.For instance, metal hard mask that this preferred embodiment provides 110 can comprise the composite film of Ti/TiN or Ta/TaN, but is not limited thereto.It should be noted that in addition; Because metal hard mask 110 has the stress with respect to dielectric layer 106; Therefore in this preferred embodiment, cover layer 108 also can be used as the buffering between metal hard mask 110 and the dielectric layer 106, avoids dielectric layer 106 directly to receive the stress influence of metal hard mask 110.As shown in Figure 1; This preferred embodiment also forms anti-reflecting layer (anti-reflective coating on metal hard mask 110; ARC) 120, anti-reflecting layer 120 can comprise dielectric material such as silicon oxynitride (SiON) or tetraethyl oxosilane (TEOS), but is not limited thereto.
In addition; In the change type of this preferred embodiment; Conductive layer 102 can comprise other electric conducting materials such as metal nitride, metal silicide or doped silicon; 108 of cover layers can comprise that (silicon nitride, SiN), silica (SiO) or silicon oxynitride (SiON), metal hard mask 110 then is directly to be formed on the cover layer 108 to silicon nitride.
Please continue to consult Fig. 1.Next, on anti-reflecting layer 120, form patterning photoresist 122, patterning photoresist 122 comprises an opening 124 at least, inlays the channel patterns of lead in order to definition.
See also Fig. 2.After forming patterning photoresist 122; Metal hard mask 110 is carried out patterning step; See through opening 124 etching anti-reflecting layers 120, the metal hard mask 110 and part of covering layer 108 of patterning photoresist 122, form the hard mask 112 of pattern metal that comprises at least one opening 126 with the hard mask 110 of pattern metal.It should be noted that after patterning step the hard mask 112 of pattern metal has electric charge, and is generally positive charge.Therefore, the particulate 128 that drops that in patterning step, produces receives the attraction of Van der Waals force and is attached to easily around the opening 126 of the hard mask 112 of pattern metal.
See also Fig. 3.After forming the hard mask 112 of pattern metal, carry out water plasma (H
2Oplasma) handle 130, remove patterning photoresist 122, anti-reflecting layer 120, and these positive charges of the hard mask 112 of pattern metal in order to coordination ground.In this preferred embodiment, at first be to feed steam (H
2O vapor) carrying out water Cement Composite Treated by Plasma 130, and the gas flow of this steam be 2000～3000 per minute standard milliliters (standard cubic centimeter per minute, sccm).Next transforming (transform) steam becomes and has reactive water plasma, in order to remove patterning photoresist 122, anti-reflecting layer 120 and positive charge.In this preferred embodiment, the process time of water Cement Composite Treated by Plasma 130 between 15 seconds and 60 seconds, its operation pressure between 3000 milli-torrs (mTorr) and 9000 milli-torrs and its technological temperature between 25 ℃～350 ℃.Because water Cement Composite Treated by Plasma 130 is for having removed the positive charge of the hard mask 112 of pattern metal; Therefore the particulate 128 that drops no longer receives the attraction of Van der Waals force and is attached near the opening 126 of the hard mask 112 of pattern metal, and is removed by follow-up cleaning of carrying out easily.It should be noted that in addition that in water Cement Composite Treated by Plasma 130 and follow-up cleaning step dielectric layer 106 is still by comparatively fine and close 108 protections of cover layer.
In addition, in this preferred embodiment, also be not limited to before water Cement Composite Treated by Plasma 130, carry out oxygen plasma (O earlier
2Plasma) handle, can remove fully to guarantee patterning photoresist 122 and anti-reflecting layer 120.In addition, in order to remove the positive charge of the hard mask 112 of pattern metal effectively, also can comprise negative electrical charge in the water Cement Composite Treated by Plasma 130 that this preferred embodiment provided.In addition, if the hard mask 112 of pattern metal has negative electrical charge behind etch process, also can comprise positive charge in the water Cement Composite Treated by Plasma 130 that this preferred embodiment provided.
See also Fig. 4.After water Cement Composite Treated by Plasma 130, carry out aforesaid cleaning (figure does not show), remove with particulate 128 grades that will drop, on the hard mask 112 of pattern metal, form anti-reflecting layer 140 and patterning photoresist 142 subsequently again.As shown in Figure 4, anti-reflecting layer 140 fills up opening 126, and patterning photoresist 142 then has the opening 144 corresponding to opening 126 positions, is arranged in opening 126 scopes, inlays the interlayer hole pattern of lead in order to definition.
See also Fig. 5.Next utilize patterning photoresist 142 as etching mask; See through opening 144 downward etching anti-reflecting layers 140, the cover layer 108 and part dielectric layer 106 of patterning photoresist 142; And form another opening 146 in the first half of dielectric layer 106; Opening 146 is corresponding to opening 126, in order to as a part of interlayer hole.After the opening 146 to be formed, modes such as oxygen plasma capable of using are removed patterning photoresist 142 and anti-reflecting layer 140.
See also Fig. 6.Next; Carry out etch process once more; Etching downwards is not patterned cover layer 108 and the dielectric layer 106 that metal hard mask 112 covers, and so that opening 126 and opening 146 are transferred in the dielectric layer 106, and in dielectric layer 106 in, forms groove opening 150 and the interlayer hole opening 152 of inlaying lead.And as shown in Figure 6, bottom 104 exposes the bottom of interlayer hole opening 152.
After the making of accomplishing groove opening 150 and interlayer hole opening 152, can remove the bottom 104 of interlayer hole opening 152 bottoms through the etch process that is fit to, and expose conductive layer 102.Subsequently; In groove opening 150 and interlayer hole opening 152, form barrier layer (figure does not show) and the conductive layer that fills up groove opening 150 and interlayer hole opening 152 (figure does not show); Remove unnecessary conductive layer and patterned metal layer 112 through planarisation step at last, accomplish the making of inlaying lead.Because above-mentioned steps is known by persons skilled in the art, therefore in this preferred embodiment, repeat no more.It should be noted that; Particulate 128 no longer receives the attraction of Van der Waals force and in cleaning, removes fully owing to drop; Therefore etch process can be transferred to opening 126 and opening 146 in the dielectric layer 106 smoothly and intactly, and forms groove opening 150 and interlayer hole opening 152.And follow-up when groove opening 150 and interlayer hole opening 152 are inserted conductive layer, electric conducting material can intactly be inserted in groove opening 150 and the interlayer hole opening 152, so can effectively avoid because of inserting the imperfect broken string problem that causes in the known technology.
In sum, the manufacture method of semiconductor integrated circuit provided by the present invention after the opening that forms in order to definition groove position, removes the positive charge that the hard mask of this pattern metal obtains through the water Cement Composite Treated by Plasma in patterning step.Therefore the particulate that drops that in patterning step, produces more is not vulnerable to the attraction of Van der Waals force and is attached on the hard mask of pattern metal, and is easy to be removed by cleaning.Therefore, in the follow-up etch process that carries out,, and reduce the possibility that broken string takes place the follow-up metal level of inserting no longer because the existence of the particulate that drops has influence on etching result.Briefly, the manufacture method of semiconductor integrated circuit provided by the present invention can improve the reliability of semiconductor integrated circuit effectively.
The above is merely the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (17)
1. the manufacture method of a semiconductor integrated circuit comprises:
Substrate is provided, is formed with at least one metal hard mask in this substrate;
Carry out patterning step, this metal hard mask of patterning is to form the hard mask of pattern metal; And
Carry out the water Cement Composite Treated by Plasma.
2. manufacture method as claimed in claim 1, wherein this metal hard mask group of being selected from titanium, titanium nitride, tantalum, forming with tantalum nitride.
3. manufacture method as claimed in claim 1, wherein the hard mask of this pattern metal includes electric charge, and this water Cement Composite Treated by Plasma is in order to remove these a plurality of electric charges of the hard mask of this pattern metal.
4. manufacture method as claimed in claim 3, wherein the hard mask of this pattern metal comprises positive charge.
5. manufacture method as claimed in claim 4 wherein also comprises negative electrical charge in this water Cement Composite Treated by Plasma.
6. manufacture method as claimed in claim 3 also is included in and forms the first patterning photoresist on this metal hard mask, in order to this metal hard mask of patterning.
7. manufacture method as claimed in claim 6, wherein this water Cement Composite Treated by Plasma be coordination remove these electric charges and this first patterning photoresist.
8. manufacture method as claimed in claim 6 also is included in and forms first anti-reflecting layer between this first patterning photoresist and this metal hard mask.
9. manufacture method as claimed in claim 1 also comprises oxygen plasma treatment, is carried out at before this water Cement Composite Treated by Plasma.
10. manufacture method as claimed in claim 1, wherein the process time of this water Cement Composite Treated by Plasma is between 15 seconds and 60 seconds.
11. manufacture method as claimed in claim 1, wherein this water Cement Composite Treated by Plasma comprises that also feeding steam carries out this water Cement Composite Treated by Plasma, and the gas flow of this steam is 2000～3000 per minute standard milliliters.
12. manufacture method as claimed in claim 1, wherein the operation pressure of this water Cement Composite Treated by Plasma is between 3000 milli-torrs and 9000 milli-torrs.
13. manufacture method as claimed in claim 1, wherein the technological temperature of this water Cement Composite Treated by Plasma is between 25 ℃～350 ℃.
14. manufacture method as claimed in claim 1 wherein also comprises conductive layer and bottom in this substrate, and this bottom covers this conductive layer.
15. manufacture method as claimed in claim 14 wherein also comprises dielectric layer and cover layer in regular turn in this substrate, and this dielectric layer covers this bottom.
16. manufacture method as claimed in claim 15, wherein the hard mask of this pattern metal also comprises at least one first opening, and this cover layer is exposed to the bottom of this first opening.
17. manufacture method as claimed in claim 16 is further comprising the steps of, is carried out at after this water Cement Composite Treated by Plasma:
On the hard mask of this pattern metal, form second anti-reflecting layer and the second patterning photoresist in regular turn; And
See through this this second anti-reflecting layer of second patterning photoresist etching, this cover layer and this dielectric layer, and form at least one second opening, and this second opening is corresponding to this first opening.
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| CN201110150356.XA CN102820254B (en) | 2011-06-07 | 2011-06-07 | The manufacture method of semiconductor integrated circuit |
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| CN201110150356.XA CN102820254B (en) | 2011-06-07 | 2011-06-07 | The manufacture method of semiconductor integrated circuit |
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Cited By (5)
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| US20120302068A1 (en) * | 2011-05-24 | 2012-11-29 | Chun-Lung Chen | Method for manufacturing semiconductor integrated circuit |
| CN104576512A (en) * | 2013-10-28 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Processing method capable of preventing electrochemical corrosion of through-hole metals |
| CN106952863A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN111919284A (en) * | 2018-03-01 | 2020-11-10 | 应用材料公司 | System and method for forming metal hard mask in device fabrication |
| WO2022048224A1 (en) * | 2020-09-03 | 2022-03-10 | 长鑫存储技术有限公司 | Preparation method for metal connection line |
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| US20120302068A1 (en) * | 2011-05-24 | 2012-11-29 | Chun-Lung Chen | Method for manufacturing semiconductor integrated circuit |
| US8735301B2 (en) * | 2011-05-24 | 2014-05-27 | United Microelectronics Corp. | Method for manufacturing semiconductor integrated circuit |
| CN104576512A (en) * | 2013-10-28 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Processing method capable of preventing electrochemical corrosion of through-hole metals |
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| CN106952863B (en) * | 2016-01-06 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN111919284A (en) * | 2018-03-01 | 2020-11-10 | 应用材料公司 | System and method for forming metal hard mask in device fabrication |
| WO2022048224A1 (en) * | 2020-09-03 | 2022-03-10 | 长鑫存储技术有限公司 | Preparation method for metal connection line |
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