A7 B7 五、發明說明（I ) 【發明所靥之技術領域】 <-請先Mtl背面之it意事項再填寫本頁) 近年，隨著半導體裝置之微細化及積體化之要求，力 求達成多層配線化。作爲達成多層配線化之技術，例如有 下列技術· Λ 茲使用第7圖〜第9圓說明欲達成多層配線化之技術 如下。 首先，邊參照第7圖說明之*形成半導體元件等之半 導體基板2 1 0上，形成第1層間絕緣層2 1 2。在第1 層間絕緣層2 1 2上，例如依序形成導電層（例如鋁合金 )222及反射防止膜（例如氮化鈦）224。接著，由 光刻成像法（photolithgraph )及乾触刻，將導電層2 2 2 與反射防止膜2 2 4形成圖案，來形成下部配線層2 2 0 。在下部配線層2 2 0及第1層間絕緣層2 1 2上，形成 第2層間絕緣層230。 經濟部智慧財產局S工消费合作社印製 如第8圖所示，在第2層間絕緣層2 3 0上，藉光刻 成像法，形成具有既定圖案之抗蝕會R 2。抗蝕層R 2係 於欲形成貫通孔之領域上方具有開口部。將抗蝕層R 2作 爲光罩，將第2層間絕緣層2 3 0乾蝕刻，而形成抵達下 部配線層220之貫通孔240。貫通孔240係具有連 接下部配線層2 2 0與後述上部配線層2 6 0之功能。 如第9圖所示，在貫通孔2 4 0內塡充導電材，來形 成接觸層2 5 0 »第2層間絕緣層2 3 0及接觸層2 5 0 上，依序形成導電層2 6 2及反射防止膜2 6 4。藉光刻 成像法及乾蝕刻，將導電層2 6 2及反射防止層2 6 4形 私紙張尺度適用中國S家標準（CNS>A4规格（210 X 297公釐） 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明說明G ) 成圖案，以形成上部配線層2 6 0。如以上，就可達成多 層配線化· ’ 又，近年由於因應更加微細化及多層化之要求，將配 '線層之圖案寬度，成爲與貫逋孔240之寬度相同程度狹 窄之技術受到注目。但是，隨著配線層之.圖案寬度之變窄 ，起因於抗蝕層R 2之圖案配合發生偏移，對於配線層之 可靠性發生不良影響。亦即，在發生抗蝕層R 2之圖案配 合偏移狀態下，爲了欲形成貫通孔2 4 0所需而蝕刻第2 層間絕緣層230時，則因過度之蝕刻，就如第8圖所示 ，於第1電線層2 2 0之側壁附近會發生溝渠（trench ) 2 3 2。若有溝渠2 3 2時，欲將構成接觸層2 5 0之導 電材塡充於貫通孔2 4 0時，會發生下列之問題。亦即， 因欲將導電材塡充於溝渠會變成困難，所以，如第9圖所 示，會發生起因於溝渠2 3 2之空隙（void ) 2 7 0。此 空隙2 7 0將明顯地降低配線層之可靠性。 即使發生抗蝕層R 2之圖案配^偏移，也可防止發生 空隙270之技術，例如，有曰本特開平9一 2 9 8 2 3 9號公報所掲示之技術· 茲簡單說明這種技術如下* 此項技術係在上述層間絕緣膜施加乾蝕刻以形成連接 孔（貫通孔）時，就將蝕刻氣體與反射防止膜之反應生成 物，再附著於連接孔底部，來防止發生溝渠。也就是說， 將蝕刻氣體與运射防止膜之反應生成物再附著於連接孔底 部，即使發生抗蝕層之圖案配合偏移，也可抑制蝕刻之過 — — — — — — —--''裝--- I I 訂.I 111 _-線 I (‘靖先《讀背面之注意事項再填寫本頁) 表紙張尺度適用中0S家禕準（CNS)A4規格（210* 297公t ) -5- 417257 A7 B7_ ' - 五、發明說明0 ) 度進行•所以，可防止溝渠之形成，其結果.在連接孔就 不會發生空隙。 <·請先閲讀背面之注意事項再填窝本頁) 但是，這種技術係形成連接孔後，需要去除所發生反 '應生成物之製程。又，反應生成物之去除爲困難之事。 【發明所欲解決之問題】 本發明之目的，係提供一種具有高可靠性之配線層之 半導體裝置及其製造方法 【解決問題之手段】 本發明之半導體裝置，係包括： 第1配線層，與 形成在上述第1配線層上之層間絕緣層，與 形成在上述層間絕緣層上之第2配線層，與 連接上述第1配線層與上述第2配線層所需之複數貫 通孔，與 ~ 形成於上述複數貫通孔內之接觸層， 經濟部智慧財產局貝工消费合作社印製 至少1個貫通孔，係至少去除上述第1配線層之一部 分所構成，並且，其底面係由上述層間絕緣層之面與上述 第1配線層之面所構成之連續面' 本發明之半導體裝置，係至少於1個貫通孔*導電層 之面與層間絕緣層之面爲構成連續面。因此，在構成連續 面之貫通孔內，欲埋入構成接觸層之導電材時，就可將導 電材良好地埋入於其貫通孔內。其結果，本發明之半導體 本紙張尺度適用中國困家標準<CNS)A4規格（210x297公釐〉 -6· 417, A7 B7 五、發明說明f ) 裝置，其配線層之可靠性高。 <·請先閱讀背面之注意事項再瑱寫本頁) 作爲上述建續面之態樣，例如可舉出，平面，曲面或 具有曲面之態樣》 上述第1配線層，係可由矽及金屬層之至少一方所構 成。 本發明之半導體裝置，係例如可由下列之半導體裝置 之製造方法所製造。亦即，本發明之半導體裝置之製造方 法爲包括下列事項： - (A)形成第1配線層之製程， (B )在上述第1配線層上，形成層間絕緣層之製程 (C )在上述層間絕緣層之既定位置，形成抵達上述 第1配線層之複數貫通孔之製程，及 (D )在上述複數貫通孔內形成接觸層，在上述層間 絕緣層上形成第2配線層之製程， 經濟部智慧财產局貝工消费合作社印製 於上述製程所形成之至少1個貪通孔，係 至少去除上述第1配線層之一部分所構成者，其底面 爲由上述層間絕緣層之面與上述第1配線層之面所構成之 連續面。 像這樣，在至少1個貫通孔之底面，由於層間絕緣層 之面，與第1配線層之面構成爲連續面，就可將構成導電 層之導電材良好地埋入於其貫通孔內。其結果，由本發明 之製造所獲得之半導體裝置之配線層之可靠性爲高* 上述至少1個貫通孔，係例如可由下列2個之任一方 良紙張尺度適用_ B國家標準（CNS)A4規格<210 * 297公* ) 經濟部智慧財產局貝工消费合作杜印製 417257 A7 __ _&_…- 五、發明說明0 ) 法所形成。 (1 )第1，上述至少1個貫通孔，係將上述第1配 線層之一部分與上述層間絕緣層之一部分同時蝕刻所形成 '之方法。作爲上述蝕刻之蝕刻方法，例如可舉出，反應離 子蝕刻（RIE Reactive Ion Etching )，感應結合型電漿蝕刻 (inductively-coupled plasma etching ) ，ECR 電漿独刻 (electron cycloton resonance plasma etching ) 0 上述融刻 之腐蝕劑（etchant )，例如可舉出含有CF系之混合氣體 。作爲CF系之氣體，例如可舉出C.F4，CHF3， C2F6，C4F8，c5f8。於上述蝕刻，對於上述層間絕 緣層之上述第1配線層之選擇比（第1配線層之蝕刻速度 /層間絕緣層之蝕刻速度）若位於0 . 5〜2 . 0之範圍 ，就可形成更加良好之連續面。 (2 )第2，上述至少1個貫通孔*係蝕刻上述層間 絕緣層之一部分*並且，蝕刻上述第1配線層之一部分所 形成之方法。作爲上述第1配線層έ一部分之鈾刻之蝕刻 方法，係可舉出感應型結合型電漿蝕刻，下流電漿蝕刻（ downflow plasma etching )，反應離子餓刻。作爲上述第1 配線層之一部分之蝕刻之腐蝕劑，則可舉出包含氯系氣體 之混合氣體》 按，上述連續面係於貫通孔之底面，層間絕緣層之面 與第1配線層之面，爲即使構成具有微視性髙低差之凹凸 之情形，也包含可良好地塡充導電材於貫通孔程度之面。 — — — I I I ! 1!酿 II i C請先閱讀背》之注意事項再填寫本頁) 本紙張尺度適用t國B家標準（CNS)A4規格<210 X 297公釐〉 -8- 經 濟 邨 智 慧 財 產 局 工 消 t 合 作 社 印 製 417:57 A7 __^_" 五、發明說明麥) 【發明之實施形態】 茲就本發明之較佳實施形態，邊參照圖面說明如下。 (第1實施形態） '' (裝置之構造） 茲就有關本實施形態之半導體裝置說明如下。第1圖 係有關本實施形態之半導體裝置以模式表示之剖面圖。 在半導體裝置1 0 0之基板1 0之表面，形成有 MO S F Ε Τ等半導體元件，配線層及元件及元件分離領 域（沒有圖示）。在基板10上，形成有第1層間絕緣層 1 2。在第1層間絕緣層1 2上，形成有第1配線層20 。第1配線層2 0係由導電層2 2，與形成在導電層2 2 上之反射防止膜2 4所構成，而以既定之圖案形成圖案。 在第1層間絕緣層12形成有在基板10表面之半導體元 件或配線層，與形成有與第1配線層2 0連接之接觸孔（ 沒有圖示）。在接觸孔內形成有鈦逢塞，鋁合金層等之接 觸層（沒有圖示）。 在第1配線層2 0及第1層間絕緣層1 2上，形成有 第2層間絕緣層3 0。在第2層間絕緣層3 0之既定位置 ，形成有貫通孔4 0。於貫通孔'4 0底面，於第1配線層 上面2 0 a與第2層間絕緣層之上面3 0 a係構成連續面 。在貫通孔4 0內，形成有接觸層5 0。在第2層間絕緣 層30及接觸層50上，形成有第2配線層60 ·第2配 線層6 0係由導電層6 2，與形成在導電層6 2上之反射 參紙張尺度进用中0团家標準（CNS)A4 Λ格（210 * 297公1)~~ 一 - 9 - " 417^57 A7 B7 經濟部智慧財產局具工消费合作杜印製 五、發明說明p ) 防止膜6 4所構成。又，第2配線層6 0係經由接觸層 5 0連接於第1配線層2 0。 有關本實施形態之半導髏裝置1 〇 〇，其特徵爲，例 '如於貫通孔4 0之底面，第1配線層之上面2 0 a與第2 層間絕緣層之上面3 0 a爲構成連續面·亦即，於第1配 線層2 0之側壁附近，不具有由於第2層間絕緣層3 0之 過度蝕刻所發生之溝渠（參照背景技術）。由於第1配線 層之上面2 0 a與第2層間絕緣層之上面3 0 a構成爲連 續面，在貫通孔4 0內可良好地埋入構成接觸層5 0之導 電材。也就是說，不至於發生空隙，可在貫通孔4 0內埋 入導電材•所以，有關本實施形態之半導體裝置1 〇 〇， 係其配線層之可靠性高。又，若依據有關本實施形態之半 導體裝置1 0 0之構成，可邊確保配線層之可靠性，將配 線構造微細化，達成高積體化。 (第2實施形態） ^ (第1半導體裝置之製造方法） 茲就有關本實施形態之半導體裝置1 〇 〇之製造方法 說明如下。第2圖〜第4圖，係有關本實施形態之半導體 裝置1 0 0之製程以模式表示之剖面圖。 (1 )第1配線層之形成 首先，邊參照第2圖說明之°由一般性方法，在基板 10表面，形成半導體元件（例如1^1051?£：1') ’配線 Γ請先《讀貧面之注意事項再填寫本瓦) 本紙張尺度適用中國國家揉準<CNS)A4規格（210*297公釐） -10- r η pa Β7 五、發明說明@ ) 層及元件分離領域（沒有圖示）。在基板10上形成第1 層間絕緣層1 2。第1層間絕緣層1 2之詳細（形成方法 ，材質，膜厚），係與後述之第2層間絕緣層30相同。 閱 讀 背 面 之 注 意 事 項 再 填 寫 本 頁 _在第1層間絕緣層1 2，藉由各方異性之反應離子蝕刻（ RIE)形成接觸孔（沒有圖示）。由公知之方法，在接 觸孔內形成鈦塡塞，鋁合金層等接觸層（沒有圖示）。 在第1層間絕緣層12及接觸層上形成第1配線層 20。第1配線層20係由導電層22與反射防止膜24 所構成，例如如下地構成。 首先，在第1層間絕緣層1 2及接觸層上，形成導電 層2 2。導電層2 2之膜厚雖然依裝置之設計而異，但是 例如成爲1 00〜1 0 O'Onm »導電層22之材質並不 特別加以限制，例如可舉出鋁，銅，鋁合金*銅合金，多 結晶矽，鈦。導電層2 2之形成方法則可舉出CVD法， 噴濺（sputtering )法，澱積法，塗敷法等》 接著，在導電層22上，形成έ射防止膜24。反射 防止膜2 4之膜厚並不特別加以限制，例如爲2 0〜 經濟部智慧財產局具工消t合作社印製 1 0 0 nm。反射防止膜2 4之材質係例如爲氮化鈦，鈦 鎢。反射防止膜2 4之形成方法並不加以特別限制，若反 射防止膜2 4由氮化鈦形成時，則可適用噴濺法。若欲將 導電層2 2及反射防止膜2 4由噴濺法形成時，就將導電 層2 2及反射防止膜2 4由光刻成像法及乾蝕刻法加以形 成圖案，而形成第1配線層2 0。 -11 私紙張尺度適用中國因家標準（CNS)A4规格（210 * 297公《 ) A7 B7 五、發明說明$ ) (2 )第2層間絕緣層之形成 接著，如第3圖所示•在第1配線層2 0及第1層間 絕緣層1 2上，形成第2層間絕緣層3 0 ·第2層間絕緣 ’層3 0之膜厚，並特別加以限定，例如將第1配線層2 0 上面作爲基準具有.500〜1 5 OOnm »作爲第2層間 絕緣層3 0之材質，例如可使用氧化矽。作爲第2層間絕 緣層3 0之材質，若使用氧化矽時，氧化矽也可以含有磷 ，硼。作爲第2層間絕緣-層3 0之形成方法，例如可使用 高密度電漿CVD法，熱CVD法，電漿CVD法，常壓 CVD法，旋轉塗層法等塗敷法（利用SOG之方法）， 噴濺法，熱澱積法等。若欲由電漿C VD法形成第2層間 絕緣層3 0時，由平行平板之RF電漿CVD裝置來形成 較佳》若欲以平行平板之RF電漿CVD裝置來形成第2 層間絕緣層3 0時，作爲其氣體則可使用四乙氧矽烷（ TEOS tetraethoxycilane ) · 接著，視其需要，第2層間絕i層3 0之膜厚，例如 將第1配線層上面作爲基準，直到變成500〜1 500 nm，由CMP法將第2層間絕緣層3 0平坦化。 (3 )貫通孔之形成 ' 接著，如第4圖所示，在第2層間絕緣層3 0上，由 光刻成像法形成具有既定圖案之抗蝕層R 1。抗蝕層R 1 係於第1配線層2 0上方，具有開口部。亦即，抗蝕層 R 1係在欲形成貫通孔4 0之第2層間絕緣層3 0領域上 0請先Μ讀背面之>i意事項再填寫本頁) -裝 訂---------線 - 經濟部智慧財產局霣工湳费合作杜印製 本紙張尺度適用中國國家標準(CNS>A4规格（210 * 297公釐） -12-A7 B7 V. Description of the Invention (I) [Technical Fields of the Invention] < -Please fill in this page on the back of Mtl before filling in this page) In recent years, with the requirements of miniaturization and integration of semiconductor devices, we strive to Achieve multilayer wiring. As a technique for achieving multilayer wiring, for example, the following techniques are described below: The techniques for achieving multilayer wiring using Figures 7 to 9 are described below. First, a first interlayer insulating layer 2 1 2 is formed on a semiconductor substrate 2 1 0 where semiconductor elements and the like are described with reference to FIG. 7. On the first interlayer insulating layer 2 1 2, for example, a conductive layer (for example, aluminum alloy) 222 and an anti-reflection film (for example, titanium nitride) 224 are sequentially formed. Next, the conductive layer 2 2 2 and the antireflection film 2 2 4 are patterned by a photolithgraph and dry contact etch to form a lower wiring layer 2 2 0. A second interlayer insulating layer 230 is formed on the lower wiring layer 2 2 0 and the first interlayer insulating layer 2 12. Printed by Intellectual Property Co., Ltd. of the Intellectual Property Bureau of the Ministry of Economic Affairs. As shown in Fig. 8, a resist pattern R 2 having a predetermined pattern is formed on the second interlayer insulating layer 230 by photolithography. The resist R 2 has an opening above a region where a through hole is to be formed. The resist layer R 2 is used as a photomask, and the second interlayer insulating layer 230 is dry-etched to form a through-hole 240 reaching the lower wiring layer 220. The through hole 240 has a function of connecting the lower wiring layer 220 and an upper wiring layer 260 described later. As shown in FIG. 9, a conductive material is filled in the through hole 2 4 0 to form a contact layer 2 5 0 »A conductive layer 2 6 is sequentially formed on the second interlayer insulating layer 2 3 0 and the contact layer 2 5 0. 2 和 Anti-reflective film 2 6 4 By photolithography and dry etching, the conductive paper layer 2 6 2 and the anti-reflection layer 2 6 4 are applied to the standard of Chinese paper (CNS > A4 specification (210 X 297 mm).) The cooperative prints A7 B7 V. Description of the invention G) Patterning to form the upper wiring layer 260. As described above, multi-layer wiring can be achieved. In addition, in recent years, in response to the demand for more miniaturization and multilayering, the technology of matching the pattern width of the wire layer to the same degree as the width of the through-hole 240 has attracted attention. However, as the pattern width of the wiring layer becomes narrower, the pattern matching due to the resist layer R 2 shifts, which adversely affects the reliability of the wiring layer. That is, in a state where the pattern matching of the resist layer R 2 is shifted, when the second interlayer insulating layer 230 is etched in order to form the through holes 2 4 0, the excessive etching is performed as shown in FIG. 8. It is shown that a trench 2 3 2 occurs near the sidewall of the first wire layer 2 2 0. If there is a trench 2 3 2 and the conductive material constituting the contact layer 2 50 is filled in the through hole 2 4 0, the following problems occur. That is, since it becomes difficult to fill the trench with the conductive material, as shown in FIG. 9, a void 2 7 0 due to the trench 2 3 2 occurs. This gap 2 70 will significantly reduce the reliability of the wiring layer. Even if the pattern of the resist layer R 2 is shifted, the gap 270 can be prevented. For example, there is a technique shown in Japanese Patent Application Laid-Open No. 9-2 9 8 2 3 9 The technology is as follows * This technology is to prevent the occurrence of trenches by attaching the reaction product of the etching gas and the antireflection film to the connection hole (through hole) when dry etching is applied to the interlayer insulating film to form a connection hole. In other words, the reaction product of the etching gas and the transport prevention film is re-attached to the bottom of the connection hole, and even if the pattern of the resist layer is misaligned, the etching process can be suppressed. — — — — — — — — ' 'Equipment --- II Order. I 111 _-Line I (' Jing Xian "Read the precautions on the back side and then fill out this page) The paper size is applicable in the 0S furniture standard (CNS) A4 specification (210 * 297 g t) -5- 417257 A7 B7_ '-V. Description of the invention 0) Degrees • Therefore, the formation of trenches can be prevented, and as a result, voids do not occur in the connection holes. < Please read the precautions on the back before filling this page) However, this technique is a process of removing the reaction product after forming the connection hole. Removal of the reaction product is difficult. [Problems to be Solved by the Invention] The object of the present invention is to provide a semiconductor device having a highly reliable wiring layer and a method for manufacturing the same. [Means for solving the problem] The semiconductor device of the present invention includes: a first wiring layer, With the interlayer insulating layer formed on the first wiring layer, and the second wiring layer formed on the interlayer insulating layer, and a plurality of through holes required to connect the first wiring layer and the second wiring layer, and ~ The contact layer formed in the plurality of through-holes is printed by at least one through-hole in the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, which is formed by removing at least a part of the first wiring layer, and the bottom surface is insulated by the interlayer The continuous surface formed by the surface of the layer and the surface of the first wiring layer described above. The semiconductor device of the present invention is a surface that is continuous with at least one surface of the through-hole * conductive layer and the surface of the interlayer insulating layer. Therefore, when the conductive material constituting the contact layer is to be buried in the through hole constituting the continuous surface, the conductive material can be well buried in the through hole. As a result, the semiconductor paper sheet of the present invention is compliant with the Chinese Standard for Standards < CNS) A4 (210x297 mm> -6 · 417, A7 B7. 5. Description of the Invention) The device has high reliability of the wiring layer. < Please read the precautions on the back before writing this page) As examples of the above-mentioned continuous surface, for example, flat, curved, or with curved surfaces. The first wiring layer mentioned above can be made of silicon and It is composed of at least one of the metal layers. The semiconductor device of the present invention can be manufactured, for example, by the following method of manufacturing a semiconductor device. That is, the method for manufacturing a semiconductor device of the present invention includes the following matters:-(A) a process for forming a first wiring layer, (B) a process for forming an interlayer insulation layer (C) on the first wiring layer described above A process of forming a plurality of through holes that reach the first wiring layer at a predetermined position of the interlayer insulating layer, and (D) forming a contact layer in the plurality of through holes, and a process of forming a second wiring layer on the interlayer insulating layer, which is economical The Ministry of Intellectual Property Bureau Shellfish Consumer Cooperative printed at least one through hole formed in the above process, which is formed by removing at least a part of the first wiring layer, and the bottom surface is the surface of the interlayer insulation layer and the above Continuous surface formed by the surface of the first wiring layer. As described above, since the surface of the interlayer insulating layer and the surface of the first wiring layer are continuous on the bottom surface of at least one through hole, the conductive material constituting the conductive layer can be well buried in the through hole. As a result, the reliability of the wiring layer of the semiconductor device obtained by the manufacturing of the present invention is high. * The at least one through-hole mentioned above can be applied to, for example, one of the following two good paper sizes. B National Standard (CNS) A4 Specification < 210 * 297 public *) Printed 417257 A7 __ _ & _...- 5. Description of the Invention 0) formed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperation. (1) First, the at least one through-hole is formed by simultaneously etching a part of the first wiring layer and a part of the interlayer insulating layer. Examples of the etching method for the above-mentioned etching include reactive ion etching (RIE Reactive Ion Etching), inductively-coupled plasma etching, and ECR (electron cycloton resonance plasma etching). 0 Examples of the etchant for melting include a CF-based mixed gas. Examples of the CF-based gas include C.F4, CHF3, C2F6, C4F8, and c5f8. In the above-mentioned etching, if the selection ratio of the first wiring layer (the etching speed of the first wiring layer / the etching speed of the interlayer insulating layer) for the interlayer insulating layer is in the range of 0.5 to 2.0, it can be formed more. Good continuous surface. (2) Secondly, the at least one through-hole * is formed by etching a part of the interlayer insulating layer * and etching a part of the first wiring layer. Examples of the etching method for uranium etching of a part of the first wiring layer include induction-type plasma etching, downflow plasma etching, and reactive ion etching. As an etchant for etching a part of the first wiring layer, a mixed gas containing a chlorine-based gas may be mentioned. The continuous surface is the bottom surface of the through hole, the surface of the interlayer insulating layer, and the surface of the first wiring layer. Even if the unevenness has a microscopicity and a low difference, it includes a surface that can sufficiently fill the conductive material to the extent of the through hole. — — — III! 1! Brew II i C, please read the precautions in “Back” before filling out this page) This paper size is applicable to country B standards (CNS) A4 specifications < 210 X 297 mm> -8- Economy Printed by the Village Intellectual Property Bureau Industrial Cooperative Cooperative Society 417: 57 A7 __ ^ _ " V. Description of Invention Mai) [Inventive Embodiment] The following describes the preferred embodiment of the present invention with reference to the drawings. (First Embodiment) '' (Structure of Device) The semiconductor device according to this embodiment will be described below. Fig. 1 is a schematic cross-sectional view of a semiconductor device according to this embodiment. On the surface of the substrate 10 of the semiconductor device 100, there are formed semiconductor elements such as MO S F ET, a wiring layer, and an element separation region (not shown). On the substrate 10, a first interlayer insulating layer 12 is formed. A first wiring layer 20 is formed on the first interlayer insulating layer 12. The first wiring layer 20 is composed of a conductive layer 22 and an antireflection film 24 formed on the conductive layer 22, and is patterned in a predetermined pattern. A semiconductor element or a wiring layer on the surface of the substrate 10 is formed in the first interlayer insulating layer 12, and a contact hole (not shown) connected to the first wiring layer 20 is formed. Contact layers (not shown) of titanium plugs, aluminum alloy layers, etc. are formed in the contact holes. A second interlayer insulating layer 30 is formed on the first wiring layer 20 and the first interlayer insulating layer 12. A through hole 40 is formed at a predetermined position of the second interlayer insulating layer 30. A continuous surface is formed on the bottom surface of the through-hole '40, on the top surface of the first wiring layer 20a, and on the top surface of the second interlayer insulating layer 30a. A contact layer 50 is formed in the through hole 40. On the second interlayer insulating layer 30 and the contact layer 50, a second wiring layer 60 is formed. The second wiring layer 60 is composed of a conductive layer 62 and a reflective paper sheet formed on the conductive layer 62. 0 Group Standard (CNS) A4 Λ grid (210 * 297 male 1) ~~ 1-9-" 417 ^ 57 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperation Du printed 5. Inventive note p) Preventive film 6 4 composition. The second wiring layer 60 is connected to the first wiring layer 20 via a contact layer 50. The semiconductor crossbond device 100 according to this embodiment is characterized in that, for example, the bottom surface of the through-hole 40, the upper surface 20a of the first wiring layer and the upper surface 3a of the second interlayer insulating layer are constituted. The continuous surface, that is, in the vicinity of the side wall of the first wiring layer 20, there are no trenches caused by the excessive etching of the second interlayer insulating layer 30 (refer to the background art). Since the upper surface 20 a of the first wiring layer and the upper surface 30 a of the second interlayer insulating layer are formed as continuous surfaces, the conductive material constituting the contact layer 50 can be well embedded in the through-hole 40. In other words, a conductive material can be embedded in the through-hole 40 without causing voids. Therefore, the semiconductor device 100 of this embodiment has high reliability of the wiring layer. In addition, according to the structure of the semiconductor device 100 according to the present embodiment, the reliability of the wiring layer can be ensured, and the wiring structure can be miniaturized to achieve high integration. (Second Embodiment) ^ (Manufacturing method of the first semiconductor device) A manufacturing method of the semiconductor device 100 according to this embodiment will be described below. Figures 2 to 4 are cross-sectional views showing the manufacturing process of the semiconductor device 100 of this embodiment in a pattern. (1) Formation of the first wiring layer First, a semiconductor device (for example, 1 ^ 1051? £: 1 ') is formed on the surface of the substrate 10 by a general method while referring to FIG. 2. Note for the poor side, please fill in this tile.) This paper size is applicable to China National Standards < CNS) A4 specification (210 * 297 mm) -10- r η pa Β7 V. Description of the invention @) Layer and component separation field ( (Not shown). A first interlayer insulating layer 12 is formed on the substrate 10. The details (forming method, material, and film thickness) of the first interlayer insulating layer 12 are the same as those of the second interlayer insulating layer 30 described later. Read the notes on the back side and complete this page. _ Contact holes (not shown) are formed in the first interlayer insulating layer 12 by anisotropic reactive ion etching (RIE). By a known method, a contact layer (not shown) such as a titanium plug or an aluminum alloy layer is formed in the contact hole. A first wiring layer 20 is formed on the first interlayer insulating layer 12 and the contact layer. The first wiring layer 20 is composed of the conductive layer 22 and the anti-reflection film 24, and is configured as follows, for example. First, a conductive layer 22 is formed on the first interlayer insulating layer 12 and the contact layer. Although the film thickness of the conductive layer 22 varies depending on the design of the device, it is, for example, 100 to 100 O'Onm. »The material of the conductive layer 22 is not particularly limited. Examples include aluminum, copper, and aluminum alloy * copper. Alloys, polycrystalline silicon, titanium. Examples of the method for forming the conductive layer 22 include a CVD method, a sputtering method, a deposition method, a coating method, and the like. Next, a hand-off prevention film 24 is formed on the conductive layer 22. The thickness of the anti-reflection film 24 is not particularly limited. For example, it is printed from 20 to 100 nm by the Intellectual Property Bureau of the Ministry of Economic Affairs. The material of the antireflection film 24 is, for example, titanium nitride or titanium tungsten. The method for forming the antireflection film 24 is not particularly limited. If the antireflection film 24 is formed of titanium nitride, a sputtering method can be applied. When the conductive layer 22 and the antireflection film 24 are to be formed by a sputtering method, the conductive layer 22 and the antireflection film 24 are patterned by a photolithography method and a dry etching method to form a first wiring. Layer 2 0. -11 The private paper standard applies the Chinese Standard (CNS) A4 specification (210 * 297) "A7 B7 V. Description of the invention $) (2) The formation of the second interlayer insulation layer Next, as shown in Figure 3 • A film thickness of the second interlayer insulating layer 30 is formed on the first wiring layer 20 and the first interlayer insulating layer 12, and the thickness of the second interlayer insulating layer 30 is specifically limited. For example, the first wiring layer 20 The upper surface has .500 to 1500 nm as a reference. »As the material of the second interlayer insulating layer 30, for example, silicon oxide can be used. As the material of the second interlayer insulating layer 30, if silicon oxide is used, the silicon oxide may also contain phosphorus and boron. As the method for forming the second interlayer insulation-layer 30, for example, a high-density plasma CVD method, a thermal CVD method, a plasma CVD method, an atmospheric pressure CVD method, a spin coating method, or other coating methods (a method using SOG) can be used. ), Sputtering method, thermal deposition method, etc. If it is desired to form the second interlayer insulating layer 30 by the plasma C VD method, it is better to form the RF plasma CVD apparatus of parallel flat plates.》 If you want to form the second interlayer insulating layer by the RF plasma CVD apparatus of parallel flat plates. At 30, TEOS tetraethoxycilane can be used as the gas. Next, if necessary, the film thickness of the second interlayer insulation layer 30 is 30, for example, using the upper surface of the first wiring layer as a reference until it becomes 500. ~ 1 500 nm, the second interlayer insulating layer 30 is planarized by the CMP method. (3) Formation of through-holes' Next, as shown in FIG. 4, a resist layer R 1 having a predetermined pattern is formed on the second interlayer insulating layer 30 by a photolithography method. The resist R 1 is located above the first wiring layer 20 and has an opening. That is, the resist layer R 1 is on the second interlayer insulating layer 30 where the through-hole 40 is to be formed. 0 Please read the "I & M" on the back side before filling in this page.) -Binding ----- ---- Line-Cooperating with labor and expenses of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed paper sizes are applicable to Chinese national standards (CNS > A4 specifications (210 * 297 mm) -12-
經濟部智慧財產局WX消费合作杜印製 五、發明說明¢0 ) ’具有開口部· 接著，將抗蝕層R 1作爲光罩，蝕刻第2層間絕緣層 30，以形成貫通孔40。第2層間絕緣層30之蝕刻， ‘係作爲第2層間絕緣層30與第1配線層20同時可蝕刻 之方法，例如由乾蝕刻進行》作爲較佳之乾蝕刻之具體例 ，係例如可使用反應離子蝕刻*感應結合型電漿蝕刻， E C R電漿蝕刻。此蝕刻之腐蝕劑係只要可同時蝕刻第2 層間絕緣層3 0與第1配線層2 0者則不特別加以限定。 較佳之腐蝕劑，則可使用包含C F系氣體之混合氣體。作 爲此CF系之氣體，係從CF*，CHF3，C2F*， C<F8，（： 5Fs所選擇之至少1種較佳。又，包含CF系 氣體之混合氣體爲包含從CO.，Ar，〇2，N:所選擇之 至少1種較佳。對於第2層間絕緣層3 0之第1配線層 2 0之選擇比（第1配線層之蝕刻速度/第2層間絕緣層 之蝕刻速度）爲位於0.5〜2.0之範圍內較佳。 由這種蝕刻方法，藉蝕刻第2§間絕緣層3 0，若發 生抗蝕層R 1之圖案配合偏移時，在第2層間絕緣層3 0 之蝕刻時，就可同時蝕刻第1配線層2 0。因此，當發生 抗蝕層R 1之圖案配合偏移時，於貫通孔4 0底面，第2 層間絕緣層上面3 0 a與第1配線層上面2 0 a就會構成 連續面。亦即，於第1配線層2 0側壁附近’不會發生溝 渠》又，因藉控制選擇比，就可將貫通孔4 0底面成爲更 良好之連續面。 11 — — — — — I! 訂·--» -锖先Η讀背面之汪意事項再填寫本頁) 本纸張尺度適用中國困家標準（CNS)A4规袼（2】0 * 297公« ) -13 · A7 B7 417257 五、發明說明〇1 ) (4)接觸層〜第2配線層之形成 ’ 接著，將抗蝕層R 1灰化（ashing)去除之後’如第 1圖所示，在貫通孔4 0形成接觸層5 0。接觸層5 0 ’ •係例如，在貫通孔40內塡充導電材，藉將導電材反触刻 來加以形成。作爲導電材，例如，可列舉鎢，銘’錯合金 ’銅，銅合金。又，也可以在第2層間絕緣層3及第2配 線層6 0，與接觸層5 0間之具有濕層及阻隔層之一方° 在第2層間絕緣層3 0及接觸層5 0上’形成第2配線層 6 0。第2配線層6 0之詳細情形（例如’膜厚，材質’ 形成方法），係與第1配線層20相同。像這樣，就完成 半導體裝置1 0 0 - 於本實施形態，其特徵爲例如如下。亦即’爲了欲形 成貫通孔4 0蝕刻第2層間絕緣層3 0時，欲將第2層間 絕緣層3 0與第1配線層2 0可同時蝕刻利用該蝕刻方法 。藉此，當發生抗蝕圖案之配合偏移時’可同時蝕刻第2 層間絕緣層3 0與第1配線層2 0 :因此’若發生配合偏 移時，於貫通孔4 0之底面，在第2層間絕緣層上面 3〇a與第1配線層上面20a，可構成連續面。亦即’ 於第1配線層2 0之側壁附近，不會發生第2層間絕緣層 3 0之局部性過度蝕刻所引起之溝渠。 並且，因第2層間絕緣層之上面3 0 a與第1配線層 上面20a ，構成連續面，所以，欲形成接觸層50時， 可在貫通孔4 0內良好地埋入構成接觸層5 0之導電材。 因此，依據有關本實施形態之半導體裝匱之製造方法 (請先閱讀背面之注意事項再填寫本頁) 裝！ —訂.------!線 經濟邨智慧財產局貝工消费合作社印製 本紙張尺度適用中圉國家標攀（CNS)A4規格（210x297公* > - 14- 經濟部智慧財產局貝Η消費合作社印製 A7 Λ1 W__Β7_ · - 玉、發明說明〇2 ) ，可提升配線層之可靠性》又，依據由此半導體裝置之製 造方法所獲得之半導體裝置之構成，就可邊確保配線層之 可靠性，將配線構造微細化而可達成高積層化。 (第3實施形態） (第2半導體裝置之製造方法） 有關第3實施形態之半導體裝置之製造方法，係於貫 通孔4 0之形成方法之點來說，與有關第2實施形態之製 造方法不相同，除此之外，因實質上爲相同，而從略詳細 說明。又，對於具有同樣之部分，係標示了同一符號。 (1)貫通孔之形成 與有關第2實施形態之製程（1 )及（2 )同樣，形 成到第2層間絕緣層3 0 * 第5圖及第6圖，係欲形成貫通孔之製程以模式表示 之剖面圖。 * 如第5圖所示，在第2層間絕緣層3 0之上，由光刻 成像法形成與第2實施形態同樣之圖案之抗蝕層R1。將 抗蝕層R 1作爲光罩，蝕刻第2層間絕緣層3 0。以下， 將第2層間絕緣層30之蝕刻，稱爲「第1蝕刻」。第1 蝕刻係進行到第1配線層2 0之上面露出。在此•如第5 圖所示，若抗蝕層R 1發生圖案配合之偏移時，於第1配 線層2 0之側壁附近，會發生溝渠3 2。第1蝕刻方法， 係並不特別加以限定，例如，可舉出乾蝕刻。較佳乾蝕刻 .·、·.一.»·· 一 ^張尺度適用中a a家標準（CNS)A4規格（210 X 297公藿)~ .15- I —II. I— -----< i ---— In --- (請先《讀背面之泫+?^項再填窵本頁> I 』 - - -00 _1 Λ 1 e 9 r ” A7 B7 五、發明說明Ο3 ) {,請先《讀背面之注意事項再填寫本頁》 之具體例，係可舉出反應離子触刻（reactive ion etching ) ，感應結合型電漿蝕刻，E CR電漿蝕刻。作爲腐蝕劑， 只要可以將第2層間絕緣層3 0蝕刻者，並不特別加以限 定，可舉出包含CF系氣體之混合氣體*作爲此CF系之 氣體係由從 CF<，CHF3，C2F6，C4F*，C5F8 所 選擇之至少1種較佳。又，包含C F系氣體之混合氣體， 係包含從CO，Ar，Oi，N:所選擇之至少1種較佳。 接著，如第6圖所示1將抗蝕層R 1灰化去除之後， 將第2層間絕緣層3 0作爲光罩1蝕刻第1配線層2 0 » 經濟部智慧財產局貝工消费合作社印製 第1配線層2 0係只有蝕刻於第1蝕刻所發生之溝渠3 2 之深度。亦即，於貫通孔4 0之底面，第1配線層上面 20a ，與第2層間絕緣層上面30a ，直到構成連續面 ，蝕刻第1配線層2 0。藉此，即使發生起因於抗蝕層 R 1之圖案配合偏移之溝渠3 2時，就可將溝渠3 2消除 。以下，將第1配線層20之蝕刻，稱爲「第2蝕刻」。 在第2蝕刻完成時，形成貫通孔4 0。作爲第2蝕刻之蝕 刻方法，只要可蝕刻第1配線層2 0之方法時並不特別加 以限定。作爲較佳之蝕刻方法，係可舉出感應結合型電漿 蝕刻*下流電漿蝕刻1反應離子蝕刻。作爲腐蝕劑，係只 要可蝕刻第1配線層2 0者並不特別加以限定。作爲較佳 腐蝕劑，可舉出包含氯系氣體之混合氣體。作爲此氯系氣 體，係從C 1 2，BC 1 3所選擇之至少1種較佳》又，包 含氯系氣體之混合氣體’係包含從CO，Ar ’ 〇2，Ν: 所選擇之至少1種者較佳。第2蝕刻’係在不發生第1配 本纸張尺度適用中國0家標準（CNS)A4規格（210x297公藿） -16- 4 4 炷濟部智慧財產局BK工消费合作社印製 A7 B7 五、發明說明（14 ) 線層2 0之側邊蝕刻之條件下進行較佳。 (2 )接觸層〜第2配線層之形成 • 如第1層所示，在貫通扎4 0內，與第2實施形態同 樣，形成接觸層5 0之上，與第2實施形態同樣，形成第 2配線層.6 0。像這樣，完成半導體裝置1 0 0。 於本實施形態，其特徵爲進行第1蝕刻之後，進行第 2蝕刻。亦即，由於發生抗蝕層R 1配合之偏移，結束第 1蝕刻時•即使發生溝渠3 2，藉第2蝕刻，於貫通孔 4 0之底面，第2層間絕緣層上面3 0 a與第1配線層上 面20a ，將構成連續面。因第2層間絕緣層上面3〇a 與第1配線層上面20a ，構成連續面，所以形成接觸層 5 0時，在貫通孔4 0可良好地埋入導電材=亦即不至於 發生空隙，可在貫通孔4 0內埋入導電材。因此，依據有 關本實施形態之半導體裝置之製造方法，就可提升配線層 之可靠性。又，由此半導體裝置之^造方法所獲得之半導 體裝置之構成，邊確保配線層之可靠性，將配線層微細化 ，就可達到高積層化。 按，於本實施形態，於貫通孔4 0之底面，第1配線 層上面2 0 a，與第2層間絕緣層上面3 0 a，構成連續 面之範圍，於第2蝕刻蝕刻第2層間絕緣層3 0。 (實驗例） _ (第1實施例） — I — — — — — — — - · I —I I I —I ^ I I I 111 —I Γ請先閱讀背面之注意事項再赛寫本頁) ^紙張尺度適用中國國家標準（CNS)A4规格（2W * 297公釐） -17- Λ Α7 Β7 五、發明說明卟） 由有關第2實施形態之半導體裝置之製造方法之以下 實驗條件，蝕刻第2層間絕緣層，形成貫通孔時，獲得了 如下見解。亦即，由以下之實驗條件，形成貫通孔時，可 '將第1配線層與第2層間絕緣層30之蝕刻速度約略變成 相等*因此，於貫通孔底面，第1層間絕緣層上面與第1 配線層上面，爲構成連續面（約略水平面）。亦即，於第 1配線層之側壁附近，沒有發生溝渠。 (實驗條件） (蝕刻條件） 蝕刻裝置：反應離子蝕刻（R I )裝置Printed by WX Consumer Cooperation Bureau of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention ¢ 0) 'Has an opening. Next, the second interlayer insulating layer 30 is etched with the resist R1 as a photomask to form a through hole 40. The etching of the second interlayer insulating layer 30 is a method in which the second interlayer insulating layer 30 and the first wiring layer 20 can be etched at the same time, for example, by dry etching. As a specific example of dry etching, for example, a reaction can be used. Ion etching * induction combined plasma etching, ECR plasma etching. The etchant for this etching is not particularly limited as long as it can etch the second interlayer insulating layer 30 and the first wiring layer 20 simultaneously. As a preferred etchant, a mixed gas containing a C F-based gas can be used. As the CF-based gas, at least one selected from CF *, CHF3, C2F *, C < F8, (: 5Fs) is preferred. In addition, the mixed gas containing CF-based gas is composed of CO., Ar, 〇2, N: At least one selected is preferred. Selection ratio for the second interlayer insulating layer 30 to the first wiring layer 20 (etching speed of the first wiring layer / etching speed of the second interlayer insulating layer) It is preferably within the range of 0.5 to 2.0. By this etching method, by etching the second interlayer insulating layer 30, if the pattern of the resist layer R1 shifts, the second interlayer insulating layer 3 0 During the etching, the first wiring layer 20 can be etched at the same time. Therefore, when the pattern matching of the resist layer R 1 is shifted, the bottom surface of the through hole 40 and the upper surface of the second interlayer insulating layer 3 a and the first The upper surface of the wiring layer 20a will form a continuous surface. That is, no ditch will occur near the side wall of the first wiring layer 20, and by controlling the selection ratio, the bottom surface of the through hole 40 can be made better. Continuous side. 11 — — — — — I! Order ·-»-锖 Read the details on the back side and fill in this page) This paper is for Chinese families Standard (CNS) A4 specification (2) 0 * 297 male «) -13 · A7 B7 417257 V. Description of the invention 〇 1) (4) Formation of contact layer to second wiring layer 'Next, the resist layer R 1 After the ashing is removed, as shown in FIG. 1, a contact layer 50 is formed in the through hole 40. The contact layer 50 'is formed by, for example, filling a conductive material in the through-hole 40, and forming the conductive material by inversely touching the conductive material. Examples of the conductive material include tungsten, copper, copper, and copper alloy. It is also possible to have one of a wet layer and a barrier layer between the second interlayer insulating layer 3 and the second wiring layer 60 and the contact layer 50 on the second interlayer insulating layer 3 0 and the contact layer 50. A second wiring layer 60 is formed. The details of the second wiring layer 60 (for example, the method of forming the "film thickness, material") are the same as those of the first wiring layer 20. In this way, the semiconductor device 100 is completed. According to this embodiment, the features are, for example, as follows. That is, when the second interlayer insulating layer 30 is to be etched to form a through hole 40, the second interlayer insulating layer 30 and the first wiring layer 20 can be simultaneously etched using this etching method. Therefore, when the misalignment of the resist pattern occurs, the second interlayer insulating layer 30 and the first wiring layer 20 can be etched at the same time: Therefore, if the misalignment occurs, the bottom surface of the through hole 40 The upper surface 30a of the second interlayer insulating layer and the upper surface 20a of the first wiring layer may constitute a continuous surface. In other words, the trenches caused by the local over-etching of the second interlayer insulating layer 30 will not occur near the side wall of the first wiring layer 20. In addition, since the upper surface 30 a of the second interlayer insulating layer and the upper surface 20 a of the first wiring layer constitute a continuous surface, when the contact layer 50 is to be formed, the contact layer 50 can be embedded well in the through hole 40 to form the contact layer 50. Of conductive material. Therefore, according to the manufacturing method of the semiconductor device in this embodiment (please read the precautions on the back before filling this page). —Order .------! Printed on paper by Shelley Consumer Cooperative of the Intellectual Property Bureau of the Economic Village. The paper size applies to the China National Standard Climbing (CNS) A4 Specification (210x297) * >-14- Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Behr Consumer Cooperative A7 Λ1 W__Β7_ ·-Jade, invention description 0 2), can improve the reliability of the wiring layer ", and according to the structure of the semiconductor device obtained by this semiconductor device manufacturing method, the wiring can be ensured Reliability of layers can be achieved by miniaturizing the wiring structure. (Third embodiment) (Manufacturing method of second semiconductor device) The manufacturing method of the semiconductor device of the third embodiment is related to the method of forming the through-hole 40, and the manufacturing method of the second embodiment It is not the same except that it is substantially the same, so it will be described in detail. In addition, the same symbols are assigned to the parts having the same parts. (1) The formation of through-holes is the same as the processes (1) and (2) of the second embodiment, and is formed to the second interlayer insulating layer 3 0 * Figures 5 and 6 are the processes for forming the through-holes. Sectional representation of the pattern. * As shown in FIG. 5, a resist layer R1 having the same pattern as that of the second embodiment is formed on the second interlayer insulating layer 30 by a photolithography method. Using the resist R1 as a photomask, the second interlayer insulating layer 30 is etched. Hereinafter, the etching of the second interlayer insulating layer 30 is referred to as "first etching". The first etching is performed until the upper surface of the first wiring layer 20 is exposed. Here, as shown in FIG. 5, if the pattern matching of the resist layer R 1 is shifted, a trench 32 may occur near the side wall of the first wiring layer 20. The first etching method is not particularly limited, and examples thereof include dry etching. Better dry etching .., ........... One size is applicable to the Chinese Standard AA (CNS) A4 specification (210 X 297 cm) ~ .15- I —II. I— ----- < i ----- In --- (please read the "++ ^^ item on the back side and then fill in this page">---00 _1 Λ 1 e 9 r ”A7 B7 V. Description of the invention 〇3 ) {, Please read "Notes on the back side before filling out this page" for specific examples. Reactive ion etching, induction plasma etching, and E CR plasma etching are examples. As an etchant, As long as the second interlayer insulating layer 30 can be etched, it is not particularly limited, and a mixed gas containing CF-based gas * can be cited as the CF-based gas system from CF <, CHF3, C2F6, C4F *, C5F8 At least one selected is preferred. In addition, a mixed gas containing a CF-based gas is preferably selected from CO, Ar, Oi, and N: At least one selected is preferred. Next, as shown in FIG. 6, 1 will resist After the etched layer R 1 is ashed and removed, the second interlayer insulating layer 30 is used as the photomask 1 to etch the first wiring layer 2 0. The first wiring layer 2 0 is printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 1 The depth of the trench 3 2 that occurred in the etching. That is, on the bottom surface of the through hole 40, the upper surface of the first wiring layer 20a, and the upper surface of the second interlayer insulating layer 30a, until the continuous surface is formed, the first wiring layer 2 0 is etched. With this, even if the trench 32 caused by the pattern of the resist layer R1 is shifted, the trench 32 can be eliminated. Hereinafter, the etching of the first wiring layer 20 is referred to as "second etching". . When the second etching is completed, a through hole 40 is formed. The etching method for the second etching is not particularly limited as long as it can etch the first wiring layer 20. As a preferred etching method, induction-coupled plasma etching * downstream plasma etching 1 reactive ion etching can be mentioned. The etchant is not particularly limited as long as it can etch the first wiring layer 20. Preferred examples of the etchant include a mixed gas containing a chlorine-based gas. As the chlorine-based gas, at least one selected from C 1 2 and BC 1 3 is preferred. Also, the mixed gas containing the chlorine-based gas 'includes at least one selected from CO, Ar' 〇2, N: One is better. The second etch is not applicable to the paper size of the first paper. The Chinese standard 0 (CNS) A4 size (210x297 cm) is applicable. -16- 4 4 Printed by the Ministry of Economic Affairs Bureau of Intellectual Property BK Industrial and Consumer Cooperative A7 B7 V. DESCRIPTION OF THE INVENTION (14) It is better to perform the etching on the side of the wire layer 20. (2) Formation of the contact layer to the second wiring layer As shown in the first layer, the contact layer 50 is formed in the through hole 40 as in the second embodiment, and is formed in the same manner as in the second embodiment. 2nd wiring layer. 6 0. In this way, the semiconductor device 100 is completed. This embodiment is characterized in that after the first etching is performed, the second etching is performed. In other words, due to the shift of the resist layer R 1, the first etching is ended. Even if the trench 3 2 occurs, by the second etching, the bottom surface of the through-hole 40 and the upper surface of the second interlayer insulating layer 30 a and The upper surface 20a of the first wiring layer will constitute a continuous surface. The upper surface 30a of the second interlayer insulating layer and the upper surface 20a of the first wiring layer constitute a continuous surface. Therefore, when the contact layer 50 is formed, the conductive material can be buried well in the through-hole 40 = that is, no voids will occur. A conductive material may be embedded in the through hole 40. Therefore, according to the method for manufacturing a semiconductor device according to this embodiment, the reliability of the wiring layer can be improved. In addition, the structure of the semiconductor device obtained by the method for manufacturing a semiconductor device can achieve high layering while ensuring the reliability of the wiring layer and miniaturizing the wiring layer. According to this embodiment, on the bottom surface of the through-hole 40, the upper surface of the first wiring layer 20a, and the upper surface of the second interlayer insulation layer 30a constitute a continuous surface range, and the second interlayer insulation is etched in the second etching. Layer 3 0. (Experimental example) _ (First embodiment) — I — — — — — — — — · I —III —I ^ III 111 —I Γ Please read the notes on the back before writing this page) ^ Paper size applies Chinese National Standard (CNS) A4 specification (2W * 297mm) -17- Λ Α7 B7 V. Description of the invention) The second interlayer insulating layer is etched under the following experimental conditions regarding the manufacturing method of the semiconductor device of the second embodiment When forming through-holes, the following insights were obtained. That is, when the through-holes are formed under the following experimental conditions, the etching rate of the first wiring layer and the second interlayer insulating layer 30 can be made approximately equal *. Therefore, on the bottom surface of the through-hole, the upper surface of the first interlayer insulating layer and the first 1 The upper surface of the wiring layer is a continuous surface (approximately horizontal). That is, no trench occurs near the side wall of the first wiring layer. (Experimental conditions) (Etching conditions) Etching device: Reactive ion etching (R I) device
蝕刻氣體：CHF?/Ar/N2=8〇s ccm/200 s c cm/6(^c cm RF功率：1300W 壓力·* 150mTorr (=19 . 95Pa) 基板溫度：5 0 °C * (第2層間絕緣層） 材質：氧化矽 膜厚：〇 . 8 # m ' (第1配線層） 導電層之材質：鋁合金 反射防止膜之材質：氮化鈦Etching gas: CHF? / Ar / N2 = 8〇s ccm / 200 sc cm / 6 (^ c cm RF power: 1300W pressure · * 150mTorr (= 19. 95Pa) Substrate temperature: 50 ° C * (Second layer Insulation layer) Material: Silicon oxide film thickness: 0.8 # m '(1st wiring layer) Material of conductive layer: Aluminum alloy anti-reflection film Material: titanium nitride
— — — — — — — — — — — — — — — — ~τ 11 I I 1, J. - — — III — — «Iilll — Ι— I _'·請先閱讀背面之注意事項再填寫本頁W 經濟部智慧财產局具工消费合作杜印製 本紙張尺度遶用中00家標準（CNS)A4規格（210* 297公釐> -18- 經濟部智慧財產局員工消f合作社印製 五、發明說明Ο6 ) 上述之實施形態，於不脫離本發明要旨之範圍，可進 行種種變更。例如，可變更爲如下。 第2及第3實施形態，將構成接觸層5 0，與第2配 '線層60之導電層62個別地形成，但是，也可以將此同 時形成。此時之接觸層5 0與第2配線層之材質，係例如 可舉出鋁，鋁合金，銅，銅合金，鎢等。又，作爲接觸層 50與導電層62之形成方法，可舉出CVD法，PVD 法，電鍍法等》 - 圖式之簡單說明 第1圖係將有關第1實施形態之半導體裝置以模式表 示之剖面圖。 第2圖係將有關第1實施形態之半導體裝置之製造方 法之製程以模式表示之剖面圖。 第3圖係將有關第1實施形態之半導體裝置之製造方 法之製程以模式表示之剖面圖。 ^ 第4圖係將有關第1實施形態之半導體裝置之製造方 法之製程以模式表示之剖面圖。 第5圖係將有關第2實施形態之半導體裝置之製造方 法之製程以模式表示之剖面圖》 第6圖係有關先行技術之半導體裝置之製造方法之製 程以模式表示之剖面圖。 第7圖係有關先行技術之半導體裝置之製造方法之製 程以模式表示之剖面圖。 ------- »^inllll^ilnl—!^- « Γ請先《讀背面之沒意事項再填寫本頁> 本紙張尺度適用中國困家標準（CNS>A4規格<210 * 297公釐） •19- B7 B7 經濟部智慧財產局員工消t合作社印岽 五、發明說明π ) 第8圖係有關先行技術之半導體裝置之製造方法之製 程 以模式 表 示 之 剖 面 圖。 第9 圖係有 關 先行技 術 之 半 程 以模式表示 之 剖 面 圖。 [ 符號之 說 明 ] 1 0 基 板 > 1 2 第 1 層 間 絕 緣 層， - 2 0 第 1 配線 層 * 2 0 ； a 第 1 配 線 層 之上 面 > 3 0 第 2 層 間 絕 緣 層， 3 0 ί 3 第 2 層 間 絕 緣層 之 上 面 3 2 溝 渠 4 0 貫 通 孔 5 0 接 觸 層 f 6 0 第 2 配 線 層 t R 1 抗餓 層 〇 Γ請先閲讀背面之注意事項再填寫本頁) 20 良纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）— — — — — — — — — — — — — — — — ~ Τ 11 II 1, J.-— — III — — «Iilll — Ⅰ— I _ '· Please read the notes on the back before filling out this page W Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperation Duplicates this paper. Standards (CNS) A4 specifications (210 * 297 mm) & -18- Printed by the Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the Invention 〇6) The above embodiments can be modified in various ways without departing from the scope of the present invention. For example, it can be changed as follows. In the second and third embodiments, the contact layer 50 is formed separately from the conductive layer 62 of the second wiring layer 60, but it may be formed at the same time. Examples of the material of the contact layer 50 and the second wiring layer at this time include aluminum, aluminum alloy, copper, copper alloy, and tungsten. In addition, as a method for forming the contact layer 50 and the conductive layer 62, a CVD method, a PVD method, a plating method, and the like can be cited.-Brief Description of the Drawings The first drawing shows the semiconductor device according to the first embodiment in a pattern. Sectional view. Fig. 2 is a cross-sectional view schematically showing a manufacturing process of the method for manufacturing a semiconductor device according to the first embodiment. Fig. 3 is a cross-sectional view schematically showing a manufacturing process of the method for manufacturing a semiconductor device according to the first embodiment. ^ Fig. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device manufacturing method according to the first embodiment in a pattern. Fig. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device manufacturing method of the second embodiment in a pattern. Fig. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device manufacturing method of the prior art in a pattern. Fig. 7 is a cross-sectional view schematically showing a manufacturing process of a semiconductor device manufacturing method according to the prior art. ------- »^ inllll ^ ilnl —! ^-« Γ Please read the "Unintended Matters on the Back Side before filling in this page"> This paper size is in accordance with Chinese standards (CNS > A4 specifications < 210 * 297 mm) • 19- B7 B7 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, Cooperative Cooperative Seal, V. Invention Description π) Figure 8 is a cross-sectional view showing the manufacturing process of the semiconductor device manufacturing method of the prior art. Figure 9 is a cross-sectional view of the half of the prior art shown in a pattern. [Explanation of symbols] 1 0 substrate > 1 2 first interlayer insulation layer,-2 0 first wiring layer * 2 0; a above the first wiring layer > 3 0 second interlayer insulation layer, 3 0 ί 3 Above the second interlayer insulation layer 3 2 Trench 4 0 Through hole 5 0 Contact layer f 6 0 Second wiring layer t R 1 Anti-starvation layer Γ Please read the precautions on the back before filling this page) 20 Good paper size Applicable to China National Standard (CNS) A4 (210 X 297 mm)