KR100850216B1 - Method of forming fine patterns of semiconductor device using double patterning process - Google Patents

Abstract

A method for forming fine patterns of a semiconductor device using a double patterning process is provided to form plural wire lines by using a layout for forming an embossed wire pattern and by patterning a lower layer using a first pattern to form an opening on the lower layer and to form a wire line in the opening. An etching target layer(114) is formed on a substrate(100) including a first region and a second region. Plural first mask patterns(130a) are formed on the etching target layer. The first mask patterns have first pattern density in the first region and second pattern density in the second region. A first capping layer pattern(140a) is formed on the first region to gap-fill a space between two adjacent first mask patterns of the plural first mask patterns. A second capping layer pattern(142a) is formed in the second region to cover a sidewall of the first pattern so that a recess region having a predetermined width remains in the space. Plural second mask patterns(150a) are located on the same level as the first mask pattern in the recess region on the second capping layer. One of a first pattern being comprised of the first capping layer pattern and a second capping layer pattern, and a second pattern being comprised of the first mask pattern and a second mask pattern is removed. The etching target layer is etched by using the selected one pattern as an etching mask.

Description

Method of forming fine patterns of semiconductor device using double patterning process

1A to 1K are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with a first embodiment of the present invention.

2A and 2B are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with a second embodiment of the present invention, according to a process sequence.

3A to 3F are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with a third embodiment of the present invention, according to a process sequence.

4 is a cross-sectional view for describing a method of forming a fine pattern of a semiconductor device in accordance with a fourth embodiment, which is a modification of the third embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

Reference Signs List 100: substrate, 112: first etch stop layer, 114: etched film, 114a: etched pattern, 114h: opening, 116: second etch stop layer, 122: hard mask layer, 122a: hard mask pattern, 124: transient Etch buffer layer, 124a: transient etching buffer layer pattern, 130: first mask layer, 130a: first mask pattern, 140: first capping layer, 140a: first capping layer pattern, 142: second capping layer, 142a: second Capping layer pattern, 142a-1: second capping layer vertical pattern, 142a-2: second capping layer bottom portion, 144: recessed region, 150: second mask layer, 150a: second mask pattern, 152: antireflection film 154: photoresist pattern, 210: barrier film, 212: metal film, 220: wiring line, 342: third capping layer, 342a: third capping layer pattern, 342a-1: third capping layer vertical pattern, 342a- DESCRIPTION OF SYMBOLS 2: 3rd capping layer bottom part, 344: recess, 350: 2nd mask layer, 350a: 2nd mask pattern, 360: mask pattern, 362: anti-reflective film pattern, 364: photoresist pattern, 370: 4th cap Ping layer, 370a: fourth capping layer pattern.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly to a method of forming a fine pattern of a semiconductor device using a fine pitch hard mask pattern formed by a double patterning process.

Pattern refinement is essential in manufacturing highly integrated semiconductor devices. In order to integrate a large number of devices in a small area, the size of the individual devices should be made as small as possible. For this purpose, the pitch, which is the sum of the widths of the patterns to be formed and the spacing between the patterns, should be made small. do. Recently, as the design rule of a semiconductor device is drastically reduced, there is a limit in forming a pattern having a fine pitch due to a resolution limitation in a photolithography process for forming a pattern required for semiconductor device implementation. In particular, in the photolithography process for forming a line and space pattern (hereinafter referred to as "L / S pattern") on a substrate, there is a limit in forming a desired pattern having a fine pitch due to the resolution limitation. have.

In order to overcome the resolution limitation in the photolithography process as described above, methods for forming a hard mask pattern having a fine pitch using a double patterning process have been proposed.

However, when a predetermined pattern is to be simultaneously formed in a region having a relatively high pattern density, such as in a cell array region on a semiconductor substrate, and in a region having a relatively low pattern density, such as a peripheral circuit region or a core region, only in a region having a high pattern density In order to selectively apply the double patterning process, it is necessary to develop a double patterning process that can form a pattern to be formed at a different pitch for each region. In applying the double patterning process, even when the pattern density or pattern width to be formed is simultaneously formed in different areas with different pattern densities, the difference in pattern density or pattern width in each area There is a need to develop a new double patterning process that can overcome the problems caused by the difference in etching rate and the depth of etching in each region.

In addition, it is necessary to form a plurality of wiring lines that are repeatedly formed at a fine pitch in order to manufacture ultra-high density semiconductor devices, which are recently required, and the space width between adjacent wiring lines in the plurality of wiring lines is gradually decreasing. In addition, Cu has a low specific resistance as a material of the wiring line. In general, when a Cu film pattern is to be formed, a damascene process of filling Cu in the intaglio pattern is formed by first forming an insulation layer pattern having a negative wiring line pattern formed on the insulator film. However, in the case of forming a plurality of Cu film patterns repeatedly formed at a fine pitch required for an ultra-high density semiconductor device, the width of the space between wiring lines is very small, about several to several tens nm, so that the wiring in the case of using the double patterning process It is very difficult to implement an insulating film pattern having a width corresponding to the space between lines. In addition, for example, wiring patterns having a very small width, which are repeatedly formed at a fine pitch as in the cell array region, and circuit patterns having various sizes as in the peripheral circuit region may be simultaneously implemented as negative patterns on the insulating layer. Even more difficult. Therefore, there is a limit in forming a plurality of wiring lines required for an ultra-highly integrated semiconductor device when forming a Cu film pattern using an intaglio pattern using a conventional technique.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in the prior art, by using a double patterning process for realizing a pattern of fine pitch that can overcome the resolution limitation in the photolithography process. And simultaneously forming patterns of various pitches, to form a desired pattern while preventing problems that may be caused by pattern density or pattern width difference in each region where the pattern density or pattern width is different, and forming an embossed pattern. Fine pattern formation of a semiconductor device capable of forming a plurality of wiring lines repeatedly formed at a fine pitch by a damascene process by using an embossed wiring pattern formation layout used when patterning a patternable film by a method as it is To provide a way.

In order to achieve the above object, in the method of forming a fine pattern of a semiconductor device according to the present invention, an etching target film is formed on a substrate including a first region and a second region. A plurality of first mask patterns having a first pattern density in the first region and a second pattern density in the second region are formed on the etched film. In the first region, a first capping layer pattern is formed to fill a space between two adjacent first mask patterns among the plurality of first mask patterns. In the second region, two adjacent capping layer patterns among the plurality of first mask patterns are formed. A second capping layer pattern covering sidewalls of the first mask pattern such that a recessed region of a predetermined width remains in a space between the first mask patterns, and the first capping layer pattern in the recess region on the second capping layer pattern A plurality of second mask patterns positioned on the same level as the mask pattern are formed. The other one pattern is removed such that a selected one of the first pattern including the first capping layer pattern and the second capping layer pattern and the second pattern including the first mask pattern and the second mask pattern remain. The etching target layer is etched using the selected one pattern as an etching mask.

In the method of forming a fine pattern of a semiconductor device according to an embodiment of the present invention, to form the first capping layer pattern, the second capping layer pattern, and the second mask pattern, first, the plurality of first only in the first region A first capping layer covering a mask pattern and a space therebetween is formed. A second cap covering upper surfaces and sidewalls of the plurality of first mask patterns such that recesses of a predetermined width remain in a space between two adjacent first mask patterns among the plurality of first mask patterns in the second region; A ping layer is formed. A second mask layer is formed on the second capping layer in the second region so that the recess region is completely filled. A portion of each of the second mask layer, the second capping layer, and the first capping layer is removed until the first mask pattern is exposed, so that the first capping layer pattern, the second mask pattern, and the A first capping layer pattern is formed. The second capping layer may be formed in the first region and the second region, respectively, and the second capping layer may be formed on the first capping layer in the first region.

In the method of forming a fine pattern of a semiconductor device according to another embodiment of the present invention, in order to form the first capping layer pattern, the second capping layer pattern, and the second mask pattern, first of the plurality of first in the second region A third capping layer covering upper and sidewalls of the plurality of first mask patterns is formed in a space between two adjacent first mask patterns among the mask patterns so as to leave a recessed region having a predetermined width. A second mask layer is formed on the third capping layer so as to fill a space between two adjacent first mask patterns among the plurality of first mask patterns in the first region and the second region. The second mask layer is removed from the first region so that the second mask layer remains only in the second region. A fourth capping layer is formed on the third capping layer to completely fill the recess region in the first region. The first capping layer including the remaining portion of the fourth capping layer by removing portions of each of the fourth capping layer, the second mask layer, and the third capping layer until the first mask pattern is exposed. And a second capping layer pattern including a pattern, the second mask pattern, and the remaining portion of the third capping layer.

In the method of forming a fine pattern of a semiconductor device according to another embodiment of the present invention, the third capping layer may be formed only in the second region. Alternatively, the third capping layer may be formed in the first region and the second region, respectively. In this case, the fourth capping layer is formed on the third capping layer in the first region, and the first capping layer pattern includes a remaining portion of the fourth capping layer and a remaining portion of the third capping layer. .

In the method of forming a fine pattern of a semiconductor device according to the present invention, the method may further include forming a transient etching buffer layer on the etched film in the first region and the second region before forming the first mask pattern. In this case, the first mask pattern is formed on the transient etching buffer layer. The forming of the first mask pattern may include forming a first mask layer on the transient etching buffer layer in the first region and the second region, and patterning the first mask layer and the transient etching buffer layer to form the first mask pattern. Forming a plurality of first mask patterns and a plurality of transient etching buffer layer patterns each having a first pattern density and a second pattern density in the first region and the second region. The transient etching buffer layer may be formed of a material having the same etching characteristics as the second capping layer pattern.

In the method of forming a fine pattern of a semiconductor device according to an embodiment of the present invention, after forming the etched film and before forming the first mask pattern, forming a hard mask layer on the etched film and before etching the etched film. The method may include forming a hard mask pattern by etching the hard mask layer using the selected one pattern as an etching mask. In this case, the selected one pattern and the hard mask pattern are used as an etching mask to etch the etched film.

When the etched film is an insulating film, etching the etched film using the first pattern as an etching mask to etch the etched film to form an etched pattern having a plurality of openings, and forming a metal film in the opening. It may comprise the step of forming. When the etching target layer is a conductive layer, the second pattern may be used as an etching mask to etch the etching target layer.

According to the present invention, in simultaneously forming patterns of various sizes and various pitches on the same substrate using a double patterning process, the pattern density or pattern width may be caused by the difference in the pattern density or pattern width in each different region. It is possible to easily form the desired pattern while preventing possible problems. In particular, even in the case of forming a plurality of wiring lines repeatedly formed at a fine pitch in the damascene process, the pattern formation is performed by the embossed pattern formation method without having to design a separate layout for the intaglio pattern formation required in the damascene process. An embossed wiring pattern forming layout used when patterning the film as possible can be used as it is.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1K are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 1A, a first etch stop layer 112, an etched film 114, and a second etch stop layer 116 are sequentially formed on the substrate 100.

The substrate 100 may be made of a conventional semiconductor substrate such as, for example, a silicon substrate. Unit substrates (not shown) necessary for forming a semiconductor device such as a transistor may be formed on the substrate 100, and an interlayer insulating film (not shown) covering the unit elements may be formed on the substrate 100. It may be formed on the upper surface. In addition, conductive regions (not shown) that may be electrically connected to the unit devices through the interlayer insulating layer may be exposed on the upper surface of the substrate 100.

The substrate 100 includes a low density pattern region A and a high density pattern region B. FIG. The low density pattern region A is a region having a relatively low pattern density per unit area, and may be, for example, a peripheral circuit region or a core region. Alternatively, the low density pattern region A may be a region having a relatively low density of a pattern to be formed in the cell array region. The high density pattern region B is a region having a higher pattern density per unit area than the low density pattern region A, and may be part of a cell array region, for example.

The first etch stop layer 112 and the second etch stop layer 116 may be made of the same material or may be made of different materials. The first etch stop layer 112 and the second etch stop layer 116 are made of a material having an etching selectivity different from that of the etch layer 114.

The first etch stop layer 112 is formed to serve as an etch stopper when the etched film 114 is etched. The first etch stop layer 112 may be formed of, for example, a silicon nitride film, a silicon oxynitride film, or a silicon carbide film, and may be formed to a thickness of about 400 to about 500 μm.

The etched film 114 may be a conductive film or an insulating film for forming a plurality of conductive patterns or conductive pads repeatedly arranged at a fine pitch to form a semiconductor device. When the etched film 114 is a conductive film, the etched film 114 may be formed of a metal, a metal nitride, or a semiconductor. However, it is not limited to these. When the etched film 114 is an insulating film, it may be formed of an insulating material having a relatively low dielectric constant such as, for example, tetraethyl orthosilicate (TEOS), fluorine silicate glass (FSG), SiOC, SiLK, and the like.

The second etch stop layer 116 is formed to serve as an etch stopper during an etching process for forming a subsequent hard mask pattern. The second etch stop layer 116 may be formed of, for example, a silicon nitride film, a silicon oxynitride film, a silicon carbide film, or a polysilicon film, and may be formed to a thickness of about 400 to about 500 μm.

In some cases, the first etch stop layer 112 and the second etch stop layer 116 may be omitted.

The hard mask layer 122 and the transient etching buffer layer 124 are sequentially formed on the second etch stop layer 116.

The hard mask layer 122 may be formed of various materials according to the material of the etched film 114 and the purpose of the pattern to be formed. The hard mask layer 122 may be formed of an oxide, a nitride, a SiON, an amorphous carbon layer (ACL), or a combination thereof. The hard mask layer 122 is made of a material capable of providing an etching selectivity according to the material of the etched film 114. For example, the hard mask layer 122 may include at least one selected from the group consisting of a thermal oxide film, a chemical vapor deposition (CVD) film, an undoped silicate glass film, and a high density plasma oxide film. It may be made of an oxide film. Alternatively, the hard mask layer 122 may be formed of at least one film selected from the group consisting of SiON, SiN, SiBN, and BN. Alternatively, the hard mask layer 122 may be formed of a multilayer consisting of at least one oxide film selected from the above-described oxide films and at least one nitride film selected from the above-described nitride films.

The transient etching buffer layer 124 is formed to prevent damage to the surrounding films during the transient etching for removing residues in a subsequent process. The transient etching buffer layer 124 is preferably made of a material having the same or similar etching characteristics as the first capping layer 140 (FIG. 1C) and the second capping layer 142 (FIG. 1E) formed in a subsequent process. . The reason is described later (see FIG. 1I). The transient etching buffer layer 124 may be formed of, for example, a silicon nitride film or a silicon oxide film.

The first mask layer 130 is formed on the transient etching buffer layer 124. The first mask layer 130 may be formed of a polysilicon film or a nitride film such as SiON, SiN, SiBN, BN, or the like. Alternatively, the first mask layer 130 may be formed of an oxide film. When the hard mask layer 124 is formed of a nitride film or an ACL, the first mask layer 130 may be formed of an oxide film or a polysilicon film. Alternatively, when the hard mask layer 124 is formed of an oxide film, the first mask layer 130 may be formed of a polysilicon film.

Referring to FIG. 1B, the mask layer 130 and the transient etching buffer layer 124 are patterned by a conventional photolithography process to form a plurality of first mask patterns 130a and the transient etching buffer layer pattern 124a.

In the low density pattern region A on the substrate 100, the plurality of first mask patterns 130a are repeatedly formed at the same pitch P _A as the pitch of the pattern to be finally formed from the etched film 114. It consists of a pattern. In the high-density pattern region B on the substrate 100, the first pitch 2P is twice as large as the pitch P _B of the pattern to be finally formed in the etching target film 114. _B ).

For example, in the high-density pattern region B, the first width W ₁ of the first mask pattern 130a may be designed to have a value equal to 1/4 of the first pitch 2P _B. . In the low density pattern region A and the high density pattern region B, the first mask pattern 130a may be formed of, for example, a plurality of line patterns repeatedly formed in a predetermined direction or a rectangular pattern in plan view. have. However, the present invention is not limited thereto and may have various shapes within the scope of the spirit of the present invention.

Referring to FIG. 1C, a first capping layer 140 is formed on a resultant product on which the first mask pattern 130a and the transient etching buffer layer pattern 124a are formed. The first capping layer 140 is formed to a thickness sufficient to completely fill the space between the plurality of first mask patterns 130a.

The first capping layer 140 may be formed of, for example, an oxide film, a nitride film, an ACL, or silicon. Preferably, when the hard mask layer 122 is etched using the first capping layer 140 as an etching mask, the first capping layer 140 is different from the hard mask layer 122. It may be made of a material having an etching characteristic. For example, when the hard mask layer 122 is formed of a nitride film, the first capping layer 140 may be formed of an oxide film. Alternatively, when the hard mask layer 122 is formed of an oxide film, the first capping layer 140 may be formed of a nitride film.

However, when the hard mask layer 122 is etched using the first mask pattern 130a as an etch mask, the first capping layer 140 is etched the same as or similar to that of the hard mask layer 122. It may be made of a material having properties.

Referring to FIG. 1D, a mask pattern in which an antireflection film 152 and a photoresist pattern 154 are sequentially stacked is formed on the first capping layer 140 in the low density pattern region A on the substrate 100. The first capping layer 140 is exposed to the high-density pattern region B through the anti-reflection film 152 and the photoresist pattern 154.

The first capping layer 140 is etched using the photoresist pattern 154 as an etching mask to completely remove the first capping layer 140 in the high density pattern region B. Referring to FIG.

In removing the first capping layer 140 from the high density pattern region B, the first capping layer may be formed on the sidewall of the first mask pattern 130a or the corner portion of the upper surface of the substrate 100 in the high density pattern region B. In order to prevent the residue of the capping layer 140 is left over-etched. For example, in order to remove the first capping layer 140 in the high density pattern region B, a reactive ion etching (RIE) process may be used. In this case, since the transient etching buffer layer 124 is formed on the bottom surface of the first capping layer 140, the transient etching for the complete removal of the first capping layer 140 is performed while a sufficient process margin is secured. I can do it. As a result, there is no fear that the residue of the first capping layer 140 may remain on the sidewall of the first mask pattern 130a or the corner portion of the upper surface of the substrate 100. Therefore, it is not necessary to add a separate wet etching process to remove the residue, thereby preventing damage to the underlying structure or surrounding films due to the wet etching.

Although not illustrated, the first capping layer 140 may have a space between the plurality of first mask patterns 130a in a partial region selected as necessary not only in the low density pattern region A but also in the high density pattern region B. It may be formed to completely fill the. As described above, in the portion where the first capping layer 140 is filled in the space between the plurality of first mask patterns 130a, another pattern cannot be formed due to the first capping layer 140 so that double patterning is performed. It won't work.

Referring to FIG. 1E, after removing the anti-reflection film 152 and the photoresist pattern 154, the both sidewalls of each of the plurality of first mask patterns 130a are covered with a uniform thickness in the high-density pattern region B. Referring to FIG. The second capping layer 142 is formed.

To this end, the second capping layer 142 may be formed on the entire surface of the low density pattern region A and the high density pattern region B with a uniform thickness. As a result, the second capping layer 142 is formed on the first capping layer 140 in the low density pattern region A, and among the plurality of first mask patterns 130a in the high density pattern region B. Sidewalls of the first mask pattern 130a are covered by a second capping layer 142 having a uniform thickness between two adjacent first mask patterns 130a. A recess region 144 having a predetermined width is formed on the second capping layer 142 between two adjacent first mask patterns 130a.

The width W ₂ of the recess region 144 formed on the upper surface of the second capping layer 142 is the first width W ₁ of the first mask pattern 130a formed in the high density pattern region B. FIG. The thickness of the second capping layer 142 may be determined to be equal to).

The second capping layer 142 may be formed of a material having an etching characteristic that is the same as or similar to that of the first capping layer 140. For example, the second capping layer 142 may be made of the same material as the material of the first capping layer 140. Alternatively, the second capping layer 142 may be formed of a similar material to the first capping layer 140 but having different etching characteristics. In addition, the second capping layer 142 may be formed of a material having an etching characteristic that is the same as or similar to that of the transient etching buffer layer pattern 124a. More details on this will be described in more detail with reference to FIG. 1I.

For example, the second capping layer 142 may be formed of an oxide film or a nitride film formed by an atomic layer deposition (ALD) method.

Referring to FIG. 1F, a second mask layer 150 is formed on the second capping layer 142. The second mask layer 150 is formed to a thickness sufficient to completely fill the recess 144.

By forming the second mask layer 150, the recess region 144 may be filled with the second mask layer 150. When the thickness of the second capping layer 142 has a value equal to 1/4 of the first pitch 2P _B , the width of the portion of the second mask layer 150 filled in the recess region 144 is Similar to the width of the recess region 144, a value equal to 1/4 of the first pitch 2P _B , that is, equal to a width W ₁ of the first mask pattern 130a.

The second mask layer 150 may be formed of a material having an etching characteristic similar to that of the first mask layer 130. The second mask layer 150 may be made of the same material as the first mask layer 130, and may have similar etching characteristics but different materials. For example, the first mask layer 130 and the second mask layer 150 may be formed of polysilicon films, respectively. Alternatively, the first mask layer 130 may be formed of a nitride film, and the second mask layer 150 may be formed of a polysilicon film. Of course, the reverse is also possible.

Referring to FIG. 1G, the resultant formed with the second mask layer 150 is planarized by a chemical mechanical polishing (CMP) process until the first mask pattern 130a is exposed, thereby flattening the resultant material in the high density pattern region B. A plurality of second mask patterns 150a are formed between the first mask patterns 130a of the second mask patterns 130a. The plurality of second mask patterns 150a are repeatedly formed at the same pitch as the first pitch 2P _B.

After the plurality of second mask patterns 150a are formed, the first capping layer pattern 140a that fills the space between the plurality of first mask patterns 130a remains in the low density pattern region A. FIG. In the high-density pattern region B, portions of the second capping layer 142 that are on the first mask pattern 130a are removed and only portions that existed in the space between the first mask patterns 130a remain to be separated from each other. A plurality of second capping layer patterns 142a are formed. The plurality of second mask patterns 150a are respectively disposed in the recess regions 144 on the second capping layer pattern 142a.

In the high-density pattern region B, the second capping layer pattern 142a is formed by contacting two sidewalls between the first mask pattern 130a and the second mask pattern 150a, respectively, at two sidewalls. A capping layer vertical pattern 142a-1 and a second capping layer bottom portion 142a-2 covering the hard mask layer 122 therebetween.

When the thickness of the second capping layer 142 has a value of 1/4 of the first pitch 2P _B , the width W ₃ of the second capping layer vertical pattern 142a-1 is equal to the first width. The width W ₁ of the mask pattern 130a may be the same.

Referring to FIG. 1H, the first mask pattern 130a and the second mask pattern 150a are removed.

Conventional dry or wet etching process using the first capping layer pattern 140a and the second capping layer pattern 142a as an etching mask to remove the first mask pattern 130a and the second mask pattern 150a. Can be used. After the first mask pattern 130a and the second mask pattern 150a are removed, the overetch buffer layer pattern 124a is exposed in the low density pattern region A and the high density pattern region B.

Referring to FIG. 1I, the transient etching buffer layer pattern 124a is exposed by using an anisotropic dry etching process.

The transient etching buffer layer pattern 124a is formed of a material having the same or similar etching characteristics as the material of the second capping layer pattern 142a, thereby removing the transient etching buffer layer pattern 124a and bottom surface of the second capping layer. The portion 142a-2 may also be removed to expose the top surface of the hard mask layer 122. As a result, as shown in FIG. 1I, in the high-density pattern region B, the plurality of second capping layer vertical patterns 142a repeatedly arranged at the pitch P _{B that} is 1/2 of the first pitch 2P _B. -1) will remain. In the low density pattern region A, only the first capping layer pattern 140a remains. The plurality of second capping layer vertical patterns 142a-1 and the first capping layer pattern 140a are also removed while the transient etching buffer layer pattern 124a and the second capping layer bottom part 142a-2 are removed. It is consumed by a predetermined thickness from the upper surface.

Referring to FIG. 1J, anisotropic dry etching is performed on the hard mask layer 122 exposed between the plurality of second capping layer vertical patterns 142a-1 and the first capping layer pattern 140a as an etch mask. The hard mask pattern 122a is formed. In this case, the second etch stop layer 116 is used as an etch stopper.

During the etching process for forming the hard mask pattern 122a, the plurality of second capping layer vertical patterns 142a-1 and the first capping layer pattern 140a are also partially consumed, as shown in FIG. 1J. The thickness can be lowered.

Referring to FIG. 1K, the second etch stop layer may be formed by using the plurality of second capping layer vertical patterns 142a-1, the first capping layer pattern 140a, and the hard mask pattern 122a as an etch mask. 116 and the etch film 114 are anisotropic dry etched to form an etch pattern 114a having a plurality of openings 114h formed therein. In this case, the first etch stop layer 112 is used as an etch stopper.

Thereafter, the substrate 100 is exposed by removing the first etch stop layer 112 exposed through the opening 114h of the etch pattern 114a. The second etch stop layer 116, the hard mask pattern 122a, the plurality of second capping layer vertical patterns 142a-1, and the first capping layer pattern 140a that remain on the etch pattern 114a. Remove it.

In the high-density pattern region B, the etched pattern 114a includes a plurality of line patterns repeatedly arranged at a pitch P _{B that} is 1/2 of the first pitch 2P _B.

When the etch pattern 114a is formed of a conductive layer or a semiconductor, the etch pattern 114a may form a wiring line required for a semiconductor device.

In the method of forming a fine pattern of a semiconductor device according to the first exemplary embodiment of the present invention described with reference to FIGS. 1A to 1K, the first mask pattern 130a and the second mask pattern 150a are removed from the resultant of FIG. 1G. As illustrated in FIG. 1I, a method of patterning an underlayer using the first capping layer pattern 140a and the second capping layer vertical pattern 142a-1 as an etching mask is illustrated. However, the present invention is not limited to this. Although not shown, the first mask pattern 130a and the second mask pattern 150a are left in the result of FIG. 1G, and the first capping layer pattern 140a and the second capping layer vertical pattern (exposed between them) are exposed. The method of patterning an underlayer using the first mask pattern 130a and the second mask pattern 150a as an etch mask by removing 142a-1 is also included in the scope of the present invention. In this case, a fine pattern having a shape of reverse tone with respect to the resultant illustrated in FIG. 1K is obtained.

In the method of forming a fine pattern of a semiconductor device according to the first embodiment of the present invention described with reference to FIGS. 1A to 1K, in forming patterns of various sizes and various pitches simultaneously on the same substrate, the pattern density or Even when a pattern having a different pitch is simultaneously formed in each region having a different width of the pattern, the first mask pattern 130a and the second mask are formed by a double patterning process after forming the transient etching buffer layer 124 in advance. The mask pattern 150a is formed. Therefore, when the first mask pattern 130a and the second mask pattern 150a are formed by the double patterning process in each region having a different pattern density, the first capping layer 140 or the second capping layer 142 may be formed. Transient etching may be performed sufficiently to prevent residue from remaining on the substrate 100. Therefore, while effectively preventing unnecessary film quality from remaining on the substrate 100 during the double patterning process, the pattern density and the width of the pattern may be caused by the difference in the pattern density or the pattern width in different regions. The problems due to the difference in etching rate and the difference in etching depth can be overcome.

2A and 2B are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with a second embodiment of the present invention, according to a process sequence.

Referring to FIG. 2A, the etch pattern 114a is formed by a series of processes as described with reference to FIGS. 1A through 1K. However, in this example, the etched film pattern 114a is made of an insulating film.

A barrier layer 210 is formed on an inner wall of the opening 114h formed in the etch pattern 114a and a surface of the etch pattern 114a. Thereafter, a metal film 212 is formed on the barrier film 210 to completely fill the opening 114h.

The barrier film 210 is formed to prevent the metal atoms of the metal film 212 filling the opening 114h from diffusing to other films around the barrier film 210. The barrier layer 210 may be formed to have a thickness of several to several hundred micrometers depending on the width and depth of the opening 114h. For example, the barrier layer 210 may be formed to have a thickness of about 5 to 150 kPa. The barrier layer 210 may be formed of Ta, TaN, TiN, TaSiN, TiSiN, or a combination thereof, and may be formed using a chemical vapor deposition (CVD) process or a sputtering process. Forming the barrier film 210 is not an essential process in the present invention, and in some cases, the process of forming the barrier film 210 may be omitted.

The metal film 212 may be made of any one metal selected from the group consisting of Cu, W, and Al, for example. Preferably, the metal film 212 is made of Cu having a relatively small specific resistance. In order to form the metal film 212, a physical vapor deposition (PVD) process or an electroplating process may be used.

In order to form the metal film 212, the first process using the PVD process and the second process using the electroplating process may be performed. For example, when the metal film 212 is formed of Cu, a first Cu film is first formed on the barrier film 210 by a PVD process to form the metal film 212, and then the first Cu is formed. The second Cu film can be formed by performing a Cu electroplating process using the film as a seed layer. When using such a process, the first Cu film serves to provide an initial nucleation site in a subsequent electroplating process, so that the uniformity of the second Cu film formed by the electroplating process on the first Cu film is achieved. Can be improved. For example, the first Cu film may be formed to a thickness of about 100 to about 500 kPa. The second Cu film is formed to a thickness sufficient to completely fill the opening 114h. For example, the second Cu film may be formed to a thickness of about 1000 to 10000 kPa.

Referring to FIG. 2B, a portion of the metal layer 212 and a portion of the barrier layer 210 may be removed until an upper surface of the etched pattern 114a is exposed to remove the portion between the etched pattern 114a. A metal wiring line 220 is formed in the opening 114h. The metal wiring line 220 includes a barrier film 210 and a metal film 212.

The metal wiring line 220 has a structure arranged at a pitch P _B which is 1/2 of the first pitch 2P _B.

A CMP process may be used to remove a portion of the metal layer 212 and a portion of the barrier layer 210. Alternatively, a wet etching process may be used to remove a portion of the metal layer 212 and a portion of the barrier layer 210. When the metal film 212 is formed of a Cu film, for example, an etching solution including a mixture of HF, H ₂ O _2, and H ₂ O may be used to remove a part of the metal film 212 by a wet etching process. have. At this time, an etchant in which HF, H ₂ O ₂ and H ₂ O are mixed in a volume ratio of 1 to 5, 1 to 5, and 50 to 300 can be used. Alternatively, in order to remove a part of the metal film 212 by a wet etching process, an etching solution including a mixture of H ₂ SO ₄ and H ₂ O ₂ may be used. In this case, an etchant in which H ₂ SO ₄ and H ₂ O ₂ are mixed in a volume ratio of 2: 1 to 10: 1 may be used. In addition, when the barrier layer 210 is formed of Ta, TaN, or a combination thereof, in order to remove a portion of the barrier layer 210 by a wet etching process, for example, NH ₃ , H ₂ O _2, and H _2. An etchant in which O is mixed in a volume ratio of 1 to 5, 1 to 5, and 5 to 30 can be used, respectively. A wet etching process for removing a portion of the metal layer 212 and a portion of the barrier layer 210 may be performed at room temperature, respectively. Alternatively, a wet etching process and a dry etching process may be used to remove a portion of the metal layer 212 and a portion of the barrier layer 210, respectively. That is, a part of the metal film 212 may be removed using a wet etching process in the same manner as described above, and as a result, a dry etching process may be used to remove a part of the barrier film 210 that is exposed. When the barrier layer 210 is formed of Ta, TaN, or a combination thereof, for example, Cl ₂ and BCl ₃ are used as an etching gas to remove a part of the barrier layer 210 by a dry etching process. The dry etching process of the plasma method can be performed.

In the case of forming the wiring line 220 according to the second embodiment described with reference to FIGS. 2A and 2B, to finally form the wiring line 220 repeatedly formed at a fine pitch using a damascene process. An insulating film pattern having an intaglio pattern having the same layout as that of the wiring line 220 is first formed by using a double patterning process. Therefore, even when a wiring pattern is formed using a Cu film having a low resistivity, a predetermined conductive layer is required in the existing wiring pattern forming process, without having to design a separate layout for the intaglio pattern formation required in the damascene process. The metal wiring pattern of a desired layout can be obtained even if a damascene process is performed using the layout used for directly patterning the pattern into an embossed pattern. Therefore, when the fine pattern wiring pattern is to be formed by the damascene process, various patterns having different sizes and pitches, such as in the cell array region and the peripheral circuit region, may be more easily used by using the fine pattern forming method according to the present invention. Can be implemented.

3A to 3F are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with a third embodiment of the present invention, according to a process sequence.

The third embodiment of the present invention described with reference to FIGS. 3A to 3F is substantially the same as the first embodiment. However, in the first embodiment, the first capping layer pattern 140a is first formed in the low density pattern region A without double patterning, and then the second mask pattern 150a is formed in the high density pattern region B. Although the second mask layer 150 is formed for this purpose, in the present example, the second mask layer 350 for forming the second mask pattern 350a is first formed in the high density pattern region B (see FIG. 3B). ), The fourth capping layer 370 is formed in the low density region A where double patterning is not performed. This will be described in more detail with reference to FIGS. 3A to 3F (see FIG. 3E). 3A to 3F, the same reference numerals as those in the first embodiment denote the same members.

Referring to FIG. 3A, a process of forming the plurality of first mask patterns 130a and the transient etching buffer layer pattern 124a on the substrate 100 may be performed by the method described with reference to FIGS. 1A and 1B.

Thereafter, a third capping layer 342 is formed on sidewalls and top surfaces of the plurality of first mask patterns 130a and the hard mask layer 122 exposed between the first mask patterns 130a. Although not illustrated, a portion of the third capping layer 342 in the low density pattern region A may be removed.

The third capping layer 342 may be formed to cover sidewalls of the plurality of first mask patterns 130a and the transient etching buffer layer pattern 124a and upper surfaces of the hard mask layer 122, respectively, with a uniform thickness. Can be. In addition, the width W ₂ of the recess 344 formed on the upper surface of the third capping layer 342 in the high density pattern region B is the same as the width W ₁ of the first mask pattern 130a. The thickness of the third capping layer 342 may be determined to have a dimension.

When the distance d ₁ between two adjacent first mask patterns 130a among the plurality of first mask patterns 130a is smaller than the distance d ₂ in the high density pattern region B, the first mask pattern 130a is formed. The recess 344 may not be formed on the top surface of the third capping layer 342.

Details of the third capping layer 342 are the same as those of the second capping layer 142 with reference to FIG. 1E.

Referring to FIG. 3B, a second mask layer 350 is formed on the third capping layer 342 in the low density pattern region A and the high density pattern region B. Referring to FIG. In this case, the second mask layer 350 is formed to a sufficient thickness so that the second mask layer 350 is completely filled in the recess 344 formed on the upper surface of the third capping layer 342.

Details of the second mask layer 350 are the same as the description of the second mask layer 150 with reference to FIG. 1F.

Referring to FIG. 3C, portions of the low-density pattern region A and the high-density pattern region B which are to form a mask pattern having a pitch smaller than the pitch of the plurality of mask patterns 130a are selectively formed by a double patterning process. A covering mask pattern 360 is formed. 3C illustrates an example in which the mask pattern 360 covering the high density pattern region B is formed. For example, the mask pattern 360 may have a structure in which an anti-reflection film pattern 362 and a photoresist pattern 364 are sequentially stacked. However, the present invention is not limited thereto and may be made of a conventional hard mask pattern forming material.

Referring to FIG. 3D, the second mask layer 350 in the low density pattern region A is etched and removed using the mask pattern 360 as an etch mask. As a result, in the present example, the second mask layer 350 is completely removed from the low density pattern region A, and the second mask layer 350 remains only in the high density pattern region B. FIG.

Although not shown, the third capping layer 342 exposed to the low density pattern region A may be removed.

Referring to FIG. 3E, after removing the mask pattern 360, a fourth capping layer 370 is formed on the third capping layer 342 and the second mask layer 350.

When the third capping layer 342 is removed from the low density pattern region A, the fourth capping layer 370 is formed on the hard mask layer 122 in the low density pattern region A. FIG.

Details of the fourth capping layer 370 are the same as those of the first capping layer 140 with reference to FIG. 1C.

Referring to FIG. 3F, the second mask layer 350 and the fourth capping layer 370 are processed by the CMP process until the first mask pattern 130a is exposed in the same manner as described with reference to FIG. 1G. The formed resultant is planarized to form a plurality of second mask patterns 350a in the high density pattern region B between the plurality of first mask patterns 130a. The plurality of second mask patterns 350a are repeatedly formed at the same pitch as the first pitch 2P _B.

After the plurality of second mask patterns 350a are formed in the high density pattern region B, the third capping layer 342 is disposed in the space between the plurality of first mask patterns 130a in the low density pattern region A. The third capping layer pattern 342b, which is a remaining portion of, and the fourth capping layer pattern 370a, which is a remaining portion of the fourth capping layer 370, remain. In the high-density pattern region B, portions of the third capping layer 342 that are on the first mask pattern 130a are removed and only portions that existed in the space between the first mask patterns 130a remain to be separated from each other. A plurality of third capping layer patterns 342a are formed. The plurality of second mask patterns 350a are respectively disposed in the recessed areas 344 on the third capping layer pattern 342a.

When the third capping layer 342 in the low density pattern region A is removed in the process of FIG. 3A or the process of FIG. 3D, as illustrated in FIG. 4, the plurality of first masks in the low density pattern region A is illustrated. Only the fourth capping layer pattern 370a remains in the space between the patterns 130a.

In the high-density pattern region B, the third capping layer pattern 342a is two thirds respectively contacting the sidewalls of the first mask pattern 130a and the second mask pattern 350a. A capping layer vertical pattern 342a-1 and a third capping layer bottom portion 342a-2 covering the hard mask layer 122 therebetween.

When the thickness of the third capping layer 342 has a value equal to 1/4 of the first pitch 2P _B , the width W ₃ of the third capping layer vertical pattern 342a-1 is equal to the first width. The width W ₁ of the mask pattern 130a may be the same. Thereafter, a fine pattern is formed on the substrate 100 according to a series of processes described with reference to FIGS. 1H to 1K or a series of processes described with reference to FIGS. 2A and 2B.

Although not shown, in the method of forming a fine pattern of the semiconductor device according to the third embodiment of the present invention described with reference to FIGS. 3A to 3F, the first mask pattern is similar to that of the first embodiment in the result of FIG. 3F. By removing the 130a and the second mask pattern 350a, the third capping layer vertical pattern 342a-1, the third capping layer pattern 342b, and the fourth capping layer pattern 370a are used as etching masks. The underlayer can be patterned. Alternatively, in the result of FIG. 3F, the first mask pattern 130a and the second mask pattern 350a are left on the substrate 100, and the third capping layer vertical pattern 342a-1 exposed between them is exposed. The base layer may be patterned by using the first mask pattern 130a and the second mask pattern 350a as an etch mask by removing the third capping layer pattern 342b and the fourth capping layer pattern 370a.

In the method for forming a fine pattern of a semiconductor device according to the present invention, after forming a first mask pattern on the etched film in the first region and the second region having different pattern densities, the plurality of first mask patterns in the first region. A first capping layer pattern is formed to fill a space between two adjacent first mask patterns. The second region may include a second capping layer pattern covering sidewalls of the first mask pattern such that recesses of a predetermined width remain in a space between two adjacent first mask patterns among the plurality of first mask patterns. And a plurality of second mask patterns positioned on the same level as the first mask pattern in the recess area on the second capping layer pattern. The lower layer is patterned by using one selected from the first pattern including the first capping layer pattern and the second capping layer pattern, and the second pattern including the first mask pattern and the second mask pattern.

Accordingly, in order to simultaneously form a plurality of patterns of various sizes and various pitches on the same substrate in order to form a plurality of wiring lines repeatedly formed at a fine pitch using a double patterning process to overcome the resolution limitation in the photolithography process. In addition, it is possible to easily form a desired pattern while preventing problems such as the possibility of film quality remaining and the occurrence of defects, which may be caused by the pattern density or the pattern width difference in each region having a different pattern density or pattern width.

In addition, even when a wiring line is formed using a Cu film having a low resistivity by performing a step of forming an opening in the lower film and forming a wiring line in the opening by patterning a lower film using the first pattern. Instead of designing a separate layout for the engraved pattern required in the drank process, the damascene process is used by using the layout for the formation of the wiring pattern of the relief used when patterning a film capable of forming the pattern by the embossed pattern forming method. Thereby, a plurality of wiring lines repeatedly formed at a fine pitch can be formed. Therefore, even when the fine pitch line is formed by the damascene process, various patterns may be easily implemented in regions having different pattern densities and pattern widths by using the method according to the present invention.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the spirit and scope of the present invention. This is possible.

Claims (22)

Forming an etching target film on the substrate including the first region and the second region; Forming a plurality of first mask patterns on the etched film having a first pattern density in the first region and a second pattern density in the second region; In the first region, a first capping layer pattern is formed to fill a space between two adjacent first mask patterns among the plurality of first mask patterns. In the second region, two adjacent capping layer patterns among the plurality of first mask patterns are formed. A second capping layer pattern covering sidewalls of the first mask pattern such that a recessed region of a predetermined width remains in a space between the first mask patterns, and the first capping layer pattern in the recess region on the second capping layer pattern Forming a plurality of second mask patterns positioned on the same level as the mask pattern, Removing the other one pattern such that a selected one of the first pattern consisting of the first capping layer pattern and the second capping layer pattern and the second pattern consisting of the first mask pattern and the second mask pattern remain; , And etching the etched film using the selected one pattern as an etching mask. The method of claim 1, The step of forming the first capping layer pattern, the second capping layer pattern, and the second mask pattern is Forming a first capping layer covering the plurality of first mask patterns and a space therebetween only in the first region; A second capping layer covering upper surfaces and sidewalls of the plurality of first mask patterns such that recesses of a predetermined width remain in a space between two adjacent first mask patterns among the plurality of first mask patterns in the second region; Forming a, Forming a second mask layer over the second capping layer in the second region so that the recess region is completely filled; A portion of each of the second mask layer, the second capping layer, and the first capping layer is removed until the first mask pattern is exposed, so that the first capping layer pattern, the second mask pattern, and the Forming a first capping layer pattern comprising the step of forming a fine pattern of a semiconductor device. The method of claim 2, And a chemical mechanical polishing (CMP) process to remove a portion of each of the second mask layer, the second capping layer, and the first capping layer. The method of claim 2, The second capping layer is formed in the first region and the second region, respectively, And the second capping layer is formed on the first capping layer in the first region. The method of claim 1, Forming the first capping layer pattern, the second capping layer pattern, and the second mask pattern may include A third capping layer covering upper surfaces and sidewalls of the plurality of first mask patterns such that recesses of a predetermined width remain in a space between two adjacent first mask patterns among the plurality of first mask patterns in the second region; Forming a, Forming a second mask layer over the third capping layer to fill a space between two adjacent first mask patterns among the plurality of first mask patterns in the first region and the second region; Removing the second mask layer from the first region so that the second mask layer remains only in the second region; Forming a fourth capping layer over the third capping layer to completely fill the recess region in the first region; The first capping layer including the remaining portion of the fourth capping layer by removing portions of each of the fourth capping layer, the second mask layer, and the third capping layer until the first mask pattern is exposed. Forming a second capping layer pattern comprising a pattern, the second mask pattern, and the remaining portion of the third capping layer. The method of claim 5, And a CMP process is used to remove a portion of each of the fourth capping layer, the second mask layer, and the third capping layer. The method of claim 5, And the third capping layer is formed only in the second region. The method of claim 5, The third capping layer is formed in the first region and the second region, respectively The fourth capping layer is formed on the third capping layer in the first region. The first capping layer pattern includes a remaining portion of the fourth capping layer and the remaining portion of the third capping layer. The method of claim 1, The etching pattern is a fine pattern forming method of a semiconductor device, characterized in that the insulating film or a conductive film. The method of claim 1, And the first mask pattern and the second mask pattern are each made of a polysilicon film. The method of claim 1, And the first capping layer pattern and the second capping layer pattern are formed of an oxide film or a nitride film, respectively. The method of claim 1, Forming a transient etching buffer layer on the etched film in the first and second regions before forming the first mask pattern, And the first mask pattern is formed on the transient etching buffer layer. The method of claim 12, Forming the first mask pattern is Forming a first mask layer on the transient etching buffer layer in the first region and the second region; Patterning the first mask layer and the transient etching buffer layer to form a plurality of first mask patterns and a plurality of transient etching buffer layer patterns each having a first pattern density and a second pattern density in the first region and the second region, respectively. Method for forming a fine pattern of a semiconductor device comprising the step. The method of claim 12, The transient etching buffer layer is a fine pattern forming method of a semiconductor device, characterized in that made of a material having the same etching characteristics as the second capping layer pattern. The method of claim 12, The transient etching buffer layer is a fine pattern forming method of a semiconductor device, characterized in that consisting of a silicon nitride film or a silicon oxide film. The method of claim 1, Forming a hard mask layer on the etched film after forming the etched film and before forming the first mask pattern; Forming a hard mask pattern by etching the hard mask layer by using the selected one pattern as an etch mask before etching the etched film; And using the selected one pattern and the hard mask pattern as an etch mask to etch the etched film. The method of claim 16, The hard mask layer is a method of forming a fine pattern of a semiconductor device, characterized in that the oxide, nitride, SiON, ACL (amorphous carbon layer), or a combination thereof. The method of claim 1, The etched film is an insulating film, Etching the etched film using the first pattern as an etch mask to etch the etched film to form an etched pattern having a plurality of openings; Forming a metal film in the opening. The method of claim 18, The metal film is a fine pattern forming method of a semiconductor device, characterized in that any one metal selected from the group consisting of Cu, W and Al. The method of claim 18, Forming the metal film Forming a barrier film on the inner wall of the opening; Forming a Cu wiring layer on the barrier film. The method of claim 18, The insulating film is TEOS (tetraethyl orthosilicate), FSG (fluorine silicate glass), SiOC, SiLK or a combination of these, characterized in that the fine pattern manufacturing method of a semiconductor device. The method of claim 1, The etched film is a conductive film, And forming the second pattern as an etch mask to etch the etched film.

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