KR100827526B1 - Method for forming fine pattern of semiconductor device - Google Patents

Abstract

A method for forming a fine pattern of a semiconductor device is provided to overcome the limit of resolution of exposure equipment by forming the fine pattern using a selective etching process. A target etching layer(110), a hard mask layer, and a first oxide layer pattern(130a) are formed on an upper portion of a semiconductor substrate(100). A first poly silicon layer(170) and a second oxide layer(180) are sequentially formed on the whole surface of the semiconductor substrate including the first oxide layer pattern. A planarized second poly silicon layer(190) is formed on the whole upper portion on which the second oxide layer is formed. An etching for planarization is performed until the first oxide layer pattern is exposed. The first oxide layer pattern, the exposed second oxide layer, and the first poly silicon layer on the lower portion of the exposed second oxide layer are selectively etched by using the first and second poly silicon layers as barriers to form a mask pattern. The hard mask layer and the target etching layer are etched by using the mask pattern as an etch mask to form a final pattern.

Description

Method of forming fine pattern of semiconductor device {METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE}

1A to 1C are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the prior art.

2A to 2H are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10, 100: semiconductor substrate 20, 110: etched layer

30: hard mask layer 40: first photosensitive film pattern

45: second photosensitive film pattern 120: first amorphous carbon layer

130: first BPSG oxide film 140: second amorphous carbon layer

150: antireflection film 160: photosensitive film pattern

130a: first BPSG oxide film pattern 170: first polysilicon layer

180: second BPSG oxide film 190: second polysilicon layer

200: mask pattern 110a: final pattern

The present invention relates to a method of forming a fine pattern of a semiconductor device, and to form an oxide film pattern on a semiconductor substrate, and sequentially forming a polysilicon layer and an oxide film having a predetermined thickness on the entire upper portion including the oxide film pattern and the oxide film and By forming a fine pattern by a selective etching process using the difference in the etching selectivity of the polysilicon layer, to overcome the resolution limitation of the exposure equipment to form a pattern having a fine line width to improve the characteristics of the device.

In recent years, as the semiconductor device becomes extremely fine and highly integrated, the overall chip area is increased in proportion to the increase in memory capacity, but the area of the cell area where the pattern of the semiconductor device is formed is decreasing.

Therefore, in order to secure a desired memory capacity, more patterns must be formed in a limited cell region, and thus, a fine pattern having a reduced critical dimension of the pattern is required.

In order to form a pattern having a fine line width, the development of a lithography process is required.

The lithography process is performed by applying a photoresist on a substrate and using an exposure mask on which a circuit pattern is drawn using a laser light source having a wavelength length of 365 nm, 248 nm, 193 nm and 153 nm. After performing the exposure process, a development process is performed to form a pattern.

In the lithography process, the resolution R is determined according to the wavelength λ and the numerical aperture NA of the light source, such as R = k1 × λ / NA.

In the above formula, k1 means a process constant, which has a physical limit, and thus it is almost impossible to reduce the value in a conventional manner, and a photoresist material which is highly reactive to the short wavelength with an exposure apparatus using the short wavelength is used. Since new development is required, it is difficult to form a fine pattern having a line width of a certain degree or less.

1A to 1C are cross-sectional views illustrating a method of forming a fine pattern using a double exposure process.

Referring to FIG. 1A, an etched layer 20, a hard mask layer 30, and a first photosensitive film (not shown) are formed on a semiconductor substrate 10, and the first photosensitive film (not shown) is exposed and developed. The first photosensitive film pattern 40 in the form of a line / space pattern is formed.

Next, the hard mask layer 30 is etched using the first photoresist pattern 40 as a mask, and then the first photoresist pattern 40 is removed.

Referring to FIG. 1B, a second photoresist layer (not shown) is formed over the entire surface, and the second photoresist layer (not shown) is exposed and developed to form a second photoresist layer pattern 45.

Here, the second photoresist layer pattern 45 may be formed in a line / space pattern form so that the center portion of the etched hard mask layer 30a is exposed.

Next, the hard mask layer 30a etched using the second photoresist pattern 45 as a mask is patterned to form a hard mask layer pattern (not shown), and the second photoresist pattern 45 is removed.

Referring to FIG. 1C, the etched layer 20 is etched using the hard mask layer pattern (not shown) as a mask to form an etched layer pattern 20a having a line / space shape.

In the aforementioned method of forming a fine pattern of a semiconductor device according to the related art, it is difficult to form a pattern having a fine line width due to a limitation in the resolution of the exposure equipment. Due to this, there is a problem that misalignment occurs between patterns.

In order to solve the problem, an oxide film pattern is formed on the semiconductor substrate, and a polysilicon layer and an oxide film having a predetermined thickness are sequentially formed on the whole including the oxide film pattern, and then etching is selected between the oxide film and the polysilicon layer. By forming a fine pattern by a selective etching process using a non-difference, to overcome the resolution limitation of the exposure equipment to form a pattern having a fine line width to provide a method of forming a fine pattern of a semiconductor device to improve the characteristics of the device The purpose.

Method for forming a fine pattern of a semiconductor device according to the present invention

Forming an etched layer, a hard mask layer, and a first oxide layer pattern on the semiconductor substrate;

Sequentially forming a first polysilicon layer and a second oxide film having a predetermined thickness on the entire surface of the semiconductor substrate including the first oxide film pattern;

Forming a planarized second polysilicon layer on the entire surface of the resultant,

Planar etching until the first oxide pattern is exposed;

Selectively etching the first oxide layer pattern, the exposed second oxide layer, and the first polysilicon layer below the exposed second oxide layer using the first and second polysilicon layers as a barrier to form a mask pattern; ,

And etching the hard mask layer and the etched layer using the mask pattern as an etch mask to form a final pattern.

The etching layer is formed of an oxide film,

The etching layer is formed to a thickness of 100 to 1000nm at a temperature of 100 to 600 ℃,

The hard mask layer is formed of an amorphous carbon layer,

The hard mask layer is formed to a thickness of 100 to 500nm,

The first oxide pattern and the second oxide film is formed of a BPSG oxide film,

The first oxide film pattern is formed to a thickness of 100 to 1000nm,

The first oxide film pattern is in the form of a line / space of 1: 5,

The first polysilicon layer and the second oxide film are each formed to a thickness of 30 to 50nm,

The second polysilicon layer is formed to a thickness of 100 to 500nm from the second oxide film,

The first polysilicon layer and the second polysilicon layer: an etch selectivity ratio of the first oxide layer pattern and the second oxide layer is 20: 1,

The final pattern is characterized in that the line / space pattern of 1: 1.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2H are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to the present invention.

Referring to FIG. 2A, an etched layer 110, a first amorphous carbon layer 120, and a first borophosphate silica oxide layer 130 are sequentially formed on the semiconductor substrate 100. .

Here, the etching target layer 110 is formed of an oxide film, it is preferable to form a thickness of 100 to 1000nm at a temperature of 100 to 600 ℃.

In addition, the first amorphous carbon layer 120 is formed to serve as a hard mask layer, and is preferably formed to a thickness of 100 to 500 nm.

In addition, the first BPSG oxide film 130 is preferably formed to a thickness of 100 to 1000nm.

Referring to FIG. 2B, a second amorphous carbon layer 140 and an antireflection film 150 are sequentially formed on the first BPSG oxide film 130.

Here, the second amorphous carbon layer 140 is preferably formed to a thickness of 100 to 500nm.

In addition, the anti-reflection film 150 is formed to a thickness of 30 to 40nm, more preferably 31 to 35nm thick.

Next, an ArF photoresist film (not shown) having a thickness of 100 to 500 nm is formed on the antireflection film 150, and then an exposure and development process using an exposure mask defining a line / space pattern of 1: 5 is performed to perform the photoresist pattern. To form 160.

In this case, the exposure process is preferably performed using an ArF (193nm) light source.

The line / space pattern has a pitch of 240 nm and preferably forms a line pattern of 40 nm and a space pattern of 200 nm.

Referring to FIG. 2C, the anti-reflection film 150, the second amorphous carbon layer 140, and the first BPSG oxide film 130 are sequentially etched using the photoresist pattern 160 as a mask to form the first BPSG oxide film pattern 130a. The second amorphous carbon layer 140 pattern and the anti-reflection film 150 pattern are formed.

Referring to FIG. 2D, only the first BPSG oxide layer pattern 130a is left by removing the photoresist layer pattern 160, the anti-reflection layer 150 pattern, and the second amorphous carbon layer 140 pattern.

Referring to FIG. 2E, the first polysilicon layer 170 and the second BPSG oxide layer 180 having a predetermined thickness are sequentially formed on the resultant surface including the first BPSG oxide layer pattern 130a.

Here, the first polysilicon layer 170 and the second BPSG oxide film 180 are each formed to a thickness of 30 to 50 nm, more preferably 35 to 45 nm.

In this case, the first polysilicon layer 170 and the second BPSG oxide layer 180 are formed to have a predetermined thickness along the topology of the lower portion, and the thickness of the second BPSG oxide layer 180 is the line width (CD) of the final pattern. (Critical Dimension).

Next, a planarized second polysilicon layer 190 is formed over the entire resultant.

In this case, the second polysilicon layer 190 may be formed to have a thickness of 100 to 500 nm from an upper portion of the first BPSG oxide layer pattern 130a, and the space between the second BPSG oxide layer 180 may be completely filled.

Referring to FIG. 2F, the planarization process is performed until the first BPSG oxide layer pattern 130a is exposed. In this case, the BPSG oxide film and the polysilicon layer are alternately exposed at a ratio of 1: 1 by the planarization process.
Here, the BPSG oxide film represents the first BPSG oxide film pattern 130a and the second BPSG oxide film 180, and the polysilicon layer represents the first polysilicon layer 170 and the second polysilicon layer 190.

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Referring to FIG. 2G, the first BPSG oxide layer pattern 130a, the second BPSG oxide layer 180, and the second BPSG layer are formed using the first polysilicon layer 170 and the second polysilicon layer 190 exposed at the top thereof as a barrier. The mask pattern 200 is formed by selectively etching the first polysilicon layer 170 under the oxide layer 180.

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Here, since the etch selectivity of the BPSG oxide film and the polysilicon layer is about 20: 1, the polysilicon layer is not removed but remains in a pattern while the BPSG oxide film is removed.

In this case, the second BPSG oxide layer 180 formed between the first polysilicon layer 170 and the second polysilicon layer 190 is not removed.

Referring to FIG. 2H, the first amorphous carbon layer 120 and the etched layer 110 are etched using a mask pattern ('200' of FIG. 2G) as an etch mask to form a final pattern 110a.

Here, the line width of the final pattern 110a is determined according to the thickness of the second BPSG oxide film 180, as shown in FIG. 2E, and is preferably a line / space pattern of 1: 1.

The method of forming a fine pattern of a semiconductor device according to the present invention can form a fine pattern of 1: 1 line / space that overcomes the limit resolution of exposure equipment, and prevents misalignment of the pattern caused by double exposure. There is an effect that the characteristics are improved.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (12)

Forming an etched layer, a hard mask layer, and a first oxide layer pattern on the semiconductor substrate; Sequentially forming a first polysilicon layer and a second oxide film having a predetermined thickness on an entire surface of the semiconductor substrate including the first oxide film pattern; Forming a planarized second polysilicon layer on the entire top of the second oxide film; Planar etching until the first oxide pattern is exposed; Forming a mask pattern by selectively etching the first oxide pattern, the exposed second oxide layer, and the first polysilicon layer under the exposed second oxide layer using the first and second polysilicon layers as barriers; And Etching the hard mask layer and the etched layer using the mask pattern as an etch mask to form a final pattern Method of forming a fine pattern of a semiconductor device comprising a. The method of claim 1, The etching pattern is a fine pattern forming method of a semiconductor device, characterized in that formed by the oxide film. The method of claim 1, The etching layer is a fine pattern forming method of a semiconductor device, characterized in that to form a thickness of 100 to 1000nm at a temperature of 100 to 600 ℃. The method of claim 1, The hard mask layer is a fine pattern forming method of a semiconductor device, characterized in that formed with an amorphous carbon layer. The method of claim 1, The hard mask layer is a fine pattern forming method of a semiconductor device, characterized in that formed in a thickness of 100 to 500nm. The method of claim 1, The first oxide pattern and the second oxide film is a fine pattern forming method of a semiconductor device, characterized in that formed by BPSG oxide film. The method of claim 1, The first oxide film pattern is a fine pattern forming method of a semiconductor device, characterized in that formed in a thickness of 100 to 1000nm. The method of claim 1, The first oxide film pattern is a fine pattern forming method of a semiconductor device, characterized in that 1: 5 line / space form. The method of claim 1, The first polysilicon layer and the second oxide film is a fine pattern forming method of the semiconductor device, characterized in that formed in each of the thickness of 30 to 50nm. The method of claim 1, The second polysilicon layer is formed with a thickness of 100 to 500nm from the top of the second oxide film, the method of forming a fine pattern of a semiconductor device. The method of claim 1, The first polysilicon layer and the second polysilicon layer: an etching selectivity of the first oxide layer pattern and the second oxide layer is 20: 1, characterized in that the etching pattern ratio. The method of claim 1, The final pattern is a fine pattern forming method of a semiconductor device, characterized in that the line / space pattern of 1: 1.

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